The document describes a configurable FIFO with a register interface for configuration. The FIFO has push and pop control signals to store incoming data on the push signal and output data on the pop signal. It also has registers that can be configured through a register interface to set properties like the FIFO depth and read/write pointers. A testbench is created to dynamically simulate and formally verify the FIFO for all possible configurations by generating random test data and configurations and checking the output meets expectations.