The document describes a method for implementing ternary Galois functions using three-dimensional lattice networks with carbon nanotube field emission devices. The method, called Iterative Symmetry Indices Decomposition (ISID), decomposes non-symmetric functions into symmetric and error parts to iteratively produce regular three-dimensional lattice networks that fit within layout constraints while maintaining equal interconnect lengths. Carbon nanotubes and nano-apex tips are used as field emission devices for controlled switching in the lattice networks to perform concurrent ternary computations congestion-free.
A Weighted Duality based Formulation of MIMO SystemsIJERA Editor
This work is based on the modeling and analysis of multiple-input multiple-output (MIMO) system in downlink communication system. We take into account a recent work on the ratio of quadratic forms to formulate the weight matrices of quadratic norm in a duality structure. This enables us to achieve exact solutions for MIMO system operating under Rayleigh fading channels. We outline couple of scenarios dependent on the structure of eigenvalues to investigate the system behavior. The results obtained are validated by means of Monte Carlo simulations.
Concurrent Ternary Galois-based Computation using Nano-apex Multiplexing Nibs...VLSICS Design
Novel realizations of concurrent computations utilizing three-dimensional lattice networks and their corresponding carbon-based field emission controlled switching is introduced in this article. The formalistic ternary nano-based implementation utilizes recent findings in field emission and nano applications which include carbon-based nanotubes and nanotips for three-valued lattice computing via field-emission methods. The presented work implements multi-valued Galois functions by utilizing concurrent nano-based lattice systems, which use two-to-one controlled switching via carbon-based field emission devices by using nano-apex carbon fibers and carbon nanotubes that were presented in the first part of the article. The introduced computational extension utilizing many-to-one carbon field-emission devices will be further utilized in implementing congestion-free architectures within the third part of the article. The emerging nano-based technologies form important directions in low-power compact-size regular lattice realizations, in which carbon-based devices switch less-costly and more-reliably using much less power than silicon-based devices. Applications include low-power design of VLSI circuits for signal processing and control of autonomous robots.
IRJET- Design of Memristor based MultiplierIRJET Journal
This document describes the design of a 4-bit multiplier circuit using memristors. It begins with an introduction to memristors and their advantages over CMOS technology. It then discusses different window functions that can be used for memristor models and selects the Biolek window function. The document implements a 2-bit and 4-bit array multiplier circuit using memristor-CMOS hybrid logic gates. It analyzes the results in LTSpice and finds improvements in area and component count compared to traditional CMOS and other memristor-based designs. The document concludes memristors can help reduce area for multiplier circuits.
COMPARISON OF VOLUME AND DISTANCE CONSTRAINT ON HYPERSPECTRAL UNMIXINGcsandit
The document compares two algorithms for hyperspectral image unmixing - one based on minimum volume constraint and one based on sum of squared distances constraint. It analyzes the performance of the two algorithms under different conditions like flatness of the endmember simplex, effects of initialization, and robustness to noise. The analysis shows that the sum of squared distances constraint performs better than the volume constraint for non-regular simplex shapes and is more robust to random initialization and noise. The comparison provides guidance on which constraint is more suitable for specific hyperspectral unmixing tasks.
This document summarizes the delay and area analysis of a regular 16-bit square root carry select adder (SQRT CSLA) architecture and a proposed modified architecture. The regular design contains five groups of ripple carry adders of different sizes. The delay and area of each group is evaluated based on the delays of basic blocks like full adders and multiplexers. The proposed design aims to reduce area and power by replacing one ripple carry adder in each group with a binary to excess-1 converter, which requires fewer logic gates. Implementation results show the proposed design has lower area and power with a slight increase in delay compared to the regular SQRT CSLA architecture.
Qubit models and methods for improving the performance of software and hardware for
analyzing digital devices through increasing the dimension of the data structures and memory
are proposed. The basic concepts, terminology and definitions necessary for the implementation
of quantum computing when analyzing virtual computers are introduced. The investigation results concerning design and modeling computer systems in a cyberspace based on the use of two-component structure <memory> are presented.
Performance Analysis of Full Adder Based 2- Bit Comparator using Different De...IJEEE
This document presents a performance analysis of different design approaches for a 2-bit comparator circuit based on a full adder module. Three logic styles are evaluated: CMOS logic, Pass Transistor Logic (PTL), and Gate Diffusion Input (GDI) logic. The 2-bit comparator circuit is designed and simulated using each logic style at both 45nm and 90nm process technologies. Simulation results show that the PTL-based comparator has the smallest area of the three designs. In terms of power consumption, PTL performs best at lower voltages below 1.4V, while GDI consumes the least power above 1.4V. Overall, the PTL logic style provides the best trade-off between area
This paper introduces two architectures for modulo 2n+1 adders. The first architecture is based on a sparse carry computation unit that computes only some carries, enabled by a new inverted circular idempotency property. This sparse approach reduces area and power compared to prior proposals while maintaining speed. The second architecture unifies the design of modulo 2n+1 and 2n-1 adders by showing 2n+1 addition can be treated as a subcase of 2n-1 addition with minor extra logic.
A Weighted Duality based Formulation of MIMO SystemsIJERA Editor
This work is based on the modeling and analysis of multiple-input multiple-output (MIMO) system in downlink communication system. We take into account a recent work on the ratio of quadratic forms to formulate the weight matrices of quadratic norm in a duality structure. This enables us to achieve exact solutions for MIMO system operating under Rayleigh fading channels. We outline couple of scenarios dependent on the structure of eigenvalues to investigate the system behavior. The results obtained are validated by means of Monte Carlo simulations.
Concurrent Ternary Galois-based Computation using Nano-apex Multiplexing Nibs...VLSICS Design
Novel realizations of concurrent computations utilizing three-dimensional lattice networks and their corresponding carbon-based field emission controlled switching is introduced in this article. The formalistic ternary nano-based implementation utilizes recent findings in field emission and nano applications which include carbon-based nanotubes and nanotips for three-valued lattice computing via field-emission methods. The presented work implements multi-valued Galois functions by utilizing concurrent nano-based lattice systems, which use two-to-one controlled switching via carbon-based field emission devices by using nano-apex carbon fibers and carbon nanotubes that were presented in the first part of the article. The introduced computational extension utilizing many-to-one carbon field-emission devices will be further utilized in implementing congestion-free architectures within the third part of the article. The emerging nano-based technologies form important directions in low-power compact-size regular lattice realizations, in which carbon-based devices switch less-costly and more-reliably using much less power than silicon-based devices. Applications include low-power design of VLSI circuits for signal processing and control of autonomous robots.
IRJET- Design of Memristor based MultiplierIRJET Journal
This document describes the design of a 4-bit multiplier circuit using memristors. It begins with an introduction to memristors and their advantages over CMOS technology. It then discusses different window functions that can be used for memristor models and selects the Biolek window function. The document implements a 2-bit and 4-bit array multiplier circuit using memristor-CMOS hybrid logic gates. It analyzes the results in LTSpice and finds improvements in area and component count compared to traditional CMOS and other memristor-based designs. The document concludes memristors can help reduce area for multiplier circuits.
COMPARISON OF VOLUME AND DISTANCE CONSTRAINT ON HYPERSPECTRAL UNMIXINGcsandit
The document compares two algorithms for hyperspectral image unmixing - one based on minimum volume constraint and one based on sum of squared distances constraint. It analyzes the performance of the two algorithms under different conditions like flatness of the endmember simplex, effects of initialization, and robustness to noise. The analysis shows that the sum of squared distances constraint performs better than the volume constraint for non-regular simplex shapes and is more robust to random initialization and noise. The comparison provides guidance on which constraint is more suitable for specific hyperspectral unmixing tasks.
This document summarizes the delay and area analysis of a regular 16-bit square root carry select adder (SQRT CSLA) architecture and a proposed modified architecture. The regular design contains five groups of ripple carry adders of different sizes. The delay and area of each group is evaluated based on the delays of basic blocks like full adders and multiplexers. The proposed design aims to reduce area and power by replacing one ripple carry adder in each group with a binary to excess-1 converter, which requires fewer logic gates. Implementation results show the proposed design has lower area and power with a slight increase in delay compared to the regular SQRT CSLA architecture.
Qubit models and methods for improving the performance of software and hardware for
analyzing digital devices through increasing the dimension of the data structures and memory
are proposed. The basic concepts, terminology and definitions necessary for the implementation
of quantum computing when analyzing virtual computers are introduced. The investigation results concerning design and modeling computer systems in a cyberspace based on the use of two-component structure <memory> are presented.
Performance Analysis of Full Adder Based 2- Bit Comparator using Different De...IJEEE
This document presents a performance analysis of different design approaches for a 2-bit comparator circuit based on a full adder module. Three logic styles are evaluated: CMOS logic, Pass Transistor Logic (PTL), and Gate Diffusion Input (GDI) logic. The 2-bit comparator circuit is designed and simulated using each logic style at both 45nm and 90nm process technologies. Simulation results show that the PTL-based comparator has the smallest area of the three designs. In terms of power consumption, PTL performs best at lower voltages below 1.4V, while GDI consumes the least power above 1.4V. Overall, the PTL logic style provides the best trade-off between area
This paper introduces two architectures for modulo 2n+1 adders. The first architecture is based on a sparse carry computation unit that computes only some carries, enabled by a new inverted circular idempotency property. This sparse approach reduces area and power compared to prior proposals while maintaining speed. The second architecture unifies the design of modulo 2n+1 and 2n-1 adders by showing 2n+1 addition can be treated as a subcase of 2n-1 addition with minor extra logic.
A High Throughput CFA AES S-Box with Error Correction CapabilityIOSR Journals
The document describes a proposed method for implementing a fault tolerant Advanced Encryption Standard (AES) using a Hamming error correction code. AES operates by performing rounds of transformations on blocks of data, with the most complex step being the SubBytes transformation which involves calculating multiplicative inverses in GF(28). The proposed method uses composite field arithmetic to more efficiently calculate these inverses. It also applies a (12,8) Hamming error correction code to each byte before and after processing to detect and correct single bit errors caused by radiation events, improving reliability for satellite communications. The parity check bits for the Hamming code are precalculated and stored for the AES S-box lookup tables.
Design and implementation of address generator for wi max deinterleaver on fpgaeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Design of 8-Bit Comparator Using 45nm CMOS TechnologyIJMER
In this paper design of 8- bit binary comparator using 45nm CMOS technology is discussed.
This design needs less area and less number of transistors, also discussed about power and execution time. The
circuit has three output X, Y and Z. X is active high, when A>B, Y is active high when A=B and Z is active high
when both X and Y are active low. Design 1- bit comparator with the help of precharge gate.The design of 1-bit
comparator has been extended to implement an 8-bit comparator by connecting in series with pass
transistor between them. The design has been implemented in Microwind3.1, is tested successfully and
has been validated using Pspice for different measurable parameter.
Layout Design Analysis of CMOS Comparator using 180nm TechnologyIJEEE
Comparator is a very useful and basic arithmetic component of digital system. In the world of technology the demand of portable devices are increasing day by day. This paper presents CMOS design of 1-bit comparator on 180nm technology. The layout of 1-bit comparator has been developed using Automatic and semi-custom techniques. Both the layouts are compared and analyzed in terms of their Power and Area consumption. Automatic layout is generated from its equivalent schematic whereas semi-custom layout is developed manually. The result shows that semi-custom consumes less power as compared to Automatic.
A Review on Channel Routing On VLSI Physical DesignIOSR Journals
This document provides a review and analysis of several algorithms for channel routing in VLSI physical design. It begins with an introduction to channel routing and multi-layer routing models. It then analyzes and summarizes two important two-layer channel routing algorithms: the Efficient Routing Algorithm and the MCC1 and MCC2 algorithms. Next, it discusses a three-layer channel routing algorithm. Finally, it analyzes the MulCh multi-layer channel routing algorithm and its differences from the Chameleon algorithm. Key concepts discussed include horizontal and vertical constraint graphs, net merging techniques, and assigning nets to different routing layers or groups.
An Efficient Image Encomp Process Using LFSRIJTET Journal
Lossless color image compression algorithm based on hierarchical prediction and Context Adaptive Lossless Image Compression (CALIC).The RGB Image decorrelation is done by Reversible Color Transformation (RCT). The output of RCT is Y Component and chrominance component (cucv). The Y Component is encoded by any conventional technique like raster scan predicted method. The Chrominance images (cucv) are encoded by hierarchical prediction. In Hierarchical prediction row wise decomposition and column wise decomposition are performed. From the predicted value in order to obtain the compressed image can apply the arithmetic coding. In that results we can apply the Security for the images using LFSR encryption.
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is an open access international journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Area Efficient and Reduced Pin Count MultipliersCSCJournals
Fully serial multipliers can play an important role in the implementation of DSP algorithms in resource-limited chips such as FPGAs; offering area efficient architectures with a reduced pin count and moderate throughput rates. In this paper two structures that implement the fully serial multiplication operation are presented. One significant aspect of the new designs is that they are systolic and require near communication links only. They are superior in speed and area usage to similar architectures in the literature. The paper also present a new fully serial multiplier optimized for area-time2 efficiency with better performance than available architectures in the open literature.
This document summarizes a research paper that implemented a pipelined CORDIC architecture in Simulink to generate sine and cosine values. The CORDIC algorithm uses only shift and add operations to perform trigonometric and other elementary functions. It was applied here in rotation mode to simultaneously compute sine and cosine of an input angle. A 12-stage pipelined CORDIC architecture was modeled in Simulink. The shifts and constants were hardwired to reduce resources and latency. Testing with an input of 0.6 radians showed accurate outputs for sine and cosine. The implementation demonstrated the utility of Simulink for modeling hardware systems and algorithms like CORDIC.
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
Improving The Performance of Viterbi Decoder using Window System IJECEIAES
An efficient Viterbi decoder is introduced in this paper; it is called Viterbi decoder with window system. The simulation results, over Gaussian channels, are performed from rate 1/2, 1/3 and 2/3 joined to TCM encoder with memory in order of 2, 3. These results show that the proposed scheme outperforms the classical Viterbi by a gain of 1 dB. On the other hand, we propose a function called RSCPOLY2TRELLIS, for recursive systematic convolutional (RSC) encoder which creates the trellis structure of a recursive systematic convolutional encoder from the matrix “H”. Moreover, we present a comparison between the decoding algorithms of the TCM encoder like Viterbi soft and hard, and the variants of the MAP decoder known as BCJR or forward-backward algorithm which is very performant in decoding TCM, but depends on the size of the code, the memory, and the CPU requirements of the application.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
1. The paper presents a state observer method for fast estimation of symmetrical components (positive, negative, zero sequences) of currents and voltages in a three-phase electrical network from measured signal values.
2. The method models the symmetrical components as state variables in a recursive state space model. It then designs a state observer using the model to estimate the symmetrical component states in real-time from the measured signals.
3. The paper provides an example applying the observer to estimate symmetrical components of fault current during a simulated double phase-to-ground fault, demonstrating the basic properties of the observer for use in digital power protection systems.
Modeling Under MATLAB by ANFIS of Three-Phase Tetrahedral Transformer Using i...TELKOMNIKA JOURNAL
This work deals with the modeling of a new three-phase tetrahedral transformer of HV power
supply, which feeds three magnetrons per phase. The design of this new power supply is composed of
three single-phase with magnetic shunt transformers coupling in star; each one is size to feed voltagedoubling
cells, thereby feeds a magnetron. In order to validate the functionality of this power supply, we
simulate it under Matlab-Simulink environment. Thus, we modeled nonlinear inductance using a new
approach of neuro-fuzzy (ANFIS); this method based on the interpolation of the curve B(H) of
ferromagnetic material, the results obtained gives forms of both voltages and currents, which shows that
they are in accordance with those of experimental tests, respecting the conditions recommended by the
magnetron manufacturer
Design of Quaternary Logical Circuit Using Voltage and Current Mode LogicVLSICS Design
This document describes the design of quaternary logical circuits using voltage mode and current mode logic. It summarizes that quaternary voltage mode logic has 51.78% lower power consumption compared to binary, but requires 3 times more transistors. Quaternary current mode logic has lower area than voltage mode, but higher power consumption. Specifically, it presents the design of quaternary logic gates like inverters, MIN, MAX gates for both modes. Comparative analysis shows voltage mode has lower power while current mode has lower area.
Implementation performance analysis of cordiciaemedu
This document discusses the implementation of a CORDIC (COordinate Rotation Digital Computer) algorithm in an OFDM-based wireless local area network receiver. It first provides background on the CORDIC algorithm and its basic principles. It then describes the design of an OFDM-based WLAN transmitter in MATLAB that provides phase angle values to a CORDIC module. This CORDIC module is implemented using VHDL and analyzes the phase angles to compute sine and cosine functions. Simulation results show that the VHDL-implemented CORDIC produces the same output waveforms as MATLAB, validating the accuracy of the hardware implementation.
This document discusses optimizing the gate-level area of digit-serial finite impulse response (FIR) filter designs using multiple constant multiplication (MCM) blocks. It introduces the problem of designing a digit-serial MCM operation with minimal area and presents algorithms to formalize the area optimization problem. Results show the proposed algorithms and digit-serial MCM architectures efficiently design digit-serial MCM operations and FIR filters with reduced area compared to existing approaches.
This paper proposes a parameterized model order reduction technique for efficient global sensitivity analysis of coupled coils over a design space. It uses parameterized models of the electromagnetic matrices and Krylov matrices from the original and adjoint systems, derived using interpolation. Numerical results confirm the efficiency and accuracy of the proposed method for sensitivity analysis across the entire design space of interest.
CONCURRENT TERNARY GALOIS-BASED COMPUTATION USING NANO-APEX MULTIPLEXING NIBS...VLSICS Design
Novel layout realizations for congestion-free three-dimensional lattice networks using the corresponding
carbon-based field emission controlled switching is introduced in this article. The developed nano-based
implementations are performed in three dimensions to perform the required concurrent computations for
which two-dimensional implementations are a special case. The introduced realizations for congestion-free
concurrent computations utilize the field-emission controlled switching devices that were presented in the
first and second parts of the article for the solution of synthesis congestion and by utilizing field-emission
from carbon nanotubes and nanotips. Since the concept of symmetry indices has been related to regular
logic design, a more general method called Iterative Symmetry Indices Decomposition that produces
regular three-dimensional lattice networks via carbon field-emission multiplexing is presented, where one
obtains multi-stage decompositions whenever volume-specific layout constraints have to be satisfied. The
introduced congestion-free nano-based lattice computations form new and important paths in regular
lattice realizations, where applications include low-power IC design for the control of autonomous robots
and for signal processing implementations.
PARALLEL BIJECTIVE PROCESSING OF REGULAR NANO SYSTOLIC GRIDS VIA CARBON FIELD...ijcsit
New implementations for parallel processing applications using reversible systolic networks and the
corresponding nano and field-emission controlled-switching components is introduced. The extensions of
implementations to many-valued field-emission systolic networks using the introduced reversible systolic
architectures are also presented. The developed implementations are performed in the reversible domain to
perform the required parallel computing. The introduced systolic systems utilize recent findings in field
emission and nano applications to implement the function of the basic reversible systolic network using
nano controlled-switching. This includes many-valued systolic computing via carbon nanotubes and carbon
field-emission techniques. The presented realization of reversible circuits can be important for several
reasons including the reduction of power consumption, which is an important specification for the system
design in several future and emerging technologies, and also achieving high performance realizations. The
introduced implementations for non-classical systolic computation are new and interesting for the design
within modern technologies that require optimal design specifications of high speed, minimum power and
minimum size, which includes applications in adiabatic low-power signal processing.
CONCURRENT TERNARY GALOIS-BASED COMPUTATION USING NANO-APEX MULTIPLEXING NIBS...VLSICS Design
This document summarizes a research article that proposes a novel method for implementing ternary Galois logic functions using three-dimensional lattice networks with carbon-based field emission devices. Specifically:
- It introduces a hierarchical design approach that utilizes carbon nanotubes and nano-apex fibers for controlled switching via field emission in three-dimensional lattice networks to realize multi-valued Galois functions concurrently.
- The document reviews fundamentals of ternary Shannon and Davio expansions that are used to formally synthesize the three-dimensional lattice networks. Joining rules are defined to realize non-symmetric functions using variable repetition.
- Carbon field emission devices are proposed to implement the basic controlled switch building block using nano
CONCURRENT TERNARY GALOIS-BASED COMPUTATION USING NANO-APEX MULTIPLEXING NIBS...VLSICS Design
Novel realizations of concurrent computations utilizing three-dimensional lattice networks and their
corresponding carbon-based field emission controlled switching is introduced in this article. The
formalistic ternary nano-based implementation utilizes recent findings in field emission and nano
applications which include carbon-based nanotubes and nanotips for three-valued lattice computing via
field-emission methods. The presented work implements multi-valued Galois functions by utilizing
concurrent nano-based lattice systems, which use two-to-one controlled switching via carbon-based field
emission devices by using nano-apex carbon fibers and carbon nanotubes that were presented in the first
part of the article. The introduced computational extension utilizing many-to-one carbon field-emission
devices will be further utilized in implementing congestion-free architectures within the third part of the
article. The emerging nano-based technologies form important directions in low-power compact-size
regular lattice realizations, in which carbon-based devices switch less-costly and more-reliably using
much less power than silicon-based devices. Applications include low-power design of VLSI circuits for
signal processing and control of autonomous robots.
A High Throughput CFA AES S-Box with Error Correction CapabilityIOSR Journals
The document describes a proposed method for implementing a fault tolerant Advanced Encryption Standard (AES) using a Hamming error correction code. AES operates by performing rounds of transformations on blocks of data, with the most complex step being the SubBytes transformation which involves calculating multiplicative inverses in GF(28). The proposed method uses composite field arithmetic to more efficiently calculate these inverses. It also applies a (12,8) Hamming error correction code to each byte before and after processing to detect and correct single bit errors caused by radiation events, improving reliability for satellite communications. The parity check bits for the Hamming code are precalculated and stored for the AES S-box lookup tables.
Design and implementation of address generator for wi max deinterleaver on fpgaeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Design of 8-Bit Comparator Using 45nm CMOS TechnologyIJMER
In this paper design of 8- bit binary comparator using 45nm CMOS technology is discussed.
This design needs less area and less number of transistors, also discussed about power and execution time. The
circuit has three output X, Y and Z. X is active high, when A>B, Y is active high when A=B and Z is active high
when both X and Y are active low. Design 1- bit comparator with the help of precharge gate.The design of 1-bit
comparator has been extended to implement an 8-bit comparator by connecting in series with pass
transistor between them. The design has been implemented in Microwind3.1, is tested successfully and
has been validated using Pspice for different measurable parameter.
Layout Design Analysis of CMOS Comparator using 180nm TechnologyIJEEE
Comparator is a very useful and basic arithmetic component of digital system. In the world of technology the demand of portable devices are increasing day by day. This paper presents CMOS design of 1-bit comparator on 180nm technology. The layout of 1-bit comparator has been developed using Automatic and semi-custom techniques. Both the layouts are compared and analyzed in terms of their Power and Area consumption. Automatic layout is generated from its equivalent schematic whereas semi-custom layout is developed manually. The result shows that semi-custom consumes less power as compared to Automatic.
A Review on Channel Routing On VLSI Physical DesignIOSR Journals
This document provides a review and analysis of several algorithms for channel routing in VLSI physical design. It begins with an introduction to channel routing and multi-layer routing models. It then analyzes and summarizes two important two-layer channel routing algorithms: the Efficient Routing Algorithm and the MCC1 and MCC2 algorithms. Next, it discusses a three-layer channel routing algorithm. Finally, it analyzes the MulCh multi-layer channel routing algorithm and its differences from the Chameleon algorithm. Key concepts discussed include horizontal and vertical constraint graphs, net merging techniques, and assigning nets to different routing layers or groups.
An Efficient Image Encomp Process Using LFSRIJTET Journal
Lossless color image compression algorithm based on hierarchical prediction and Context Adaptive Lossless Image Compression (CALIC).The RGB Image decorrelation is done by Reversible Color Transformation (RCT). The output of RCT is Y Component and chrominance component (cucv). The Y Component is encoded by any conventional technique like raster scan predicted method. The Chrominance images (cucv) are encoded by hierarchical prediction. In Hierarchical prediction row wise decomposition and column wise decomposition are performed. From the predicted value in order to obtain the compressed image can apply the arithmetic coding. In that results we can apply the Security for the images using LFSR encryption.
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is an open access international journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Area Efficient and Reduced Pin Count MultipliersCSCJournals
Fully serial multipliers can play an important role in the implementation of DSP algorithms in resource-limited chips such as FPGAs; offering area efficient architectures with a reduced pin count and moderate throughput rates. In this paper two structures that implement the fully serial multiplication operation are presented. One significant aspect of the new designs is that they are systolic and require near communication links only. They are superior in speed and area usage to similar architectures in the literature. The paper also present a new fully serial multiplier optimized for area-time2 efficiency with better performance than available architectures in the open literature.
This document summarizes a research paper that implemented a pipelined CORDIC architecture in Simulink to generate sine and cosine values. The CORDIC algorithm uses only shift and add operations to perform trigonometric and other elementary functions. It was applied here in rotation mode to simultaneously compute sine and cosine of an input angle. A 12-stage pipelined CORDIC architecture was modeled in Simulink. The shifts and constants were hardwired to reduce resources and latency. Testing with an input of 0.6 radians showed accurate outputs for sine and cosine. The implementation demonstrated the utility of Simulink for modeling hardware systems and algorithms like CORDIC.
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
Improving The Performance of Viterbi Decoder using Window System IJECEIAES
An efficient Viterbi decoder is introduced in this paper; it is called Viterbi decoder with window system. The simulation results, over Gaussian channels, are performed from rate 1/2, 1/3 and 2/3 joined to TCM encoder with memory in order of 2, 3. These results show that the proposed scheme outperforms the classical Viterbi by a gain of 1 dB. On the other hand, we propose a function called RSCPOLY2TRELLIS, for recursive systematic convolutional (RSC) encoder which creates the trellis structure of a recursive systematic convolutional encoder from the matrix “H”. Moreover, we present a comparison between the decoding algorithms of the TCM encoder like Viterbi soft and hard, and the variants of the MAP decoder known as BCJR or forward-backward algorithm which is very performant in decoding TCM, but depends on the size of the code, the memory, and the CPU requirements of the application.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
1. The paper presents a state observer method for fast estimation of symmetrical components (positive, negative, zero sequences) of currents and voltages in a three-phase electrical network from measured signal values.
2. The method models the symmetrical components as state variables in a recursive state space model. It then designs a state observer using the model to estimate the symmetrical component states in real-time from the measured signals.
3. The paper provides an example applying the observer to estimate symmetrical components of fault current during a simulated double phase-to-ground fault, demonstrating the basic properties of the observer for use in digital power protection systems.
Modeling Under MATLAB by ANFIS of Three-Phase Tetrahedral Transformer Using i...TELKOMNIKA JOURNAL
This work deals with the modeling of a new three-phase tetrahedral transformer of HV power
supply, which feeds three magnetrons per phase. The design of this new power supply is composed of
three single-phase with magnetic shunt transformers coupling in star; each one is size to feed voltagedoubling
cells, thereby feeds a magnetron. In order to validate the functionality of this power supply, we
simulate it under Matlab-Simulink environment. Thus, we modeled nonlinear inductance using a new
approach of neuro-fuzzy (ANFIS); this method based on the interpolation of the curve B(H) of
ferromagnetic material, the results obtained gives forms of both voltages and currents, which shows that
they are in accordance with those of experimental tests, respecting the conditions recommended by the
magnetron manufacturer
Design of Quaternary Logical Circuit Using Voltage and Current Mode LogicVLSICS Design
This document describes the design of quaternary logical circuits using voltage mode and current mode logic. It summarizes that quaternary voltage mode logic has 51.78% lower power consumption compared to binary, but requires 3 times more transistors. Quaternary current mode logic has lower area than voltage mode, but higher power consumption. Specifically, it presents the design of quaternary logic gates like inverters, MIN, MAX gates for both modes. Comparative analysis shows voltage mode has lower power while current mode has lower area.
Implementation performance analysis of cordiciaemedu
This document discusses the implementation of a CORDIC (COordinate Rotation Digital Computer) algorithm in an OFDM-based wireless local area network receiver. It first provides background on the CORDIC algorithm and its basic principles. It then describes the design of an OFDM-based WLAN transmitter in MATLAB that provides phase angle values to a CORDIC module. This CORDIC module is implemented using VHDL and analyzes the phase angles to compute sine and cosine functions. Simulation results show that the VHDL-implemented CORDIC produces the same output waveforms as MATLAB, validating the accuracy of the hardware implementation.
This document discusses optimizing the gate-level area of digit-serial finite impulse response (FIR) filter designs using multiple constant multiplication (MCM) blocks. It introduces the problem of designing a digit-serial MCM operation with minimal area and presents algorithms to formalize the area optimization problem. Results show the proposed algorithms and digit-serial MCM architectures efficiently design digit-serial MCM operations and FIR filters with reduced area compared to existing approaches.
This paper proposes a parameterized model order reduction technique for efficient global sensitivity analysis of coupled coils over a design space. It uses parameterized models of the electromagnetic matrices and Krylov matrices from the original and adjoint systems, derived using interpolation. Numerical results confirm the efficiency and accuracy of the proposed method for sensitivity analysis across the entire design space of interest.
Similar to CONCURRENT TERNARY GALOIS-BASED COMPUTATION USING NANO-APEX MULTIPLEXING NIBS OF REGULAR THREE-DIMENSIONAL NETWORKS, PART III: LAYOUT CONGESTIONFREE EFFECTUATION
CONCURRENT TERNARY GALOIS-BASED COMPUTATION USING NANO-APEX MULTIPLEXING NIBS...VLSICS Design
Novel layout realizations for congestion-free three-dimensional lattice networks using the corresponding
carbon-based field emission controlled switching is introduced in this article. The developed nano-based
implementations are performed in three dimensions to perform the required concurrent computations for
which two-dimensional implementations are a special case. The introduced realizations for congestion-free
concurrent computations utilize the field-emission controlled switching devices that were presented in the
first and second parts of the article for the solution of synthesis congestion and by utilizing field-emission
from carbon nanotubes and nanotips. Since the concept of symmetry indices has been related to regular
logic design, a more general method called Iterative Symmetry Indices Decomposition that produces
regular three-dimensional lattice networks via carbon field-emission multiplexing is presented, where one
obtains multi-stage decompositions whenever volume-specific layout constraints have to be satisfied. The
introduced congestion-free nano-based lattice computations form new and important paths in regular
lattice realizations, where applications include low-power IC design for the control of autonomous robots
and for signal processing implementations.
PARALLEL BIJECTIVE PROCESSING OF REGULAR NANO SYSTOLIC GRIDS VIA CARBON FIELD...ijcsit
New implementations for parallel processing applications using reversible systolic networks and the
corresponding nano and field-emission controlled-switching components is introduced. The extensions of
implementations to many-valued field-emission systolic networks using the introduced reversible systolic
architectures are also presented. The developed implementations are performed in the reversible domain to
perform the required parallel computing. The introduced systolic systems utilize recent findings in field
emission and nano applications to implement the function of the basic reversible systolic network using
nano controlled-switching. This includes many-valued systolic computing via carbon nanotubes and carbon
field-emission techniques. The presented realization of reversible circuits can be important for several
reasons including the reduction of power consumption, which is an important specification for the system
design in several future and emerging technologies, and also achieving high performance realizations. The
introduced implementations for non-classical systolic computation are new and interesting for the design
within modern technologies that require optimal design specifications of high speed, minimum power and
minimum size, which includes applications in adiabatic low-power signal processing.
CONCURRENT TERNARY GALOIS-BASED COMPUTATION USING NANO-APEX MULTIPLEXING NIBS...VLSICS Design
This document summarizes a research article that proposes a novel method for implementing ternary Galois logic functions using three-dimensional lattice networks with carbon-based field emission devices. Specifically:
- It introduces a hierarchical design approach that utilizes carbon nanotubes and nano-apex fibers for controlled switching via field emission in three-dimensional lattice networks to realize multi-valued Galois functions concurrently.
- The document reviews fundamentals of ternary Shannon and Davio expansions that are used to formally synthesize the three-dimensional lattice networks. Joining rules are defined to realize non-symmetric functions using variable repetition.
- Carbon field emission devices are proposed to implement the basic controlled switch building block using nano
CONCURRENT TERNARY GALOIS-BASED COMPUTATION USING NANO-APEX MULTIPLEXING NIBS...VLSICS Design
Novel realizations of concurrent computations utilizing three-dimensional lattice networks and their
corresponding carbon-based field emission controlled switching is introduced in this article. The
formalistic ternary nano-based implementation utilizes recent findings in field emission and nano
applications which include carbon-based nanotubes and nanotips for three-valued lattice computing via
field-emission methods. The presented work implements multi-valued Galois functions by utilizing
concurrent nano-based lattice systems, which use two-to-one controlled switching via carbon-based field
emission devices by using nano-apex carbon fibers and carbon nanotubes that were presented in the first
part of the article. The introduced computational extension utilizing many-to-one carbon field-emission
devices will be further utilized in implementing congestion-free architectures within the third part of the
article. The emerging nano-based technologies form important directions in low-power compact-size
regular lattice realizations, in which carbon-based devices switch less-costly and more-reliably using
much less power than silicon-based devices. Applications include low-power design of VLSI circuits for
signal processing and control of autonomous robots.
Concurrent Ternary Galois-based Computation using Nano-apex Multiplexing Nibs...VLSICS Design
New implementations within concurrent processing using three-dimensional lattice networks via nano carbon-based field emission controlled-switching is introduced in this article. The introduced nano-based three-dimensional networks utilize recent findings in nano-apex field emission to implement the concurrent functionality of lattice networks. The concurrent implementation of ternary Galois functions using nano threedimensional lattice networks is performed by using carbon field-emission switching devices via nano-apex carbon fibers and nanotubes. The presented work in this part of the article presents important basic background and fundamentals with regards to lattice computing and carbon field-emission that will be utilized within the follow-up works in the second and third parts of the article. The introduced nano-based three-dimensional lattice implementations form new and important directions within three-dimensional design in nanotechnologies that require optimal specifications of high regularity, predictable timing, high testability, fault localization, self-repair, minimum size, and minimum power consumption.
New implementations for concurrent computing applications of 3D networks using corresponding nano and field-emission controlled-switching components are introduced. The developed implementations are performed within 3D lattice-based systems to perform the required concurrent computing. The introduced 3D systems utilize recent findings in field-emission and nano applications to implement the function of the basic 3D lattice networks using nano controlled-switching. This includes ternary lattice computing via carbon nanotubes and carbon field-emission techniques. The presented realization of lattice networks can be important for several reasons including the reduction of power consumption, which is an important specification for the system design in several future and emerging technologies, and in achieving high performance and reliability realizations. The introduced implementations for 3D lattice computations, with 2D lattice networks as a special case, are also important for the design within modern technologies that require optimal design specifications of high speed, high regularity and ease-of-manufacturability, such as in highly-reliable error-correcting signal processing applications.
International Journal of Computer Science & Information Technology (IJCSIT) ijcsit
New implementations for concurrent computing applications of 3D networks using corresponding nano and field-emission controlled-switching components are introduced. The developed implementations are performed within 3D lattice-based systems to perform the required concurrent computing. The introduced 3D systems utilize recent findings in field-emission and nano applications to implement the function of the basic 3D lattice networks using nano controlled-switching. This includes ternary lattice computing via carbon nanotubes and carbon field-emission techniques. The presented realization of lattice networks can be important for several reasons including the reduction of power consumption, which is an important specification for the system design in several future and emerging technologies, and in achieving high performance and reliability realizations. The introduced implementations for 3D lattice computations, with 2D lattice networks as a special case, are also important for the design within modern technologies that require optimal design specifications of high speed, high regularity and ease-of-manufacturability, such as in highly-reliable error-correcting signal processing applications.
Design and Fabrication of the Novel Miniaturized Microstrip Coupler 3dB Using...TELKOMNIKA JOURNAL
In this work, a novel miniaturized compact coupler using the shunt-stubs artificial transimission
lines with high and low impedances is presented. Design of the proposed coupler is accomplished by
modifying the length and impedance of the branch lines in the conventional structure with the planar
resonators in order to achieve branch line coupler with compact size and improvement of the
performances. First part of this work is focusing on the theorical study of the proposed resonators where
the equations are obtained. Secondly, the proposed coupler is designed on FR4 susbtrate, and simulated
by using the EM Solver (ADS from Agilent technologies and CST microwave studio) in order to operate in
the ISM band. The obtained results show good agreement with the simulations and the coupler shows a
good perfo6rmance in the hole bandwidth. The size of the proposed coupler is reduced around 50%
compared to the conventional design. The last part conerns the fabrication and test of the proposed
coupler. The measurement and simulation results are in good agreements.
DWS MODELING OF MULTICONDUCTOR TRANSMISSION LINESPiero Belforte
This document summarizes different methods for simulating multiconductor transmission lines (MTL) using the DWM simulation tool SPRINT. It describes the general modal method, which applies to nonhomogeneous and asymmetrical structures using modal voltages and currents. For homogeneous structures, it presents the Marx method and tridiagonal method. It compares SPRINT's implementation of the modal and Marx methods for a simple 3-conductor line, finding good agreement with SPICE. SPRINT allows more efficient simulation of large MTL networks compared to SPICE.
The use of reversible logic gates in the design of residue number systems IJECEIAES
Reversible computing is an emerging technique to achieve ultra-low-power circuits. Reversible arithmetic circuits allow for achieving energy-efficient high-performance computational systems. Residue number systems (RNS) provide parallel and fault-tolerant additions and multiplications without carry propagation between residue digits. The parallelism and fault-tolerance features of RNS can be leveraged to achieve high-performance reversible computing. This paper proposed RNS full reversible circuits, including forward converters, modular adders and multipliers, and reverse converters used for a class of RNS moduli sets with the composite form {2 k p , 2 -1}. Modulo 2 n -1, 2 n , and 2 n +1 adders and multipliers were designed using reversible gates. Besides, reversible forward and reverse converters for the 3-moduli set {2 n -1, 2 n+k n , 2 +1} have been designed. The proposed RNS- based reversible computing approach has been applied for consecutive multiplications with an improvement of above 15% in quantum cost after the twelfth iteration, and above 27% in quantum depth after the ninth iteration. The findings show that the use of the proposed RNS-based reversible computing in convolution results in a significant improvement in quantum depth in comparison to conventional methods based on weighted binary adders and multipliers.
Modelling Quantum Transport in Nanostructuresiosrjce
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
This document summarizes three methods for modeling quantum transport in nanostructures:
1) The non-equilibrium Green's function (NEGF) method provides a rigorous description of quantum transport by solving Poisson's equation and the quantum transport solver based on NEGF formalism self-consistently.
2) The recursive Green's function method computes the Green's function recursively without full matrix inversion, reducing computational efforts.
3) The Gauss estimation method computes spectral coefficients representing the Green's function to estimate current at discrete longitudinal field values rather than integrating over the entire field.
2-Dimensional and 3-Dimesional Electromagnetic Fields Using Finite element me...IOSR Journals
This document describes using the finite element method to model 2D and 3D electromagnetic fields. It discusses modeling a quarter section of a rectangular coaxial line with triangular elements. It describes constructing the matrices for each element and combining them to solve the overall matrix equation. The document outlines implementing FEM in MATLAB, including generating meshes, adding sources, and solving the resulting matrices. Several examples are presented of using a graphical user interface created in MATLAB to calculate fields from configurations like straight wires, bent wires, solenoids, and square loops using FEM techniques.
This document describes a novel design of ternary logic gates using carbon nanotube field-effect transistors (CNTFETs). The authors propose a CNTFET-based design for ternary logic gates that eliminates the need for large off-chip resistors used in previous designs. Simulation results show the proposed ternary logic gates consume significantly lower power and delay compared to previous resistive-load CNTFET gate implementations. When used in arithmetic circuits like a full adder and multiplier, the proposed ternary gates combined with binary gates can reduce power delay product by over 90%.
A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Tec...VLSICS Design
Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.
Design of a Selective Filter based on 2D Photonic Crystals Materials IJECEIAES
Two dimensional finite differences temporal domain (2D-FDTD) numerical simulations are performed in cartesian coordinate system to determine the dispersion diagrams of transverse electric (TE) of a two-dimension photonic crystal (PC) with triangular lattice. The aim of this work is to design a filter with maximum spectral response close to the frequency 1.55 μm. To achieve this frequency, selective filters PC are formed by combination of three waveguides W 1 K A wherein the air holes have of different normalized radii respectively r 1 /a=0.44, r 2 /a=0.288 and r /a= 0.3292 (a: is the periodicity of the lattice with value 0.48 μm). Best response is obtained when we insert three small cylindrical cavities (with normalized radius of 0.17) between the two half-planes of photonic crystal strong lateral confinement.
Automatic modulation classification ased b deep learning with mixed feature IJECEIAES
The automatic modulation classification (AMC) plays an important and necessary role in the truncated wireless signal, which is used in modern communications. The proposed convolution neural network (CNN) for AMC is based on a method of feature expansion by integrating I/Q (time form) with r/Ɵ (polar form) in order to take advantage of two things: first, feature expansion helps to increase features; the second is that converting to polar form helps to increase classification accuracy for higher order modulation due to diversity in polar form. CNN consists of six blocks. Each block contains symmetric and asymmetric filters, as well as max and average pooling filters. This paper uses DeepSig: RadioML which is a dataset of 24 modulation classes. The proposed network has outperformed many recent papers in terms of classification accuracy for 24 modulation types, with a classification accuracy of up to 96.06 at an SNR=20 dB.
International journal of applied sciences and innovation vol 2015 - no 1 - ...sophiabelthome
This document presents a finite element model using cubic elements to characterize electromagnetic fields in a 3D waveguide transmission line. It uses the free and open-source GNU Octave software to perform the electromagnetic analysis and solve the Maxwell equations. The cubic finite element discretization is shown to provide an efficient solution with sparse matrices, reducing computational cost. Numerical results demonstrate good agreement between the cubic element model and analytical solutions for the electric and magnetic fields in the waveguide.
A NOVEL FULL ADDER CELL BASED ON CARBON NANOTUBE FIELD EFFECT TRANSISTORSVLSICS Design
Presenting a novel full adder cell will be increases all the arithmetic logic unit performance. In this paper, We present two new full adder cell designs using carbon nanotube field effect transistors (CNTFETs). In the first design we have 42 transistors and 5 pull-up resistance so that we have achieved an improvement in the output parameters. Simulations were carried out using HSPICE based on the CNTFET model with 0.9V VDD. The denouments results in that we have a considerable improvement in power, Delay and power delay product than the previous works.
This paper proposes a parameterized model order reduction technique for efficient global sensitivity analysis of coupled coils over a design space. It uses parameterized models of the electromagnetic matrices and Krylov matrices from the original and adjoint systems, derived using interpolation. Numerical results confirm the efficiency and accuracy of the proposed method for sensitivity analysis across the full design parameter space.
Similar to CONCURRENT TERNARY GALOIS-BASED COMPUTATION USING NANO-APEX MULTIPLEXING NIBS OF REGULAR THREE-DIMENSIONAL NETWORKS, PART III: LAYOUT CONGESTIONFREE EFFECTUATION (20)
Particle Swarm Optimization–Long Short-Term Memory based Channel Estimation w...IJCNCJournal
Paper Title
Particle Swarm Optimization–Long Short-Term Memory based Channel Estimation with Hybrid Beam Forming Power Transfer in WSN-IoT Applications
Authors
Reginald Jude Sixtus J and Tamilarasi Muthu, Puducherry Technological University, India
Abstract
Non-Orthogonal Multiple Access (NOMA) helps to overcome various difficulties in future technology wireless communications. NOMA, when utilized with millimeter wave multiple-input multiple-output (MIMO) systems, channel estimation becomes extremely difficult. For reaping the benefits of the NOMA and mm-Wave combination, effective channel estimation is required. In this paper, we propose an enhanced particle swarm optimization based long short-term memory estimator network (PSOLSTMEstNet), which is a neural network model that can be employed to forecast the bandwidth required in the mm-Wave MIMO network. The prime advantage of the LSTM is that it has the capability of dynamically adapting to the functioning pattern of fluctuating channel state. The LSTM stage with adaptive coding and modulation enhances the BER.PSO algorithm is employed to optimize input weights of LSTM network. The modified algorithm splits the power by channel condition of every single user. Participants will be first sorted into distinct groups depending upon respective channel conditions, using a hybrid beamforming approach. The network characteristics are fine-estimated using PSO-LSTMEstNet after a rough approximation of channels parameters derived from the received data.
Keywords
Signal to Noise Ratio (SNR), Bit Error Rate (BER), mm-Wave, MIMO, NOMA, deep learning, optimization.
Volume URL: https://airccse.org/journal/ijc2022.html
Abstract URL:https://aircconline.com/abstract/ijcnc/v14n5/14522cnc05.html
Pdf URL: https://aircconline.com/ijcnc/V14N5/14522cnc05.pdf
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Here's where you can reach us : ijcnc@airccse.org or ijcnc@aircconline.com
Accident detection system project report.pdfKamal Acharya
The Rapid growth of technology and infrastructure has made our lives easier. The
advent of technology has also increased the traffic hazards and the road accidents take place
frequently which causes huge loss of life and property because of the poor emergency facilities.
Many lives could have been saved if emergency service could get accident information and
reach in time. Our project will provide an optimum solution to this draw back. A piezo electric
sensor can be used as a crash or rollover detector of the vehicle during and after a crash. With
signals from a piezo electric sensor, a severe accident can be recognized. According to this
project when a vehicle meets with an accident immediately piezo electric sensor will detect the
signal or if a car rolls over. Then with the help of GSM module and GPS module, the location
will be sent to the emergency contact. Then after conforming the location necessary action will
be taken. If the person meets with a small accident or if there is no serious threat to anyone’s
life, then the alert message can be terminated by the driver by a switch provided in order to
avoid wasting the valuable time of the medical rescue team.
Determination of Equivalent Circuit parameters and performance characteristic...pvpriya2
Includes the testing of induction motor to draw the circle diagram of induction motor with step wise procedure and calculation for the same. Also explains the working and application of Induction generator
A high-Speed Communication System is based on the Design of a Bi-NoC Router, ...DharmaBanothu
The Network on Chip (NoC) has emerged as an effective
solution for intercommunication infrastructure within System on
Chip (SoC) designs, overcoming the limitations of traditional
methods that face significant bottlenecks. However, the complexity
of NoC design presents numerous challenges related to
performance metrics such as scalability, latency, power
consumption, and signal integrity. This project addresses the
issues within the router's memory unit and proposes an enhanced
memory structure. To achieve efficient data transfer, FIFO buffers
are implemented in distributed RAM and virtual channels for
FPGA-based NoC. The project introduces advanced FIFO-based
memory units within the NoC router, assessing their performance
in a Bi-directional NoC (Bi-NoC) configuration. The primary
objective is to reduce the router's workload while enhancing the
FIFO internal structure. To further improve data transfer speed,
a Bi-NoC with a self-configurable intercommunication channel is
suggested. Simulation and synthesis results demonstrate
guaranteed throughput, predictable latency, and equitable
network access, showing significant improvement over previous
designs
Build the Next Generation of Apps with the Einstein 1 Platform.
Rejoignez Philippe Ozil pour une session de workshops qui vous guidera à travers les détails de la plateforme Einstein 1, l'importance des données pour la création d'applications d'intelligence artificielle et les différents outils et technologies que Salesforce propose pour vous apporter tous les bénéfices de l'IA.
Applications of artificial Intelligence in Mechanical Engineering.pdfAtif Razi
Historically, mechanical engineering has relied heavily on human expertise and empirical methods to solve complex problems. With the introduction of computer-aided design (CAD) and finite element analysis (FEA), the field took its first steps towards digitization. These tools allowed engineers to simulate and analyze mechanical systems with greater accuracy and efficiency. However, the sheer volume of data generated by modern engineering systems and the increasing complexity of these systems have necessitated more advanced analytical tools, paving the way for AI.
AI offers the capability to process vast amounts of data, identify patterns, and make predictions with a level of speed and accuracy unattainable by traditional methods. This has profound implications for mechanical engineering, enabling more efficient design processes, predictive maintenance strategies, and optimized manufacturing operations. AI-driven tools can learn from historical data, adapt to new information, and continuously improve their performance, making them invaluable in tackling the multifaceted challenges of modern mechanical engineering.
Properties of Fluids, Fluid Statics, Pressure MeasurementIndrajeet sahu
Properties of Fluids: Density, viscosity, surface tension, compressibility, and specific gravity define fluid behavior.
Fluid Statics: Studies pressure, hydrostatic pressure, buoyancy, and fluid forces on surfaces.
Pressure at a Point: In a static fluid, the pressure at any point is the same in all directions. This is known as Pascal's principle. The pressure increases with depth due to the weight of the fluid above.
Hydrostatic Pressure: The pressure exerted by a fluid at rest due to the force of gravity. It can be calculated using the formula P=ρghP=ρgh, where PP is the pressure, ρρ is the fluid density, gg is the acceleration due to gravity, and hh is the height of the fluid column above the point in question.
Buoyancy: The upward force exerted by a fluid on a submerged or partially submerged object. This force is equal to the weight of the fluid displaced by the object, as described by Archimedes' principle. Buoyancy explains why objects float or sink in fluids.
Fluid Pressure on Surfaces: The analysis of pressure forces on surfaces submerged in fluids. This includes calculating the total force and the center of pressure, which is the point where the resultant pressure force acts.
Pressure Measurement: Manometers, barometers, pressure gauges, and differential pressure transducers measure fluid pressure.
Properties of Fluids, Fluid Statics, Pressure Measurement
CONCURRENT TERNARY GALOIS-BASED COMPUTATION USING NANO-APEX MULTIPLEXING NIBS OF REGULAR THREE-DIMENSIONAL NETWORKS, PART III: LAYOUT CONGESTIONFREE EFFECTUATION
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol 11, No 6, December 2020
DOI: 10.5121/vlsic.2020.11602 21
CONCURRENT TERNARY GALOIS-BASED
COMPUTATION USING NANO-APEX MULTIPLEXING
NIBS OF REGULAR THREE-DIMENSIONAL
NETWORKS, PART III: LAYOUT CONGESTION-
FREE EFFECTUATION
Anas N. Al-Rabadi
Department of Computer Engineering, The University of Jordan, Amman – Jordan &
Department of Renewable Energy Engineering, Isra University – Jordan
ABSTRACT
Novel layout realizations for congestion-free three-dimensional lattice networks using the corresponding
carbon-based field emission controlled switching is introduced in this article. The developed nano-based
implementations are performed in three dimensions to perform the required concurrent computations for
which two-dimensional implementations are a special case. The introduced realizations for congestion-free
concurrent computations utilize the field-emission controlled switching devices that were presented in the
first and second parts of the article for the solution of synthesis congestion and by utilizing field-emission
from carbon nanotubes and nanotips. Since the concept of symmetry indices has been related to regular
logic design, a more general method called Iterative Symmetry Indices Decomposition that produces
regular three-dimensional lattice networks via carbon field-emission multiplexing is presented, where one
obtains multi-stage decompositions whenever volume-specific layout constraints have to be satisfied. The
introduced congestion-free nano-based lattice computations form new and important paths in regular
lattice realizations, where applications include low-power IC design for the control of autonomous robots
and for signal processing implementations.
KEYWORDS
Concurrency, Iterative symmetry decomposition, Layout congestion, Lattice networks, Nano-apex
emission.
1. INTRODUCTION
Several various methods that are used for functional decomposition are considered as major
techniques that are widely used for the synthesis of binary and multi-valued logic circuits and
systems [2], [15], [18], [20]-[21], [25]. For example, logic circuits were synthesized using
symmetric indices that characterize certain function symmetries like in symmetric networks,
Akers arrays and lattice networks [1]-[4], [7], [21]. Other decomposition methods that have been
widely utilized to synthesize logic functions utilize function expansions such as in decision trees
and diagrams [2], [10], [23], [27]. Other synthesis methods include the use of various synthesis
techniques to produce multi-level sum-of-products (SOP) or exclusive-sum-of-products (ESOP)
forms for logic circuits and systems [21].
As was previously presented in the first and second parts of the article, regular interconnects
generally lead to cheap implementations and high densities, where higher density implies both
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol 11, No 6, December 2020
22
higher performance and lower overhead for support components. In addition, the property of high
regularity leads to important design consequences such as predictable timing, high testability, fast
fault localization and self-repair, and the minimization of power consumption [2], [24], [26]. In
this paper, a general processing that produces regular three-dimensional lattice networks via
carbon field-emission using the corresponding operations on symmetry indices is presented. A
decomposition called the Iterative Symmetry Indices Decomposition (ISID) is implemented for
the three-dimensional design of lattice networks, where the synthesis of the special case of
regular two-dimensional lattice networks via field-emission techniques using ISID is also
presented. The new method can be used for the synthesis of ternary functions using nano-based
three-dimensional regular lattice networks whenever volume-specific layout constraints have to
be satisfied.
Field electron emission is the emission of electrons from the surface of a cathode under the
influence of the applied electric field which is strongly dependent upon the work function of the
emitting material [9], [16], [19], where the general form of the governing Fowler-Nordheim
equation [17] was produced [16]. Carbon nanotubes (CNTs) are important emerging structures
within the highly-expanding science and engineering field of nanotechnology [5], [8], [12], [22],
[29]-[30], which have several attractive engineering properties [6], [12]-[14], [22]. Carbon field-
emission can be achieved through using various types of single-walled and multi-walled CNTs
and also by using carbon nano-apex tips that were presented and utilized in the first and second
parts of the article. Figure 1 illustrates the layered layout of the introduced carbon field emission
– based system design method that is used in this article.
Three-Dimensional ISID-Based Lattice Realizations
Field Emission-Based Circuits
Carbon-Based Field Emission Devices
Field-Emission Physics
Galois Algebra
Figure 1. The introduced hierarchy for the utilized nano-based system realization.
The research findings and implementations in this article are original and new, and are performed
for the first time for the implementation of ternary Galois functions utilizing ISID-based
concurrent nano-based lattice systems that use carbon field-emission devices which are based on
the field-emission from nano-apex carbon fibers and nanotubes. The operations of the ternary
ISID-based three-dimensional lattice architectures utilizing the introduced nano-based systems
are also demonstrated.
The remainder of this article is organized as follows: Fundamentals of the important concept of
symmetry indices and their application within lattice networks are presented in Section 2. The
utilization of ISID-based decomposition for the synthesis of two-dimensional and three-
dimensional lattice networks is presented in Section 3. The utilization of the carbon field-
emission devices in controlled switching and multiple-valued computing is presented in Section
4. The implementation of controlled switching that use carbon field emission-based devices
within ISID-based layout congestion-free lattice architectures via carbon field - emission
multiplexing is introduced in Section 5. Conclusions and future work are presented in Section 6.
2. BASICS OF SYMMETRY INDICES
It is well-known in logic synthesis that certain classes of logic functions exhibit specific types of
symmetries [2], [11], [21], [28]. Such symmetries have various types that include symmetries
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol 11, No 6, December 2020
23
between different functions under negation, symmetries within a logic function under the
negation of its variables, and symmetries within a logic function under the permutation of its
variables [21]. One method to characterize a symmetry that might exist in a logic function is
performed by using symmetry indices.
Definition 1. A single index symmetric function, denoted as Sk
(x1, x2,…, xn) has value 1 when
exactly k of its n inputs are equal to 1, and exactly (n - k) of its remaining inputs are 0.
Example 1. The following Karnaugh map represents symmetric function F = ab bc ac.
(a) (b)
Figure 2. A three-variable symmetric Boolean function: (a) Karnaugh map, and (b) relation
with symmetry indices.
In Fig. 2, a symmetry index Si
specifies a Karnaugh map cell that counts value “1” in the
specified minterm in number of times equal to i.
Definition 2. The elementary symmetric functions of n variables are:
S0
= nxxx ...21 ,
S1
= nnnn xxxxxxxxxxx 12132121 ............ ,
…,
Sn
= nxxx ...21 .
Thus, for Boolean function of three variables one obtains the following sets of symmetry indices:
S0
= cba , S1
= cbacbacba ,, , S2
= cbacabbca ,, , and S3
= abc . It has been shown that an
arbitrary n-variable symmetric function f is uniquely represented by elementary symmetric
functions {S0
, S1
, …, Sn
} as follows: f =
Ai
Ai
SS , where A {0, 1, …, n}. Also it can be
shown that for f = SA
and g = SB
, the following operations are obtained:
BA
Sgf
. (1)
BA
Sgf
(2)
BA
Sgf
(3)
A
Sf (4)
ab
c
0 1
00 0 S0
0 S1
01 0 S1
1 S2
11 1 S2
1 S3
10 0 S1
1 S2
Two-Valued Tabular
Representation
Inputs "1" Values
Symmetry Indices
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It has been shown [2], [21] that a function which is not symmetric can be symmetrized by
repeating its variables. This method of variable repetition transforms the values of Karnaugh map
cells which make the function non-symmetric into don’t cares which make the function
symmetric.
Example 2. The following Karnaugh map demonstrates the symmetrization by repeating the
variables of non-symmetric Boolean function F = ba .
(a) (b)
Figure 3. Symmetrization by repeating variables: (a) non-symmetric Boolean function F, and (b)
symmetric Boolean function F which is obtained by the repetition of variable {a}.
One notes that while in Fig. 3(a) conflicting values occur for symmetry index S1
in minterms ba
and ba and thus producing non-symmetric function, non-conflicting values are produced for the
same non-symmetric function in Fig. 3(b) by repeating variable {a} two times.
As stated previously, various applications of symmetry indices for the synthesis of logic
functions have been previously shown. This includes symmetric networks, Akers arrays and
lattice networks [1]-[4], [7], [21] among other several implementations.
The concept of lattice networks for switching functions involves three components: (1) expansion
of a function that corresponds to the root in the lattice which creates several successor nodes of
the expanded node, (2) joining of several nodes to a single node which is the reverse operation of
the expansion process, and (3) regular geometry to which the nodes are mapped. Figure 4(a)
shows an example of a four-variable (i.e., four-level) general two-dimensional lattice network
(with interconnected nodes which are two-to-one multiplexers), and Figs. 4(b) and 4(c) show the
relationship between Fig. 4(a) and symmetry indices.
Therefore, Fig. 4 shows an example of the fact that regular lattice networks exhibit a close
relationship with symmetry indices, where symmetry indices represent the sets of all possible
paths from leafs to the root of the corresponding lattice network. One also notes that each internal
node in Fig. 4(a) is a Shannon node which is practically implemented as a two-to-one multiplexer
whose output goes in two directions. Other types of expansion nodes can be implemented as well
[2] that will produce corresponding types of various kinds of lattice networks.
b
a 0 1
0 1 1
1 0 1 F
0
S 1S
1S 2
S
b
a
a
0 1
00 1 1
01 - -
11 0 1
10 - - F
0
S 1
S
1
S 2
S
2S 3S
1S 2S
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Figure 4. The relation between a two-dimensional lattice and symmetry indices: (a) two-dimensional lattice
network for a four-variable function, (b) sets of binary symmetry indices, and (c) the corresponding
Karnaugh map interpretation of the binary symmetry indices.
It has been shown [2], [21] that every non-symmetric function can be symmetrized by repeating
its variables. Therefore, since a single variable corresponds to a single level in the lattice
network, repeating variables produces a repetition of levels in a lattice network. In general, three
main factors control the size of a lattice network that realizes non-symmetric functions [2]: (1)
expansion types that are used in the internal nodes, (2) order of variables upon which functions
are expanded in each level of the lattice, and (3) the choice of repeated variables. Consequently,
various optimization methods have been addressed for an optimal choice of the three factors that
are mentioned above in order to minimize the size of the corresponding lattice network.
In general, it has been shown [2] that in order to preserve the regular realization of expansions
over nth
radix, it is sufficient to join n nodes in n-dimensional space to obtain the corresponding
lattice networks. For instance, it is sufficient in the binary case to join two nodes. Analogously, it
is sufficient in the ternary case to join three nodes to form the corresponding three-dimensional
lattice networks. Fully symmetric ternary functions do not need any joining operations to repeat
variables in order to realize them in three-dimensional lattice networks.
Figure 5 shows the close relationship between three-dimensional lattice networks and ternary
symmetry indices, where ternary symmetry indices are the sets of all possible paths from leafs to
the root of a three-dimensional lattice network. Note that each internal node in Fig. 5 is a ternary
Shannon node which is a three-to-one multiplexer whose output goes in three directions.
3. LATTICE NETWORK SYNTHESIS USING ITERATIVE SYMMETRY INDICES
DECOMPOSITION
The realization of non-symmetric functions using lattice networks demands the repetition of
variables [2]. In many cases, one has to repeat variables so many times that will result in a big
size two-dimensional lattice network which doesn't fit the specified area or the required volume
in the case of three-dimensional networks. On the other hand, one can re-route the corresponding
interconnects between the internal nodes of the lattice network using optimization methods in a
way such that the network will fit into the specified layout space. Yet, this process will make the
used interconnects between lattice cells of many different lengths, and consequently strips the
lattice network from one of its most important features for which all of the interconnects are of
the same length.
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(a)
(b) (c)
Figure 5. Three-dimensional lattice for ternary three-variable functions: (a) three-
dimensional lattice network, (b) sets of ternary symmetry indices, and (c) the ternary natural-encoded map
for the ternary symmetry indices.
In current and future circuit technologies, most of the resulting circuit area is occupied by local
and global interconnects, and the delay of interconnects is responsible for more than 50% of the
total delay which is associated with a circuit or a system [26]. Thus, maintaining local
interconnects of equal length will minimize the total length of the used wires and consequently
will minimize the resulting delay and consumed power. This idea of maintaining interconnects of
equal length for a large size lattice network which does not fit specific layout boundaries can be
achieved using the process of Iterative Symmetry Indices Decomposition (ISID) [3].
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol 11, No 6, December 2020
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For a karnaugh map of a non-symmetric Boolean function, conflicting values of “0” and “1” exist
within some symmetry indices Si
. While one method of removing such conflicting values is done
by repeating variables, another method of removing such conflicting values is done by
decomposing the non-symmetric function into a symmetric part superimposed with an error part
[3], where the error part can be then iteratively decomposed into a superposition of two parts. The
superposition of the decomposed parts to produce the total function can be done using either the
Exclusive-OR operator or the Equivalence operator. The following procedure demonstrates the
detailed steps for obtaining the required ISID-based decomposition that will maintain
interconnects of the same length for large size lattice networks which don't fit specific layout
boundaries.
ISID Decomposition
(1) For a given area or volume specifications, synthesize any non-symmetric function using a
lattice network by repeating variables.
(2) If repeating variables will force the lattice network to grow out of the layout boundaries,
decompose the non-symmetric function into two superimposed parts; a symmetric part and
an error part (i.e., the correction part). Then, the original function is equal to the exclusive-
OR or the equivalence of the two decomposed functions. This is denoted as -ISID and -
ISID, respectively. Since there are many possible ways to obtain a symmetric function
from the original non-symmetric function using ISID, one can choose a symmetric part by
using the optimization criterion of Hamming distance in which one chooses the minimum
number of changes of function values that are needed to transform the non-symmetric
Boolean function into a symmetric one.
(3) Synthesize the symmetric part using a lattice network. If the synthesis fits layout boundaries
then synthesize the error function.
(4) If the resulting synthesis does not fit layout boundaries, then go to step (2) and perform in
serial-mode a single decomposition of the symmetric or error sub-functions, or perform in
parallel-mode a multi-decomposition on all symmetric and error sub-functions.
(5) Repeat step (4) until the synthesis fits the specified layout boundaries.
Example 3. For the non-symmetric function F, Fig. 6 shows the synthesis of F using a two-
dimensional lattice network which requires the repetition of a variable {b} to remove the non-
symmetrization.
Figure 6. A two-dimensional Shannon lattice network.
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One notes that the two-dimensional lattice network in Fig. 6 is made up of 15 two-to-one
multiplexers. Each two-to-one multiplexer consists of three logic gates. Thus, Fig. 6 is made up
of a total of 45 logic primitives. Using the ISID procedure, the same non-symmetric function can
be synthesized using XOR-based ISID as shown in Fig. 7.
Figure 7. Shannon ISID XOR-based lattice network.
In Fig. 7, F1 realizes the symmetric part and F2 realizes the error part. Note that in Fig. 7 one has
six two-to-one multiplexers and three logic primitives namely AND, OR and XOR. Thus, one has
a total of 63 + 3 = 21 logic primitives. Consequently, by comparing the total number of gates
needed in Fig. 7 to those in Fig. 6, one observes that we economized a total of 24 logic
primitives. On the other hand, if one uses ISID XNOR-based synthesis then we obtain the
decomposition in the tables that are shown in Fig. 8 and the corresponding lattice-based synthesis
of the non-symmetric function. The cost of the lattice network in Fig. 8 is 21 logic primitives
which is equal to the cost that was obtained in Fig. 7.
Figure 8. Shannon ISID XNOR-based lattice network.
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One observes that two-level sum-of-product (SOP) circuits have been used to synthesize the error
functions in Figs. 7 and 8, respectively. This choice has the advantage of the use of minimal
number of logic primitives, but has the disadvantage of transforming the lattice network from a
fully-regular network, where only one type of primitives has been used (namely the two-to-one
multiplexer), to a semi-regular network where many different logic primitives have been used;
two-to-one multiplexer, AND and OR gates. To maintain full regularity in terms of using one
type of logic primitives, one can synthesize the error function using a separate multiplexer-based
logic network. This idea is demonstrated in Fig. 8 using the ISID XNOR-based Shannon lattice
network, where one observes that the multiplexer-based network in Fig. 8 has 10 two-to-one
multiplexers and thus has 30 Boolean gates, which is still much less than the total number of
gates that were obtained in Fig. 6.
Using the procedure for the ISID decomposition, one can have a complicated decomposed
structure that fits certain specifications. The following extends the ISID algorithm to the case of
the three-dimensional space, where the introduced three-dimensional logic synthesis is
implemented using the ternary radix of Galois field which is shown in Table 1.
Table 1. Third radix Galois operations: (a) GF(3) addition and (b) GF(3) multiplication.
(a) (b)
Analogously to the ISID procedure for the binary case of two-dimensional lattice network, the
three-dimensional lattice network of ternary functions using ISID can be obtained as well. The
same idea of two-dimensional ISID can be used for three-dimensional ISID by using the
corresponding algebraic equations over GF(3) to decompose the corresponding three-valued
input three-valued output maps, where these equations are shown as follows:
a *3 a *3 a = a (5)
a +3 a +3 a = 0 (6)
Thus, the same ISID procedure (which was previously presented) is utilized in three-dimensions,
with the only exception of replacing binary Galois operations (e.g., the XOR operation) with the
corresponding ternary Galois operations that are represented in Equations (5) and (6). Full
illustration of this will be presented in Section 5 where the synthesis of nano-based ISID three-
dimensional lattice networks will be shown.
4. MULTIPLE-VALUED GALOIS COMPUTING USING CARBON FIELD
EMISSION – BASED DEVICES
As was previously shown in the first and second parts of the article, and by utilizing the
previously experimented and observed characterizations and operations of carbon field-emission
that were presented, Fig. 9 presents the carbon field-emission primitive that realizes the two-to-
10. International Journal of VLSI design & Communication Systems (VLSICS) Vol 11, No 6, December 2020
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one controlled switch. In Fig. 9, the input control signal that is used to control the electric
conduct of the device is implemented using the imposed electric field intensity (E) or
equivalently the corresponding work function (Φ) or voltage (V).
In the carbon field-emission device which is shown in Fig. 9(a), by imposing the control signal of
high voltage (HV), the voltage difference between the carbon cathodes and the facing anode is
varied. This change will make the carbon cathode with control signal (HV) to be field-emitting
while the other carbon cathode with the complementary control signal ( VH ) to be without field-
emission. When the voltage difference is reversed, then carbon cathode with the complementary
control signal ( VH ) will be field- emitting while the other carbon cathode with the control signal
(HV) will be without field-emission. Thus, this device implements the functionality of the two-to-
one controlled switching (G = ac + bc') which is shown in Fig. 9(b).
(a) (b)
Figure 9. Carbon field-emission device implementing two-to-one controlled switching (CS): (a) carbon
field-emission two-to-one controlled switching, and (b) the corresponding block diagram.
Synthesizing many-to-one carbon field-emission controlled switches is possible using the
fundamental two-to-one carbon field-emission controlled switch from Fig. 9. For example, for the
three-valued logic case, one needs two devices from Fig. 9 to realize the functionality of three-to-
one carbon field-emission controlled switch. In general, for the general case of m-valued logic,
one needs (m-1) of the two-to-one controlled switches to realize the function of an m-to-1
controlled switching. This idea is illustrated in Fig. 10 where devices {D1,..., D(m-1)} can be
realized using the carbon-based field-emission controlled switch that was presented in Fig. 9.
Figure 10. The realization of a general (m-to-1) controlled switch.
a
b
c
Two-to-One
CS
G
HV HV
- -
b
R1
c'
G a
R2
c
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Multiple-valued computing has been also illustrated using the presented carbon-based field-
emission device. A controlled switch-based circuit that implements GF(3) addition and
multiplication tables is shown in Fig. 11, where Fig. 11(a) can be implemented using the two-
input single-output carbon field-emission device from Fig. 9.
In Fig. 11(b), variables {A, B} are two ternary input variables that can take any value from the set
{0, 1, 2}, inputs {0, 1, 2} are constant inputs, and inputs Ck (k = 0, 1, 2, 3) are two-valued control
variables that take values from the set {0, 1}. Note that Fig. 11(b) implements GF(3) addition and
multiplication tables by using the appropriate values of control variables Ck that select the
corresponding device inputs of variable inputs {A, B} and constant inputs {0, 1, 2}.
For instance, Table 2 shows an example for the implementation of GF(3) addition and
multiplication operations using Fig. 11(b). In Table 2, the symbol (+) means GF(3) addition,
symbol (*) means GF(3) multiplication, Ck (+) means that the control variable Ck to implement
the ternary addition operation, and Ck (*) means that the control variable Ck to implement the
ternary multiplication operation.
Since three-valued networks over GF(3) will be synthesized using the corresponding addition and
multiplication operations, the circuit in Fig. 11(b) can be used in multi-valued implementations
whenever GF(3) addition and multiplication operations are applied. For example, any hierarchical
complex system-level implementation can be performed from the iterative utilization of the
carbon-based controlled switching device which is shown in Fig. 11, where the corresponding
arithmetic operations can be implemented using the nano circuit from Fig. 11(b) and by utilizing
the corresponding specified input values from Table 2.
(a)
(b)
Figure 11. The carbon-based implementation of Galois arithmetic operations: (a) controlled switch symbol
that can be implemented using the device in Fig. 9, and (b) circuit that uses controlled-switching to
implement GF(3) addition and multiplication operations.
A B C G
a b 0 a
a b 1 b
A 0
B 1
C
G
A 0
B 1
0
1
2
C0 C1 C2 C3
0
1
0
1
K
0
1
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Table 2. The implementation of third radix Galois addition and multiplication operations using Fig. 11(b).
5. LAYOUT CONGESTION-FREE LATTICE PROCESSING VIA CARBON
FIELD - EMISSION MULTIPLEXING
This section introduces the synthesis of three-valued Galois functions using carbon field
emission–based three-dimensional lattice networks utilizing the method shown in Fig. 12. In this
method, mapping any three-valued function into the corresponding three-dimensional lattice
network can be achieved using either of the following two functional forms: (1) the function
expression form through the RPL-based decomposition, or (2) using the tabular form of the
corresponding three-valued function.
Figure 12. Utilized method to realize three-valued Galois logic using function decompositions.
Example 4 shows the realization of a ternary non-symmetric function in a three-dimensional
lattice through the repetition of variables and by utilizing the synthesis scheme from Fig. 12,
where in general the operations performed in each node in the three-dimensional lattice network
can be implemented using the nano-based circuit from Fig. 11(b) and by using the specified input
values from Table 2.
A B C0 (+) C1 (+) C2 (+) C3 (+) C0 (*) C1 (*) C2 (*) C3 (*) + *
0 0 0 0 0 0 0 0 0 0 0 0
0 1 1 0 0 0 0 0 0 0 1 0
0 2 1 0 0 0 0 0 0 0 2 0
1 0 0 0 0 0 1 0 0 0 1 0
1 1 0 0 0 1 0 0 0 0 2 1
1 2 0 1 0 0 1 0 0 0 0 2
2 0 0 0 0 0 1 0 0 0 2 0
2 1 0 1 0 0 0 0 0 0 0 2
2 2 0 0 1 0 0 0 1 0 1 1
Three-Valued Tabular
Decomposition
ISID-Based Three-
Dimensional Lattice
Computing
Ternary Galois
Function Expression
Ternary Galois
Function Expression
13. International Journal of VLSI design & Communication Systems (VLSICS) Vol 11, No 6, December 2020
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Example 4. Lets us apply the ternary version of ISID procedure to decompose the map in Fig.
13(a).
(a) (b)
Figure 13. A non-symmetric ternary function: (a) Ternary map, and (b) ISID to be performed using the
tabular decomposition of the ternary function.
Using the previously presented definition of ternary symmetric indices, one can observe that the
ternary non-symmetric map shown in Fig. 13 can be decomposed using the ISID procedure into a
symmetric part and non-symmetric part. In contrast to the binary case, where this can be done
only in one specific EXOR expression, ISID can be done in the multiple-valued case in various
ways. This can be illustrated here as the indexed cell {a = 0, b = 2, c = 2} has the value of “0”.
To produce a symmetric part, the indicated indexed cell has to have the value of “1”.
Consequently, there are two possibilities for this. The first one follows Equation (6) for which (1
+GF(3) 1 +GF(3) 1 = 0), and the second possibility follows the algebraic equation from Table 1(a) for
which (1 +GF(3) 2 = 0). Thus two possible ternary map decompositions follow as shown in Fig. 14,
and consequently two possible three-dimensional lattice networks can be implemented using the
ternary ISID decomposition as shown in Fig. 15. One notes that, for the non-symmetric function
in Fig. 13, one needs to repeat one of the variables in order to realize such non-symmetric ternary
function using a three-dimensional lattice network.
(a) (b)
Fig. 14. Two possible ISID decompositions for the ternary three-variable {a, b, c} function in Fig. 13:
(a) first decomposition obtained using the GF(3) algebraic equation (1 +3 1 +3 1 = 0), and (b) second
decomposition obtained using the GF(3) algebraic equation (1 +3 2 = 0).
The process of variable repetition in a three-dimensional lattice network will impose the addition
of many new internal cells, depending on the variables chosen to be repeated, and in the worse
case one has to repeat variables so many times that the final three-dimensional lattice network
ab
c
0 1 2
00 1 2 0
01 2 0 2
02 0 2 0
10 2 0 2
11 0 1 2
12 2 2 0
20 0 2 1
21 2 2 0
22 1 0 1
1 2 0
2 0 2
0 2 0
2 0 2
0 1 2
2 2 0
0 2 1
2 2 0
1 0 1
0 0 0
0 0 0
0 0 1
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
1 2 0
2 0 2
0 2 1
2 0 2
0 1 2
2 2 0
0 2 1
2 2 0
1 0 1
0 0 0
0 0 0
0 0 1
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
1 2 0
2 0 2
0 2 0
2 0 2
0 1 2
2 2 0
0 2 1
2 2 0
1 0 1
0 0 0
0 0 0
0 0 2
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
1 2 0
2 0 2
0 2 1
2 0 2
0 1 2
2 2 0
0 2 1
2 2 0
1 0 1
= + + = +
Three-Valued Tabular
Decomposition
ISID-Based Three-
Dimensional Lattice
Realization
= + + = +
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will not fit the specified three-dimensional volume boundaries. On the other hand, the networks
in Fig. 15 do not need to repeat variables because the ternary error part is realized in Galois field
Sum-Of-Product (GFSOP) network. This can reduce substantially the number of nodes that are
needed for highly non-symmetric ternary functions. Yet, the trade off here is that, while we have
a totally-regular structure in the case of large three-dimensional lattice networks where one uses
only single type of internal nodes and only one type of interconnects, we have now (as shown in
Fig. 15) a semi-regular lattice network which is composed of two parts, namely the error part
which is not fully-regular in general, and the symmetric part which is made of a fully-regular
three-dimensional lattice network.
Analogously to the two-dimensional case, three-dimensional network synthesis using ternary
ISID can be iteratively performed in either serial-mode or parallel-mode. The result of such three-
dimensional ISID will be the decomposition of a large three-dimensional lattice network into
many superimposed smaller three-dimensional lattice networks as shown in Fig. 16; the iterative
use of ISID (in serial or parallel modes) will result in decomposing the three-dimensional cubical
lattice into corresponding three-dimensional pyramids. The resulting decomposition seen in Fig.
16 will generate pyramids in three dimensions, in contrast to the binary case for which the
iterative use of ISID will decompose the two-dimensional rectangular layout into many smaller
two-dimensional triangles.
One also can note that the error part in a ternary ISID can be realized in a three-dimensional
lattice network with variable repetition if the error function is non-symmetric, or without any
variable repetition if the error function is symmetric. Thus, one can maintain full regularity in the
total interconnected network that includes both the error part and the symmetric part, since one
will use only one type of internal nodes and only one type of internal interconnects.
Figure 15. Two functionally-equivalent realizations of three-dimensional lattice networks using the
corresponding implementations of ternary ISID from Figs. 14(a) and 14(b), respectively.
15. International Journal of VLSI design & Communication Systems (VLSICS) Vol 11, No 6, December 2020
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(a) (b)
Figure 16. The iterative implementation of ISID procedure for the decomposition of ternary non-symmetric
functions in three-dimensions: (a) ISID in three-dimensional lattice networks, and (b) pyramid grid layout
as a result of the iterative implementation of the ISID procedure.
As mentioned previously, for the corresponding ternary three-dimensional lattice networks (such
as the ones shown in Fig. 15), the operations performed in each internal node can be implemented
using the nano circuit from Fig. 11(b) and by utilizing the corresponding specified input values
from Table 2, from which all internal node operations over GF(3) can be achieved.
The synthesized resulting ISID-based three-dimensional lattice networks (such as the ones
illustrated in Fig. 15) still possess the important characteristic of regularity, since the error part in
a ternary ISID can be realized in a three-dimensional lattice network with variable repetition if
the error function is non-symmetric or without any variable repetition if the error function is
symmetric. Therefore, one can maintain full regularity in the total interconnected network that
includes both of the error and symmetric parts, and thus preserving the important properties of
compactness in three-dimensional space, ease of manufacturability, no need for three-
dimensional layout routing and placement, predictable timing, relative ease of testability and
repair when fault occurs, and lower power consumption which is due to using both (a) only local
interconnects and (b) low-power carbon nano-based switches that were demonstrated in Fig. 11.
6. CONCLUSIONS AND FUTURE WORK
The synthesis of three-dimensional lattice networks using carbon field-emission nano switching
devices and Iterative Symmetry Indices Decomposition (ISID) for congestion-free low-power
layout realization is introduced. The operations of the ternary ISID-based three-dimensional
lattice architectures utilizing the introduced nano-based systems are also demonstrated. The
application of ISID-based decomposition in three dimensions uses operations on symmetry
indices that superimpose iteratively a symmetric part and an error-part of an arbitrary non-
symmetric function, which allows for achieving congestion-free nano-based realizations of three-
dimensional lattice networks, within which internal nodes are synthesized using carbon field-
emission nano multiplexing devices.
The research realizations which are introduced in this article are new and original, and are
performed for the first time to implement ternary Galois functions utilizing concurrent ISID-
based nano lattice systems that use carbon field-emission devices which are based on the field-
emission from carbon nano-apex fibers and nanotubes.
16. International Journal of VLSI design & Communication Systems (VLSICS) Vol 11, No 6, December 2020
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The new implementation of congestion-free architectures are important since the resulting nano-
based regular three-dimensional lattice networks possess the highly important properties of
regularity and low- power consumption, which are required in several synthesis applications. Due
to the use of local regular interconnects and low-power carbon-based nano switching devices, the
resulting three-dimensional lattice networks can be especially important for future three-
dimensional technologies for which major requirements include the minimization of power
consumption and performance enhancement.
Future work will include items such as: (1) investigating the use of various optimization
algorithms to obtain minimal-size three-dimensional lattice networks by utilizing optimization
methods such as (a) optimal selection of the order of control variables and (b) optimal selection
of the utilized types of internal lattice nodes, (2) further evaluations of the introduced methods
using applied metrics such as size, delay and power consumption in order to quantify the
efficiency of the presented new realizations, and (3) the complete fabrication and testing of the
new carbon field-emission controlled-switching devices and their integrated application within
system-level nano-based lattice architectures for arithmetic-intensive computing applications.
ACKNOWLEDGEMENT
This research was performed during sabbatical leave in 2019-2020 granted to the author from
The University of Jordan and spent at Isra University, Jordan.
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AUTHOR
Anas N. Al-Rabadi is currently a Professor in the Department of Computer Engineering at The
University of Jordan. He received his Ph.D. in Computer Design and Advanced Logic Synthesis
in 2002 and M.Sc. in Control and Power Electronic Systems Design in 1998, both from the
Department of Electrical and Computer Engineering at Portland State University. From 2002
until 2004, Prof. Al-Rabadi had served as a Research Faculty at the Office of Graduate Studies
and Research at Portland State University. He is the author of the first international published
title and first comprehensive book on Reversible Logic Synthesis (Springer-Verlag, 2004),
Reversible Logic Synthesis: From Fundamentals to Quantum Computing. Currently, Prof. Al-
Rabadi is the author of more than 130 international scholarly and indexed publications. He also
holds a USPTO nanotechnology patent which is registered in 2009 in U.S.A. under patent No. US
7,508,039 B2. His current research interests include distributed and parallel computing, systolic
architectures, regular circuits and systems, reversible logic, quantum computing, multiple-valued
logic, soft computing and computational intelligence, machine learning, artificial intelligence,
optical computing, reconstructability analysis of systems, spectral methods, signal processing,
testing and design for testability, nanotechnology, robotics, optimal and robust control, and
digital error-control coding.