The document discusses symmetric shared-memory architectures and multiprocessors. It explains that large, multilevel caches can significantly reduce memory bandwidth demands on a processor. It then covers cache coherence and different schemes for enforcing coherence, including directory-based and snooping protocols. As the number of processors or memory demands grow, centralized resources like snooping can become bottlenecks.

1. Multiprocessors and Thread-Level Parallelism Symmetric Shared-Memory Architectures “ The use of large, multilevel caches can substantially reduce the memory bandwidth demands of a processor.” Hennessy and Patterson

3. Multiprocessors Cache Coherence

6. Write Invalidate Protocol

7. An Example Protocol

8. An Example Protocol

9. An Example Protocol

11. SSM and Snooping Limitations

13. Thank you! Author: Prof. Sergio Takeo, Marcelo Arbore. Bibliography: Patterson, D. A.; Hennessy, J. L. Computer Architecture: A quantitative Approach, 4 th Ed. Morgan Kaufmann Publishers. “ The use of large, multilevel caches can substantially reduce the memory bandwidth demands of a processor.” Hennessy and Patterson