This document summarizes key concepts related to computer memory organization and hierarchy. It discusses how memory is organized from the fastest cache memory up to slower main memory and auxiliary storage. It covers cache mapping techniques like direct mapping, set associative mapping and associative mapping. Virtual memory and paging/segmentation techniques are also summarized. Replacement algorithms for cache memory like FIFO and LRU are discussed. The document provides an overview of computer architecture course topics and assessment patterns.

1. DISCOVER . LEARN . EMPOWER
MEMORY ORGANIZATION
University Institute of Engineering
DEPARTMENT OF COMPUTER SCIENCE
& ENGINEERING
Bachelor of Engineering (Computer Science & Engineering)
Subject Name: Computer Organization & Architecture
Subject Code: CST-252

2. Topics covered
• Memory hierarchy
• Cache Memory Associative Memory
• Cache memory with associative memory
• Virtual Memory:
1. Paging
2. Segmentation
2

3. MEMORY HIERARCHY
3
• Memory Hierarchy is to obtain the highest possible access speed while minimizing the total cost of the
memory system

4. MAIN MEMORY
• Typical RAM chips
• Typical ROM chips
4
Chip select 1
Chip select 2
Read
Write
7-bit address
CS1
CS2
RD
WR
AD 7
128 x 8
RAM
8-bit data bus
CS1 CS2 RD WR
0 0 x x
0 1 x x
1 0 0 0
1 0 0 1
1 0 1 x
1 1 x x
Memory function
Inhibit
Inhibit
Inhibit
Write
Read
Inhibit
State of data bus
High-impedence
High-impedence
High-impedence
Input data to RAM
Output data from RAM
High-impedence
Chip select 1
Chip select 2
9-bit address
CS1
CS2
AD 9
512 x 8
ROM
8-bit data bus

5. • Address space assignment to each memory chip
• Example: 512 bytes RAM and 512 bytes ROM
• RAM and ROM chips are connected to a CPU through the data and address buses
• - The low-order lines in the address bus select the byte within the chips and other lines in the address bus
select a particular chip through its chip select inputs
5
MEMORY ADDRESS MAP
RAM 1
RAM 2
RAM 3
RAM 4
ROM
0000 - 007F
0080 - 00FF
0100 - 017F
0180 - 01FF
0200 - 03FF
Component
Hexa
address
0 0 0 x x x x x x x
0 0 1 x x x x x x x
0 1 0 x x x x x x x
0 1 1 x x x x x x x
1 x x x x x x x x x
10 9 8 7 6 5 4 3 2 1
Address bus

6. 6
MEMORY HIERACHY
• Provide backupstorage
• MAGNETIC DISKS,MAGNETIC
TAPES
Auxiliary
Memory
• Occupiescentral position,
communicatesdirectly with theCPU,
Auxiliary Memory,CacheMemory
Main
Memory
CPU
• Special high speedmemory
• Currentprogramsanddata to
CPUat rapidrate
Cache
Memory
I/O
Processor

7. • CPU logic is usually faster than main memory access time, with the result that processing speed is limited
primarily by the speed of main memory.
• The cache is used for storing segments of programs currently being executed in the CPU and temporary data
frequently needed in the present calculations.
• The typical access time ratio between cache and main memory is about 1 to 7~10 .
• Auxiliary memory access time is usually 1000 times that of main memory.
• The memory hierarchy system consists of all storage devices employed in acomputer system from the slow by high-
capacity auxiliary memory to arelatively faster main memory,to anevensmallerandfastercachememory.
7
Contd..

8. • Amemoryunitaccessedbycontentsiscalled anassociativememory or content addressablememory(CAM).
• Thistype of memory isaccessed simultaneously andin parallel on the basisof data content rather than by specificaddress or
location.
Writeoperation:
•Whenaword iswritten ininanassociativememory, no addressisgiven
•Thememoryiscapableof finding anunusedlocation tostore the word.
Readoperation:
•When a word is to be read from an associative memory, the contents of the word, or a part of the word is specified.
•The memory locates all the words which match the specified content and marks them for reading.
8
ASSOCIATIVE MEMORY

9. HARDWARE ORGANIZATION
• Argument register(A): It contains the word to be searched.
It hasn bits(onefor eachbit of the word).
• Key Register(K): It provides mask for choosing a particular
field or key in the argument word. It also hasn bits.
• Associative memory array: It contains the words which are
to be comparedwith the argument word.
• Match Register(M):It has m bits, one bit corresponding to
each word in the memory array . After the matching process, the
bits corresponding to matching words in match register are set
to 1.
9
SOURCE: Computer architecture by Morris Mano

10. • The transformation of data from main memory to cache memory is referred to as a mapping process, there are three
types ofmapping:
• Associativemapping
• Directmapping
• Set-associativemapping
• T
ohelpunderstandthe mappingprocedure,wehavethe followingexample:
10
MAPPING PROCESS
SOURCE: Computer architecture by Morris Mano

11. ASSOCIATIVE MAPPING
11
SOURCE: Computer architecture by Morris Mano
• The fastest and most flexible cache organization uses an associative
memory.
• The associative memory stores both the address and data of the
memory word.
• This permits any location in cache to store a word from main
memory.
• The address value of 15 bits is shown as a five-digit octal number
and its corresponding 12-bit word is shown as a four-digit octal
number

12. • Associativememoryis expensivecomparedto RAM.
• In general case, there are 2^k words in cache memory and 2^n words in
mainmemory(inour case,k=9,n=15).
• Thenbitmemoryaddress isdividedintotwofields: k-bitsfortheindexand
• n-kbitsforthetagfield.
12
DIRECT MAPPING
SOURCE: Computer architecture by Morris Mano

13. • The disadvantage of direct mapping is that two words with the same index in their address but with different tag values
cannotresideincachememory atthesametime.
• Set-Associative Mappingisan improvementoverthedirect- mappinginthateachwordof cachecanstoretwoormore word
ofmemoryunderthe sameindexaddress.
13
SET ASSOCIATIVE MAPPING
SOURCE: Computer architecture by Morris Mano

14. • Optimalreplacementalgorithm–findthe blockforreplacementthathasminimum chancetobereferencednexttime.
• Twoalgorithms:
I. FIFO:Selectstheitemwhichhasbeeninthesetthe longest.
II. LRU:Selectstheitemwhichhasbeenleastrecentlyused bytheCPU.
14
REPLACEMENT ALGORITHMS

15. • Virtualmemoryisacommonpartof operatingsystemondesktopcomputers.
• ThetermVirtualMemoryreferstosomething whichappearstobepresentbutactuallyis not.
• Thistechniqueallowsuserstousemore memoryforaprogramthantherealmemory ofacomputer.
15
VIRTUAL MEMORY

16. • Virtual Memoryisaimaginarymemory which weassumeor use,when we haveamaterial that exceedsourmemoryat that
time.
• Virtual Memory is temporary memory which is used along with the ram of the system.
16
NEED FOR VIRTUAL MEMORY

17. • Allows Processes whose aggregate memory requirement is greater than the amount of physical memory, as infrequently
usedpages canresideonthedisk.
• Virtualmemoryallowsspeedgainwhenonlya particularsegmentoftheprogramisrequired fortheexecutionoftheprogram.
• Thisconceptisveryhelpfulinimplementing multiprogrammingenvironment.
17
ADVANTAGES

18. • Applicationsrunratherslowerwhentheyare usingvirtualmemory.
• Ittakesmoretimetoswitchbetween applications.
• Reducessystemstability.
18
DISADVANTAGES

19. APPLICATIONS
• Computer organization and architecture course deals with instruction set architecture, micro architecture and
efficient implementation of micro architecture.
• Understanding the computer architecture concepts is essential for students interested in hardware, processor
design, compilers, and operating systems.
19

20. REFERENCES
Reference Books:
1. J.P. Hayes, “Computer Architecture and Organization”, Third Edition.
2. Mano, M., “Computer System Architecture”, Third Edition, Prentice Hall.
3. Stallings, W., “Computer Organization and Architecture”, Eighth Edition, Pearson Education.
Text Books:
1. Carpinelli J.D,” Computer systems organization &Architecture”, Fourth Edition, Addison Wesley.
2. Patterson and Hennessy, “Computer Architecture” , Fifth Edition Morgaon Kauffman.
Reference Website
1. https://www.geeksforgeeks.org/computer-organization-and-architecture-tutorials/
20

21. Assessment Pattern
• Element1(Assignment 1,2,3(Average)): 12 Marks
• Element2(Surprise Test): 9 Marks
• Element3(Tutorial/Optional): 9 Marks
• Element4(Quiz): 12 Marks
• MST1: 36 Marks
• MST2: 36 Marks
• Final Examination: 60 Marks
21

22. THANK YOU