CMOS VLSI Design: Transistor theory lect3-transistors.ppt

Lecture 3:
CMOS
Transistor
Theory

CMOS VLSI Design
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 2
Outline
 Introduction
 MOS Capacitor
 nMOS I-V Characteristics
 pMOS I-V Characteristics
 Gate and Diffusion Capacitance

CMOS VLSI Design
Introduction
 So far, we have treated transistors as ideal switches
 An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
 Transistor gate, source, drain all have capacitance
– I = C (V/t) -> t = (C/I) V
– Capacitance and current determine speed

CMOS VLSI Design
polysilicon gate
(a)
silicon dioxide insulator
p-type body
+
-
Vg < 0
MOS Capacitor
 Gate and body form MOS
capacitor
 Operating modes
– Accumulation
– Depletion
– Inversion
(b)
+
-
0 < Vg < Vt
depletion region
(c)
+
-
Vg > Vt
depletion region
inversion region

CMOS VLSI Design
Terminal Voltages
 Mode of operation depends on Vg, Vd, Vs
– Vgs = Vg – Vs
– Vgd = Vg – Vd
– Vds = Vd – Vs = Vgs - Vgd
 Source and drain are symmetric diffusion terminals
– By convention, source is terminal at lower voltage
– Hence Vds  0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
– Cutoff
– Linear
– Saturation
Vg
Vs
Vd
Vgd
Vgs
Vds
+
-
+
-
+
-

CMOS VLSI Design
nMOS Cutoff
 No channel
 Ids ≈ 0
+
-
Vgs
= 0
n+ n+
+
-
Vgd
p-type body
b
g
s d

CMOS VLSI Design
nMOS Linear
 Channel forms
 Current flows from d to s
– e-
from s to d
 Ids increases with Vds
 Similar to linear resistor
+
-
Vgs > Vt
n+ n+
+
-
Vgd
= Vgs
+
-
Vgs
> Vt
n+ n+
+
-
Vgs
> Vgd
> Vt
Vds = 0
0 < Vds
< Vgs
-Vt
p-type body
p-type body
b
g
s d
b
g
s d
Ids

CMOS VLSI Design
nMOS Saturation
 Channel pinches off
 Ids independent of Vds
 We say current saturates
 Similar to current source
+
-
Vgs > Vt
n+ n+
+
-
Vgd
< Vt
Vds
> Vgs
-Vt
p-type body
b
g
s d Ids

CMOS VLSI Design
I-V Characteristics
 In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?

CMOS VLSI Design
Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversions
– Gate – oxide – channel
 Qchannel = CV
 C = Cg = oxWL/tox = CoxWL
 V = Vgc – Vt = (Vgs – Vds/2) – Vt
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-
drain
Vds
channel
-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2 gate oxide
(good insulator, ox = 3.9)
polysilicon
gate
Cox = ox / tox

CMOS VLSI Design
Carrier velocity
 Charge is carried by e-
 Electrons are propelled by the lateral electric field
between source and drain
– E = Vds/L
 Carrier velocity v proportional to lateral E-field
– v = E  called mobility
 Time for carrier to cross channel:
– t = L / v

CMOS VLSI Design
nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
channel
ox 2
2
ds
ds
gs t ds
ds
gs t ds
Q
I
t
W V
C V V V
L
V
V V V



 
  
 
 
 
  
 
  ox
=
W
C
L
 

CMOS VLSI Design
nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases current
 
2
2
2
dsat
ds gs t dsat
gs t
V
I V V V
V V


 
  
 
 
 
+
-
Vgs > Vt
n+ n+
+
-
Vgd
< Vt
Vds
> Vgs
-Vt
p-type body
b
g
s d Ids

CMOS VLSI Design
nMOS I-V Summary
 
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V



 

  
   
 

 


 


 Shockley 1st
order transistor models

CMOS VLSI Design
Example
 We will be using a 0.6 m process for your project
– From AMI Semiconductor
– tox = 100 Å
–  = 350 cm2
/V*s
– Vt = 0.7 V
 Plot Ids vs. Vds
– Vgs = 0, 1, 2, 3, 4, 5
– Use W/L = 4/2 
 
14
2
8
3.9 8.85 10
350 120 μA/V
100 10
ox
W W W
C
L L L
 


 
   
  
   
  
 
0 1 2 3 4 5
0
0.5
1
1.5
2
2.5
Vds
I
ds
(mA)
Vgs
= 5
Vgs = 4
Vgs = 3
Vgs
= 2
Vgs
= 1

CMOS VLSI Design
pMOS I-V
 All dopings and voltages are inverted for pMOS
– Source is the more positive terminal
 Mobility p is determined by holes
– Typically 2-3x lower than that of electrons n
– 120 cm2
/V•s in AMI 0.6 m process
 Thus pMOS must be wider to
provide same current
– In this class, assume
n / p = 2
-5 -4 -3 -2 -1 0
-0.8
-0.6
-0.4
-0.2
0
I
ds
(mA)
Vgs
= -5
Vgs = -4
Vgs = -3
Vgs
= -2
Vgs = -1
Vds

CMOS VLSI Design
Capacitance
 Any two conductors separated by an insulator have
capacitance
 Gate to channel capacitor is very important
– Creates channel charge necessary for operation
 Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is
associated with source/drain diffusion

CMOS VLSI Design
Gate Capacitance
 Approximate channel as connected to source
 Cgs = oxWL/tox = CoxWL = CpermicronW
 Cpermicron is typically about 2 fF/m
n+ n+
p-type body
W
L
tox
SiO2
gate oxide
(good insulator, ox = 3.90)
polysilicon
gate

CMOS VLSI Design
Diffusion Capacitance
 Csb, Cdb
 Undesirable, called parasitic capacitance
 Capacitance depends on area and perimeter
– Use small diffusion nodes
– Comparable to Cg
for contacted diff
– ½ Cg for uncontacted
– Varies with process

CMOS VLSI Design: Transistor theory lect3-transistors.ppt

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