This document provides an overview and outline of key topics in implementing a processor, including: - It describes building a datapath and control unit to implement a simple MIPS processor, including functional units like registers, ALU, and memory. - It explains the flow of data and control through the processor, from fetching instructions from memory to executing operations and writing results. - It discusses adding multiplexors and control lines to direct data between functional units based on the instruction, as well as pipelining the design for improved performance.

1. Chapter3 Notes: Hennessy | Arithmetic for Computers 1
Chapter 4 (Hennessy 4th Ed): The Processor
Supplement(s):
Outline:
 Introduction
 Logic DesignConventions
 Building a Datapath
 A Simple Implementation Scheme
 An Overview of Pipelining
 Pipelined Datapath and Control
 Data Hazards: Forwarding versus Stalling
 Control Hazards
 Exceptions
 Parallelism and Advanced Instruction-Level Parallelism
 Fallacies and Pitfalls
 Concluding Remarks
Content
INTRODUCTION
Chapter 1 explains that the performance of a computer is determinedbythree keyfactors:instructioncount, clock cycle time, and clockcycles per instruction
(CPI). Chapter 2 explains that the compiler andthe instructionset architecture determine the instructioncount requiredfor a given program. However, the
implementationof the processor determines boththe clockcycle time andthe number of clock cycles per instruction. Inthis chapter, we construct the
datapathandcontrol unit for two different implementations of the MIPS instructionset. This chapter contains anexplanationof the principlesandtechniques
usedinimplementing a processor, starting witha highlyabstract andsimplifiedoverview in this section. It is followedby a sectionthat buildsup a datapath
and constructs a simple versionof a processor sufficient to implement aninstructionset like MIPS. The bulk ofthe chapter covers a more realistic pipelined
MIPS implementation, followed bya sectionthat develops the concepts necessaryto implement more complex instructionsets, l ike the x86.
A Basic MIPS Implementation – We will be examining an implementationthat includes a subset of the core MIPS instructionset:
 The memory-reference instructions loadword(lw) and store word (sw)
 The arithmetic-logical instructions add,sub,AND,OR, and slt
 The instructions branchequal (beq)andjump(j), whichwe addlast
This subset doesnot include all the integer instructions (for example, shift, multiply, anddivide are missing), nor does it include anyfloating-point instructions.
However, the keyprinciplesusedincreating a datapathanddesigningthe control are illustrated. The implementationof the remaining instructions is similar.
In examiningthe implementation, we willhave the opportunityto see how the instructionset architecture determines manyaspects ofthe implementation,
and howthe choice ofvarious implementation strategies affects the clock rate and CPI for the computer. Manyof the keydesign principles introducedin
Chapter 1 can be illustratedbylooking at the implementation, suchas the guidelines Make the common case fast and Simplicityfavors regularity. In addition,
most concepts usedto implement the MIPS subset inthis chapter are the same basic ideas that are used to construct a broads pectrumof computers, from
high-performance servers to general- purpose microprocessors to embeddedprocessors.
An Overview of the Implementation – For everyinstruction, the first twosteps are identical:1) Sendthe program counter (PC) to the memorythat contains
the code and fetch the instructionfrom that memory. 2) Readone or two registers, usingfields of the instructionto select the registers to read. For the load
word instruction, we needto readonlyone register, but most other instructions require that we readtwo registers.
After these two steps, the actions requiredto complete the instruction depend onthe instruction class. Fortunately, for eachof the three instructionclasses
(memory-reference, arithmetic-logical, and branches), the actions are largelythe same, independent of the exact instruction. The simplicityand regularity of
the MIPS instruction set simplifies the implementation bymakingthe executionof manyof the instructionclasses similar. For example, allinstruction classes,
except jump, use the arithmetic-logical unit (ALU) after reading the registers. The memory-reference instructions use the ALU for anaddress calculation, the
arithmetic-logical instructions for the operationexecution, and branches for comparison. After using the ALU, the actions required to complete various
instruction classes differ. A memory-reference instructionwill needto accessthe memoryeither to readdata for a load or write data for a store. An
arithmetic-logical or loadinstruction must write the data fromthe ALU or memorybackintoa register. Lastly, for a branchinstruction, we mayneed to change
the next instructionaddress basedon the comparison;otherwise, the PCshouldbe incrementedby4 to get the address of the next instruction.

2. Chapter3 Notes: Hennessy | Arithmetic for Computers 2
FIGURE4.1 An abstract view ofthe implementation ofthe MIPS subset showing the major functional units
and the major connectionsbetween them. Allinstructions startby using theprogram counter to supply the
instruction address to the instruction memory.After theinstructionis fetched,theregister operands used by
an instruction are specified by fields ofthat instruction. Once the registeroperands have been fetched, they
can be operated onto computea memory address (for a load or store), to computean arithmetic result (for
an integer arithmetic-logicalinstruction),or a compare (for a branch). Iftheinstructionis an arithmetic-logical
instruction, theresult fromtheALU mustbe written to a register. Ifthe operation is a load or store, the ALU
result is used as an address to either store a valuefrom the registers or load a value from memory into the
registers. The result fromtheALU or memory is writtenback intotheregister file. Branches requiretheuse of
the ALU outputto determinethe nextinstruction address, which comes either from the ALU (where the PC
and branch offset aresummed) or from an adder that increments thecurrent PC by 4. The thick lines interconnecting the funct ional units represent buses, which consist of
multiplesignals. The arrows are used toguide the reader inknowing how information flows. Sincesignallines may cross, weexplicitly showwhen crossing lines areconnected by
the presence of a dot where the lines cross.
Figure 4.1 shows thehigh-levelview ofa MIPS implementation, focusing onthevarious functionalunits and their interconnection.Althoughthis figureshows most ofthe flow of
data through theprocessor, itomits twoimportant aspects ofinstructionexecution. First, inseveral places, Figure4.1shows data going to a particular unit as coming from two
different sources.For example, thevalue written into thePC can comefrom one oftwoadders, the data written intotheregister file can come from either the ALU or the data
memory, and thesecond inputto theALU cancomefroma register ortheimmediate field oftheinstruction.In practice, these data lines cannot simply be wired together; we
must add a logic elementthatchooses fromamong the multiplesources andsteers oneofthosesources to its destination. This selectionis commonly donewitha devicecalled a
multiplexor, although this devicemight betterbe called a data selector. Appendix C describes themultiplexor,whichselects from among several inputs basedon thesetting ofits
control lines. The control lines are set based primarily on information taken from the
instruction being executed.
The secondomissionin Figure4.1is that several oftheunits mustbe controlleddepending on
the type ofinstruction. For example,the data memory must read on a load and write on a
store. The registerfilemustbe written on a loadandanarithmetic-logicalinstruction.And, of
course, the ALUmust perform oneofseveraloperations,as wesaw inChapter2. (AppendixC
describes the detailed designof theALU.) Like the multiplexors, theseoperations aredirected
by control lines that are set on the basis ofvarious fields in the instruction.
FIGURE 4.2 The basic implementation of the MIPS subset, including the necessary
multiplexorsand control lines. Thetop multiplexor (“Mux”) controls whatvaluereplaces the
PC (PC +4 or the branch destinationaddress); themultiplexor is controlled by the gate that
“ANDs” together the Zero output ofthe ALU and a control signal that indicates that the
instruction is a branch. Themiddle multiplexor, whoseoutput returns to the register file, is
used to steer the output of theALU (in thecase ofan arithmetic-logical instruction) or the
output ofthe data memory (inthecase ofa load) for writing into theregister file. Finally, the
bottom most multiplexor is used to determine whether the second ALU input is from the
registers (for an arithmetic-logical instruction OR a branch) or from the offset field ofthe
instruction (for a load or store). The added controllines arestraightforward and determine
the operation performed at the ALU, whether the data memory should read or write, and
whether the registers should perform a write operation. The control lines are shown in color to make them easier to see.
Figure 4.2 shows thedatapathof Figure4.1 with thethreerequired multiplexors added, as well as control lines for the major functional units. A control unit, which has the
instruction as an input, is used todeterminehow toset the controllines for thefunctional units and twoofthe multiplexors. Thethird multiplexor, which determines whether PC
+ 4 or the branchdestination address is written into the PC, is set based on the Zero output ofthe ALU, which is used to pe rform the comparison ofa beq instruction. The
regularity and simplicity of the MIPS instruction set means that a simple decoding process can be used to determine how to set the c ontrol lines.
In the remainder of thechapter, werefinethis view to fill inthedetails, which requires that weadd further functionalunits, increasethenumber ofconnections between units,
and, ofcourse,enhance a control unitto control what actions aretaken for differentinstruction classes. Sections 4.3and 4.4 describea simpleimplementationthat uses a single
long clock cyclefor every instruction and follows thegeneralform ofFigures 4.1and4.2. Inthis firstdesign, every instructionbegins execution on oneclock edge and completes
execution onthenext clock edge.Whileeasier tounderstand,this approach is not practical,since the clock cyclemustbe stretchedto accommodatethelongestinstruction. After
designing the control for this simple computer, we will look at pipelined implementation with all its complexities, including exceptions.
LOGIC DESIGN CONVENTIONS
This section reviews a few keyideas in digitallogic that wewill useextensively inthis chapter. The datapathelements in theMIPS implementationconsist oftwo differenttypes of
logic elements: elements that operateon data values andelements thatcontainstate. The elements thatoperateon data values areallcombinational(An operational element,
such as an AND gateor an ALU.), which means thattheiroutputs depend only on thecurrent inputs. Giventhesame input, a combinational element always produces the same
output. The ALU shown inFigure 4.1 is an exampleofa combinational element. Givena setofinputs, it always produces the s ame output because it has no internal storage.
Other elements in the designarenotcombinational,but instead contain state. An elementcontains state ifit has someinternal storage.We call theseelements state elements(A
memory element, such as a register or a memory.) because, ifwepulled the power plug on the computer, wecould restartit by loading the stateelements wi th the values they
containedbefore wepulledtheplug. Furthermore, ifwesaved andrestored thestateelements,it wouldbeas if thecomputer had never lostpower.Thus, thesestate elements
completely characterize the computer. In Figure 4.1, the instruction and data memories, as well as the registers, are all exa mples ofstate elements.
A stateelement has atleasttwo inputs and one output.The required inputs are the data valueto bewritteninto theelement and the clock, which determines when the da ta
value is written.The output froma stateelement provides thevaluethatwas written inanearlier clock cycle. For example, one ofthe logically simplest stateelements is a D-type
flip-flop, which has exactly thesetwo inputs (a value anda clock) andoneoutput. Inaddition to flip-flops, our MIPS implementation also uses two other types ofstate elements:
memories andregisters, both of whichappear in Figure4.1. Theclock is used todeterminewhen the state elementshould bewritten; a state element can be read at any time.
Logic components that contain stateare alsocalled sequential, becausetheir outputs depend onboththeirinputs and thecontents oftheinternalstate. For example, the output
from the functional unit representing the registers depends both on the register numbers supplied and on what was written int o the registers previously.

3. Chapter3 Notes: Hennessy | Arithmetic for Computers 3
We will use the word asserted (The signal is logically highor true) toindicatea signalthat is logically high and assertto specify that a signal should be driven logically high, and
deassert or deasserted (The signal is logically low or false) to represent logically low.
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