Basic electrical properties of MOSFET circuits.pdf

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Outline
• Introduction to VLSI Design Flow
• Introduction to IC technology
• Ids vs Vds Relationships
• Aspects of MOS transistor
• Threshold Voltage
• MOS transistor conductance
• Output Conductance
• Figure of Merit.
• Fabrication process:
• nMOS, pMOS and CMOS.
• Alternate pull up forms in inverter circuits
• Pull-up to Pull-down Ratio for nMOS inverter driven by another nMOS inverter
• basic current mirror
• CMOS Inverter
• Latch-up in CMOS circuits

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VLSI Design Flow

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IC Technology
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What advantages do ICs have over discrete components?
➢ Size: Sub-micron, millimeter/nanometer.
➢ Speed and Power: Smaller size of IC components yields higher speed and lower power consumption due
to smaller parasitic resistances, capacitances and inductances.
Switching between ‘0’and ‘1’much faster on chip than between chips.
Lower power consumption => less heat => cheaper power supplies =>
reduced system cost.
➢ Integrated circuit manufacturing is versatile. Simply change the mask to change the design.
However, designing the layout (changing the masks) is usually the most time consuming task in IC
design.

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IC Technology
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• Early developments of the Integrated Circuit (IC) go back to 1949.
• German engineer Werner Jacobi filed a patent for an IC like semiconductor
amplifying device showing five transistors on a common substrate in a 2-
stage amplifier arrangement.
• Jacobi disclosed small cheap of hearing aids.
Invention

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Inventor Year Circuit Remark
Fleming 1904
1906
Vacuum tube diode
Vacuum triode
large expensive, power- hungry,
unreliable
William Shockley (Bell
labs)
1945 Semiconductor replacing vacuum tube
Bardeen and Brattain
and Shockley (Bell
labs)
1947 Point Contact transfer
resistance device “BJT”
Driving factor of growth of the VLSI
technology
Werner Jacobi
(SiemensAG)
1949 1st IC containing amplifying
Device 2stage amplifier
No commercial use reported
Shockley 1951 Junction Transistor “Practical form of transistor”
Jack Kilby
(Texas Instruments)
July 1958 Integrated Circuits F/F With 2-T
Germanium slice and gold wires
Father of IC design
Fairchild
Semiconductor And
Texas
1061 First Commercial
IC
Frank Wanlass
(Fairchild Semiconductor)
1963 CMOS
Federico Faggin
(Fairchild Semiconductor)
1968 Silicon gate IC technology Later Joined Intel to lead first CPU
Intel 4004 in 1970
2300 T on 9mm2

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1965 - Moore's law
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Gordon E. Moore - Chairman Emeritus of Intel Corporation
➢ 1965 - observed trends in industry - of transistors on ICs vs. release dates:
➢ Noticed number of transistors doubling with release of each new IC generation
➢ release dates (separate generations) were all 18-24 months apart
➢ Moore’s Law:
➢ “The number of transistors on an integrated circuit will double every 18 months”
➢ The level of integration of silicon technology as measured in terms of number of devices per IC
➢ Semiconductor industry has followed this prediction with surprising accuracy.
"Cramming more components onto integrated circuits".

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1965 - Moore's law
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Discrete vs Integrated Circuit Design
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Activity/Item Discrete circuits Integrated Circuits
ComponentAccuracy Well Known Poor absoluteAccuracies
Bread boarding Yes No
Fabrication Independent Very dependent
Physical Implementation PC Layout Layout, verification and
Extraction
Parasitic Not important Must be included in the
design
Simulation Model Parameters well known Model parameters vary widely
Testing Generally complete testing is possible Must be considered before design
CAD Schematic capture Simulation, PC Board
layout
Schematic capture
Simulation, layout
Components All possible Active devices, capacitor, and
resistor

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IC Technology
Bipolar CMOS BiCMOS SOI SiGe GaAs
Category BJT CMOS
Power
Dissipation
Moderate
to High
less
Speed Faster Fast
Gm 4ms 0.4ms
Switch
implementation
poor Good
Technology
improvement
slower Faster
Why
CMOS
?
Lower
Power
Dissipation
High
packing
density
Scale down
more easily
Fully
restored
logic levels
Appr.
Equal rise
and fall
time

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MOSFETs
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MOSFETs have characteristics similar to JFETs and additional characteristics that make them very useful.
There are 2 types:
Depletion-Type MOSFET
Enhancement-Type MOSFET

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Depletion-Type MOSFET Construction
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The Drain (D) and Source (S) connect to the to n-
doped regions. These N-doped regions are
connected via an n-channel.
This n-channel is connected to the Gate (G) via
a thin insulating layer of SiO2.
The n-doped material lies on a p-doped
substrate that may have an additional terminal
connection called SS.

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Basic Operation
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Enhancement-Type MOSFET Construction
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The Drain (D) and Source (S) connect to the to n- doped regions.
These n-doped regions are connected via an n-channel.
The Gate (G) connects to the p-doped substrate via a thin
insulating layer of SiO2. There is no channel.
The n-doped material lies on a p-doped substrate that may
have an additional terminal connection called SS.

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Basic Operation and Characteristics
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If VGS is set at 0 V and a voltage applied between the drain and source of the device, the absence of an n- channel
(with its generous number of free carriers) will result in a current of effectively zero amperes— quite different from the
depletion- type MOSFET and JFET where ID = IDSS.
It is not sufficient to have a large accumulation of carriers (electrons) at the drain and source (due to the n-doped
regions) if a path fails to exist between the two.
If both VDS and VGS is set at some positive voltage greater than 0 V, then the positive potential at the gate will
pressure the holes (since like charges repel) in the p-substrate along the edge of the SiO2 layer to leave the area and
enter deeper regions of the p- substrate.
However, the electrons in the p-substrate (the minority carriers of the material) will be attracted to the positive gate
and accumulate in the region near the surface of the SiO2 layer. The SiO2 layer and its insulating qualities will prevent
the negative carriers from being absorbed at the gate terminal.

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Continued…
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As VGS increases in magnitude, the concentration of electrons near the
SiO2 surface increases until eventually the induced n-type region can
support a measurable flow between drain and source. The level of
VGS that results in the significant increase in drain current is called the
threshold voltage and is given the symbol VT.
Since the channel is non-existent with VGS=0 V and “enhanced” by the
application of a positive gate-to- source voltage, this type of MOSFET is
called an enhancement- type MOSFET.

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Continued…
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As VGS is increased beyond the threshold level, the density of free carriers in the induced channel will
increase, resulting in an increased level of drain current.
However, if we hold VGS constant and increase the level of VDS, the drain current will eventually reach a saturation level.
The levelling of ID is due to a pinching-off process depicted by the narrower channel at the drain end of the induced
channel
By applying KVL we get
If VGS is held fixed at some value such as 8 V and VDS is increased from 2 to 5V, the voltage will drop from
-6 to -3 V. This reduction in gate-to-drain voltage will in turn reduce the attractive forces for free carriers (electrons) in
this region of the induced channel, causing a reduction in the effective channel width.
Eventually, the channel will be reduced to the point of pinch-off and a saturation condition will be
established.

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Continued…
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MOSFET Symbols
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MOSFET vs BJT
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MOSFET applications
• Radiofrequency applications use MOSFET amplifiers extensively.
• MOSFET behaves as a passive circuit element.
• Power MOSFETs can be used to regulate DC motors.
• MOSFETs are used in the design of the chopper circuit.
Advantages of MOSFET
• MOSFETs operate at greater efficiency at lower voltages.
• Absence of gate current results in high input impedance producing high switching speed.
Disadvantages of MOSFET
• MOSFETs are vulnerable to damage by electrostatic charges due to the thin oxide layer.
• Overload voltages make MOSFETs unstable.

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MOSFET vs BJT
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Fabrication Processes
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Fabrication is the process of constructing an industrial
product. We can also define it as a set of methods to
manufacture an electronic device or product.
For example, silicon semiconductor chips, etc. In the case of
metals, fabrication is a process used to convert the raw
materials into the finished product. The basic fabrication processes of
the Integrated Circuits

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Sand / Ingot
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Sand
Silicon is the second most abundant element in
the earth's crust. Common sand has a high
percentage of silicon. Silicon – the starting
material for computer chips – is a
semiconductor, meaning that it can be readily
turned into an excellent conductor or an
insulator of electricity, by the introduction of
minor amounts of impurities.
Melted Silicon –
scale: wafer level (~300mm / 12 inch)
In order to be used for computer chips, silicon
must be purified so there is less than one alien
atom per billion. It is pulled from a melted state
to form a solid which is a single, continuous and
unbroken crystal lattice in the shape of a
cylinder, known as an ingot.
Monocrystalline Silicon Ingot –
scale: wafer level (~300mm / 12
inch)
The ingot has a diameter of 300mm
and weighs about 100 kg.

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Wafer Preparation
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The wafer preparation is the first step for IC fabrication. It involves cutting, shaping, and polishing the wafer
material to make it suitable for further fabrication. Some wafers are modified because of their sharp edges,
irregular surface, and shape to convert them to the required wafer.
A wafer is a thin material used for making various Integrated circuits and transistors. Wafer acts as a base for
such devices. The material of a wafer is the semiconductor, especially crystalline silicon. The silicon crystals
used for the wafer manufacturing are highly pure. The process of extracting pure metal from the melt is known
as a boule. The impurities are further added to the molten state of the material in a specific amount to make it
n-type or p- type.

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Oxidation – Create Oxide Film on Wafer Surface
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Oxidation is the process of adding oxygen. In a semiconductor, the oxygen and the silicon react to form silicon
dioxide. The oxidation is carried out in furnaces at high temperatures up to 1250 degrees Celsius. Oxidation is
classified as wet oxidation or dry oxidation. Both processes are widely used and have their own advantages and
disadvantages. Wet oxidation is fast, while dry oxidation has good electrical properties.
Wet oxidation is also known as steam. Both types of oxidation have excellent electrical insulation properties.
The deposition of silicon dioxide on the silicon wafer protects from many impurities. The dopants can be applied
only to areas not covered with the SiO2.

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Photolithography – Draw Circuit Design on Wafer
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ApplyingPhotoresist–
Photolithography is the processby which aspecific
patternis imprintedonthe wafer. Itstartswiththe
applicationof a liquidknown as photoresist, which is
evenlypouredontothewafer whileit spins.Itgets
its namefrom the fact that it is sensitiveto certain
frequencies of light(“photo”)andis resistant to
certain chemicalsthat will beusedlaterto remove
portionsof a layerof material (“resist”).
Exposure–
The photoresist is hardened, andportionsof it are exposed to
ultraviolet (UV)light, makingit soluble. The exposureis done
usingmasksthat actlike stencils,soonlyaspecificpattern of
photoresist becomessoluble.The maskhasanimageof the
patternthat needsto goonthe wafer;it is optically reduced
by a lens, andthe exposure tool steps and repeats acrossthe
wafer to formthe sameimagea largenumberof times.
ResistDevelopment–
The solublephotoresist is
removedby a chemical process,
leaving a photoresist pattern
determinedby what wasonthe
mask.
Next step is to draw a circuit design onto a wafer which is called the photolithography process. A photo mask
functions as the film. A photo mask is a glass substrate with a computer designed circuit pattern.

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Ion Implantation
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Ion Implantation–
The wafer with patterned photoresist is bombarded with a
beam of ions (positively or negatively charged atoms)
which become embedded beneath the surface in the
regions not covered by photoresist. This process is called
doping, because impurities are introduced into the silicon.
This alters the conductive properties of the silicon
(making it conductive or insulating, depending on the
type of ion used) in selected locations.
RemovingPhotoresist–
Afterion implantation, the photoresistis
removedandthe resulting wafer has a pattern
of dopedregions in which transistors will be
formed.
BeginTransistor Formation–
Here we zoominto a tiny part of the
wafer, where a singletransistor will be
formed. The greenregionrepresents
dopedsilicon. Today’s wafers canhave
hundreds of billions of suchregions
whichwill housetransistors.
Next step is to draw a circuit design onto a wafer which is called the photolithography process. A photo mask
functions as the film. A photo mask is a glass substrate with a computer designed circuit pattern.

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Ion Implantation
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Diffusion is a process of adding impurities atoms from a region with high concentration to a region of low
concentration. The dopants or impurity atoms are added to the silicon (semiconductor material), which
changes its resistivity.
Coating the thin film at a desired molecular or atomic level onto a wafer is called deposition. Since the coating is
so thin, precise and sophisticated technology is required to uniformly apply the thin film on a wafer to give the
semiconductor electrical characteristics. Ion implementation / Ion implantation is also required.

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Etching – Remove Unnecessary Materials
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Etch–
In order to create a fin for a tri-gate transistor, a
pattern of material called a hard mask (blue) is
applied using the photolithography process just
described. Then a chemical is applied to etch away
unwanted silicon, leaving behind a fin with a layer of
hard mask on top.
Removing Photoresist –
The hard mask is chemically removed,
leaving a tall, thin silicon fin which will
contain the channel of a transistor.
Now it is time to remove unnecessary materials from the wafer surface so that only the design pattern remains.
• Wet Etching: When chemical solutions are used for etching, it is called wet etching.
• Dry Etching: When gas or plasma is used, it is called dry etching.
This is done using a liquid or gas etching technique. All unnecessary materials are selectively removed to draw
the desired design.

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Metal Deposition (Metallization)
Ready Transistor –
This transistor is close to being finished.
Three holes have been etched into the
insulation layer (red color) above the
transistor. These three holes will be filled
with copper or other material which will
make up the connections to other
transistors.
Electroplating –
The wafers are put into a copper sulphate
solution at this stage. The copper ions are
deposited onto the transistor thru a process
called electroplating. The copper ions travel
from the positive terminal (anode) to the
negative terminal (cathode) which is
represented by the wafer.
After Electroplating –
On the wafer surface the
copper ions settle as a thin
layer of copper.

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Wafer Sort / Singulation
Wafer Sort –
This portion of a ready wafer is being put through a
test. A tester steps across the wafer; leads from its
head make contact on specific points on the top of
the wafer and an electrical test is performed. Test
patterns are fed into every single chip and the
response from the chip is monitored and compared
to “the right answer”.
Wafer Slicing –
The wafer is cut into pieces (called
die). The above wafer contains
future Intel processors codenamed
Ivy Bridge.
Selecting Die for Packaging –
The die that responded with the
right answer to the test patterns
will be packaged.

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Encapsulation or Packaging
Individual Die –
These are individual die which
have been cut out in the previous
step (singulation). The die shown
here is Intel’s first 22nm
microprocessor codenamed Ivy
Bridge.
Packaging –
The package substrate, the die and the heat
spreader are put together to form a completed
processor. The green substrate builds the electrical
and mechanical interface for the processor to
interact with the rest of the PC system. The silver
heat spreader is a thermal interface which helps
dissipate heat.
Processor –
Completed processor (Ivy Bridge in this
case). A microprocessor has been called
the most complex manufactured product
made by man. In fact, it takes hundreds
of steps – only the most important ones
have been included in this picture story -
in the world's cleanest environment (a
microprocessor fab).

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Semiconductor Manufacturing Process Flow Chart

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N-MOS Fabrication Process
Fig. (1) Pure Si single crystal
Si-substrate
Fig. (2) P-type impurity is lightly
doped
- - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - -
Fig. (3) SiO2 Deposited over si surface
Fig. (4) Photoresist is deposited
over SiO2 layer
Photoresist
Thick SiO2
(1 µm)
- - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm)
- - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - -

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Mask-1 is used to expose the SiO2
where S, D and G is to be formed.
Fig. (5) Photoresist layer is exposed to UV Light
through a mask
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Mask-1
Photoresist
Thick SiO2
(1 µm)
UV Light

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Fig. (6) Etching [HF acid is used] will remove SiO2 layer
which is in direct contact with etching solution
Thick SiO2
(1 µm)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Fig. (7) unpolymerised photoresist is also etched away
[using H2SO4]
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm)

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Fig. (10)A layer of photoresist is grown over polysilicon layer
Thick SiO2
(1 µm)
Thin SiO2
(0.1 µm)
Polysilicon
layer
Photoresist
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

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Mask-2 is used to deposit
Polysilicon to form gate.
Fig. (11) Photoresist is exposed to UV Light
UV Light
Mask-2
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

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Fig. (12) Etching will remove that portion of Thin SiO2 which is
not exposed to UV light
Thin SiO2
(0.1 µm)
Polysilicon
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Fig. (13) Polymerised photoresist is also stripped away
Thin SiO2
(0.1 µm)
Polysilicon used as GA
TE
(1 – 2 µm)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

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Fig. (14) n+ Doping to form SOURCE and DRAIN
- - - - - - - - - - - - - - - - - - - -
- - - -
- - - -
- - - -
- - - -
- - - - -
- - - - -
- - - - - - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm) Thin SiO2
(0.1 µm)
- - - - - -
- - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - n+ - - -
GA
TE
- - - -
- -
n+
SOURCE DRAIN
Fig. (15)A thick layer of SiO2 (1 µm) is again grown.
- - - - - - - - - - - - - - - - - - - -
- - - -
- - - -
- - - -
- - - -
- - - - -
- - - - -
- - - - - - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm)
- - - - - -
- - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - n+ - - -
- - - -
- -
n+
Thick SiO2
(1 µm)
Step - Metallization

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Fig. (16) Photoresist is grown over thick SiO2. Selected areas of the poly GATE and SOURCE and
DRAIN are exposed where contact cuts are to be made
- - - - - - - - - - - - - - - - - - - -
- - - -
- - - -
- - - -
- - - -
- - - - -
- - - - -
- - - - - - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm)
- - - - - -
- - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - n+ - - -
- - - -
- -
n+ Thick SiO2
(1 µm)
Mask-3
Mask-3 is used to make contact cuts for S, D and G.
Photoresist
UV Light
Step - Metallization

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Fig. (17) The region of photoresist which is not exposed by UV light will become soft. This
unpolymerised photoresist and SiO2 below it are etched away.
- - - - - - - - - - - - - - - - - - - -
- - - -
- - - -
- - - -
- - - -
- - - - -
- - - - -
- - - - - - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm)
- - - - - -
- - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - n+ - - -
- - - -
- -
n+ Thick SiO2
(1 µm)
Mask-3
Photoresist

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Fig. (18) The contact cuts are formed for S, D and G (hardened photoresist is stripped away).
- - - - - - - - - - - - - - - - - - - -
- - - -
- - - -
- - - -
- - - -
- - - - -
- - - - -
- - - - - - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm)
- - - - - -
- - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - n+ - - -
- - - -
- -
n+ Thick SiO2
(1 µm)
Mask-3
Photoresist

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Fig. (19) Metal (aluminium) is deposited over the surface of whole chip (1 µm thickness).
- - - -
- - - -
- - - -
- - - -
- - - - -
- - - - -
- - - - - - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm)
- - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - n+ - - -
- - - -
- -
n+ Thick SiO2
(1 µm)
Metal (1µm)

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Fig. (20) Photoresist is deposited over the metal.
- - - - - - - - - - - - - - - - - - - -
- - - -
- - - -
- - - -
- - - -
- - - - -
- - - - -
- - - - - - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm)
- - - - - -
- - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - n+ - - -
- - - -
- -
n+ Thick SiO2
(1 µm)
Metal (1µm)
Photoresist

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Mask-4 is used to deposit metal in contact cuts of S, D and G.
Fig. (21) UV Light is passed through Mask-4 (with a aim of removing all metal other than metal in
contact-cuts).
- - - - - - - - - - - - - - - - - - - -
- - - -
- - - -
- - - -
- - - -
- - - - -
- - - - -
- - - - - - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm)
- - - - - -
- - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - n+ - - -
- - - -
- -
n+ Thick SiO2
(1 µm)
Mask-4
Photoresist
Metal (1µm)
UV Light

48
Fig. (22) Photoresist and metal which is not exposed to UV light are etched away.
- - - - - - - - - - - - - - - - - - - -
- - - -
- - - -
- - - -
- - - -
- - - - -
- - - - -
- - - - - - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm)
- - - - - -
- - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - n+ - - -
- - - -
- -
n+ Thick SiO2
(1 µm)
Mask-4
Photoresist
Metal (1µm)

49
Fig. (23) Final n-MOS Transistor
- - - - - - - - - - - - - - - - - - - -
- - - -
- - - -
- - - -
- - - -
- - - - -
- - - - -
- - - - - - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - -
- - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - n+ - - -
- - - -
- -
n+
SOURCE DRAIN
GA
TE

50
P-MOS Fabrication Process

51
CMOS (Complementary Metal Oxide Semiconductor)
In CMOS technology, both N-type and P-type transistors are used to design logic functions.
In CMOS logic gates a collection of n-type MOSFETs is arranged in a pull-down network between the output and
the low voltage power supply rail (Vss or quite often ground).
The same signal which turns ON a transistor of one type is used to turn OFF a transistor of the other type.
This characteristic allows the design of logic devices using only simple switches, without the need for a pull-up
resistor

52
CMOS Fabrication
• CMOS transistors are fabricated on silicon wafer
• Lithography process similar to printing press
• On each step, different materials are deposited or etched
• Easiest to understand by viewing both top and cross-section of wafer
in a simplified manufacturing process

53
Inverter Cross-section
• Typically use p-type substrate for nMOS transistors
• Requires n-well for body of pMOS transistors
n+
p substrate
p+
n well
A
Y
GND VDD
n+ p+
SiO2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor

54
Well and Substrate Taps
n+
p substrate
p+
n well
Y
• Substrate must be tied to GND and n-well to VDD
• Metal to lightly-doped semiconductor forms poor connection called
Shottky Diode
• Use heavily doped well and substrate contacts / taps
A
GND VDD
n+
p+
substrate tap well tap
n+ p+

55
Inverter Mask Set
• Transistors and wires are defined by masks
• Cross-section taken along dashed line
GND VDD
Y
A
substrate tap well tap
nMOS transistor pMOS transistor

56
Detailed Mask Views
• Six masks
• n-well
• Polysilicon
• n+ diffusion
• p+ diffusion
• Contact
• Metal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well

57
Fabrication Steps
• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
• Cover wafer with protective layer of SiO2 (oxide)
• Remove layer where n-well should be built
• Implant or diffuse n dopants into exposed wafer
• Strip off SiO2
p substrate

58
Oxidation & Photoresist
• Grow SiO2 on top of Si wafer
• 900 – 1200 C with H2O or O2 in oxidation furnace
p substrate
SiO2
▪ Spin on photoresist
• Photoresist is a light-sensitive organic polymer
• Softens where exposed to light
p substrate
SiO2
Photoresist

59
Lithography
p substrate
SiO2
Photoresist
• Expose photoresist through n-well mask
• Strip off exposed photoresist

60
Etch
p substrate
SiO2
Photoresist
• Etch oxide with hydrofluoric acid (HF)
• Seeps through skin and eats bone; nasty stuff!!!
• Only attacks oxide where resist has been exposed

61
Strip Photoresist
• Strip off remaining photoresist
• Use mixture of acids called piranah etch
• Necessary so resist doesn’t melt in next step
p substrate
SiO2

62
n-well
• n-well is formed with diffusion or ion implantation
• Diffusion
• Place wafer in furnace with arsenic gas
• Heat until As atoms diffuse into exposed Si
• Ion Implanatation
• Blast wafer with beam of As ions
• Ions blocked by SiO2, only enter exposed Si
n well
SiO2

63
Strip Oxide
• Strip off the remaining oxide using HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of steps
p substrate
n well

64
Polysilicon
• Deposit very thin layer of gate oxide
• < 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon layer
• Place wafer in furnace with Silane gas (SiH4)
• Forms many small crystals called polysilicon
• Heavily doped to be good conductor
Thin gate oxide
Polysilicon
p substrate
n well

65
Polysilicon Patterning
• Use same lithography process to pattern polysilicon
Polysilicon
p substrate
Thin gate oxide
Polysilicon
n well

66
Self-Aligned Process
p substrate
n well
• Use oxide and masking to expose where n+ dopants should be
diffused or implanted
• N-diffusion forms nMOS source, drain, and n-well contact

67
N-diffusion
p substrate
n well
n+ Diffusion
• Pattern oxide and form n+ regions
• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned gates because it
doesn’t melt during later processing

68
N-diffusion cont.
• Historically dopants were diffused
• Usually, ion implantation today
• But regions are still called diffusion
n well
p substrate
n+
n+ n+

69
P-Diffusion
• Similar set of steps form p+ diffusion regions for pMOS source and
drain and substrate contact
p+ Diffusion
p substrate
n well
n+
n+ n+
p+
p+
p+

70
Contacts
• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+
n+ n+
p+
p+
p+
Contact

71
Metallization
• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires
p substrate
Metal
Thick field oxide
n well
n+
n+ n+
p+
p+
p+
Metal

72
Latch-UP
What is Latch-up?
• Latch-up is a condition that can occur in a circuit fabricated in a bulk CMOS technology.
When a chip is in a state of latch –up it draws a large current from the power supply but
does not function in response to input stimuli. A chip may be operating normally and then
enter a state of latch-up; in this case, removing and reconnecting the power supply may
restore operations.
In other words
•Latch-up is the creation of a low impedance path between the
power supply rails.
• Latch-up is caused by the triggering of parasitic bipolar
structures within an integrated circuit when applying a current or
voltage stimulus on an input, output, or I/O pin or by an over-
voltage on the power supply pin.

73
Latch-up in CMOS
• Shown alongside is a CMOS transistor consisting of an NMOS and a PMOS device.
• Q1 and Q2 are parasitic transistor elements residing inside it.
• Q1 is double emitter pnp transistor whose base is formed by n well substrate of PMOS, two
emitters are formed by source and drain terminal of PMOS and collector is formed by substrate(p
type) of NMOS.
• The reverse is true for Q2. The two parasitic transistors form a positive feedback loop and is
equivalent to an SCR (as stated earlier).

74
Techniques to minimize latchup sensitivity
• Increasing PMOS-NMOS spacing
• Guard rings to form
additional collectors
for the parasitic transistors
• CMOS processes:
• Epitaxial layer instead of bulk CMOS
• Retrograde well
• Oxide trenches between
the NMOS and PMOS devices
www.analog.com

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