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Workshop Outline DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 1 10:00am – 10:05am Dennis Brophy Welcome 10:05am – 10:45am Sharon Rosenberg UVM Concepts and Architecture 10:45am – 11:25am Tom Fitzpatrick UVM Sequences and Phasing 11:25am – 11:40am Break 11:40am – 12:20pm Janick Bergeron UVM TLM2 and Register Package 12:20pm – 12:50pm Ambar Sarkar Putting Together UVM Testbenches 12:50pm – 1:00pm All Q & A
Accellera at DAC DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 2 • Accellera Breakfast at DAC: UVM User Experiences – An Accellera event sponsored by Cadence, Mentor, and Synopsys – Tuesday, June 7th, 7:00am-8:30am, Room 25AB • Accellera IP-XACT Seminar – An introduction to IP-XACT, IEEE 1685, Ecosystem and Examples – Tuesday, June 7th, 2:00pm-4:00pm, Room 26AB • Birds-Of-A-Feather Meeting – Soft IP Tagging Standardization Kickoff – Tuesday, June 7, 7:00 PM-8:30 PM, Room 31AB
Workshop Outline DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 3 10:00am – 10:05am Dennis Brophy Welcome 10:05am – 10:45am Sharon Rosenberg UVM Concepts and Architecture 10:45am – 11:25am Tom Fitzpatrick UVM Sequences and Phasing 11:25am – 11:40am Break 11:40am – 12:20pm Janick Bergeron UVM TLM2 and Register Package 12:20pm – 12:50pm Ambar Sarkar Putting Together UVM Testbenches 12:50pm – 1:00pm All Q & A
UVM Transaction Level Modeling (TLM2) • Janick Bergeron Synopsys
TLM-1.0 • Unidirectional put/get interfaces •Initiator •Target •Initiator •Target •put •get • Simple message-passing semantics • No response model – E.g. What did I read back?? • Never really caught on in SystemC DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 5
Why TLM-2.0? DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 6 • Better interoperability over TLM- 1.0 – Semantics – Pre-defined transaction for buses • Performance – Pass by reference (in SystemC) – Temporal decoupling
TLM-2.0 in SV vs SC • Blocking transport interface • Nonblocking transport interfaces • Direct memory interface • Debug transport interface • Initiator sockets • Target sockets • Generic payload • Phases • Convenience sockets • Payload event queue • Quantum keeper • Instance-specific extensions • Non-ignorable and mandatory extensions • Temporal decoupling DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 7
TLM-2.0 Semantics • Blockin g – When the call returns, the transaction is done – Response is annotated • Nonblocking – Call back and forth • Protocol state changes • Transaction is updated •Initiat or •Targe t •Initiat or •Targe t DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 8
Generic Payload Attributes DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 9 Attribute Type Modifiable? Command uvm_tlm_command_e No Address bit [63:0] Interconnect only Data byte unsigned [ ] Yes (read command) Data length int unsigned No Byte enable pointer byte unsigned [ ] No Byte enable length int unsigned No Streaming width int unsigned No Response status uvm_tlm_response_status_e Target only Extensions uvm_tlm_extension_base [ ] Yes • Pre-defined bus transaction
Connecting to SystemC • Tool-specific mechanism – Not part of UVM • SystemVerilog • SystemC •Copy across at method call and return DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 10
TLM-2.0 Bridge Between SV & SC • Proxy sockets terminate the TLM2 connections in each language – Create SV/SC bridge •Initiat or •Targe t •Pack/unpack •Proxy Trgt •Proxy Init •TLM2 Bridge •Predefine d for GP in VCS • User-defined for GP extensions or non-GP • Unaware of language crossing • Unaware of language crossing DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 11
UVM Register Model • Janick Bergeron Synopsys
Overall Architecture Adapter Generic physical r/w Backdoor Any bus agent Register Model Pre-Defined SePqrue- eDnecfeinsed SUeqseure- nDceefisne d Sequence s Pre-Defined SePqrue- eDnecfeinsed SePqruee- Dnecfeinsed Sequences DUT Spec Generator Abstract read/writ e Bus- specific r/w item DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 13
Specification & Generation Register Model IP-XACT Generator System RDL SQL CSV MS- Word ... UVM UVM X EDA Vendors Generator Generator Generator DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 14
Physical Interfaces • Register model abstracts – Physical interfaces – Addresses – Endiannes s Register Model User perspectiv e R1.read(...); ... R2.write(...); ... R3.read(...); R1 R2 R3 DUT may change DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 15 Perspective stays the same
Mirror • Register model mirrors content of registers in DUT – “Scoreboard” for registers – Updated on read and write() – Optionally checked on read() Register Model R1 R2 R3 R1 R3 R2 API DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 16
Back-door Access • Must define HDL path to register in DUT – Generator-specific • Access RTL directly in zero-time via VPI – May affect simulator performance R1 R2 R3 R1 R3 R2 API Mirror is DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 17 implicitly updated
Programmer’s View R0 R1 R2 R0 F1 F2 F3 F4... ...F4 F5 F6 F5 F6 F5 F6 F7 F8 F9 F10 F7 F8 F9 F10 F7 F8 F9 F10 M0 erifying Blocks to IP to SOCs and Systems A[0] A[1] A[255] RF0[0] RF1[0] RF0[0] RF1[0] RF0[7] RF1[7] M0[0..65535] Array of Registers Array of Register Files Memory Multi-address Register DAC Workshop on Universal Verification Methodology (UVM) - V 18
Class View • One class per field • One class per register – Name – Addres s – Contained fields – Read/Write methods F1 F2 F3 R0 R0 R1 R2 F5 F6 F5 F6 F5 F6 A[0] A[1] A[255] F7 F8 F9 F10 RF0[0] RF1[0] RF0[0] RF1[0] F9 F10 F7 F8 F9 F10 RF0[7] RF1[7] M0[0..65535] F4... ...F4 M0 erifying Blocks to IP to SOCs and Systems F7 F8 class R1_reg extends uvm_reg; uvm_reg_field F1; uvm_reg_field F2; uvm_reg_field F3; endclass Generated Make sure names are different from base class methods DAC Workshop on Universal Verification Methodology (UVM) - V 19
Class View • One class per block – Name, Base address – Contained registers, register files, memories • May be arrays • Optional: contained fields R1 R0 R2 A[0] A[1] A[255] RF0[0] RF1[0] RF0[0] RF1[0] RF0[7] RF1[7] class B_blk extends uvm_reg_block; R0_reg R0; R1_reg R1; R2_reg R2; A_reg A[256]; RF_rfile ovm_ral_mem RF[8]; M0; endclass Generate d Make sure names are different from base class methods R0 F1 F3F 2 F4... ...F4 F5 F6 F5 F6 F5 F6 F7 F8 F9 F10 F7 F8 F9 F10 F7 M0[0..65535] DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 20
API View • Methods in relevant class instance R0 R1 R2 R0 F1 F2 F3 F4... ...F4 F5 F6 F5 F6 F5 F6 F7 F8 F9 F10 F7 F8 F9 F10 F7 F8 F9 F10 M0 erifying Blocks to IP to SOCs and Systems A[0] A[1] A[255] RF0[0] RF1[0] RF0[0] RF1[0] RF0[7] RF1[7] blk.R0.get_full_name() blk.F4.read(...) blk.A[1].write(...) blk.A[255].F5.write(...) foreach (blk.RF[i]) begin blk.RF[i].R0.F7.read(..._); end blk.M0.read(...) M0[0..65535] DAC Workshop on Universal Verification Methodology (UVM) - V 21
Reading and Writing DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 22 • Specify target register by hierarchical reference in register model – Compile-time checking • Use read() and write() method on – Registe r – Field – Memor y blk.blk[2].regfile[4].reg.fld blk.blk[2].regfile[4].reg.fld.read(...); blk.mem.write(...); By-name API also available
Register Sequences DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 23 • Sequences accessing registers should be virtual sequences – Not associated with a particular sequencer type • Contain a reference to register model • Access registers in body() task class my_test_seq extends uvm_sequence; my_dut_model regmodel; virtual task body(); regmodel.R1.write(...); regmodel.R2.read(...); ... endtask endclass
Register Sequences DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 24 • Includes pre-defined sequences – Check reset values – Toggle & check every bit – Front-door/back-door accesses – Memory walking
Introspection • Rich introspection API Block Register Field Register File Map get_regfile() get_maps() is_in_map() get_offset() get_block() get_blocks() get_parent() get_parent() get_fields() get_maps() get_registers() get_access() get_reset() get_n_bits() get_lsp_pos() is_volatile() DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 25
Coverage Models • Register models may contain coverage models – Up to the generator • Not instantiated by default – Can be large. Instantiate only when needed. – To enable: • Not collected by default – To recursively enable uvm_reg::include_coverage(“*”, UVM_CVR_ALL); All coverage models In all blocks and registers blk.set_coverage(UVM_CVR_ALL); All coverage models in block DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 26
Customization Opportunities Register Model Spec Generator Pre-Build Post-Build Best Options, value- add DON’T! Factory Callbacks DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 27
There’s a LOT more! DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 28 • DUT integration • Multiple interfaces • Randomization • Vertical Reuse • “Offline” access • User-defined front-door accesses • Access serialization • Pipelined accesses
Workshop Outline DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 29 10:00am – 10:05am Dennis Brophy Welcome 10:05am – 10:45am Sharon Rosenberg UVM Concepts and Architecture 10:45am – 11:25am Tom Fitzpatrick UVM Sequences and Phasing 11:25am – 11:40am Break 11:40am – 12:20pm Janick Bergeron UVM TLM2 and Register Package 12:20pm – 12:50pm Ambar Sarkar Putting Together UVM Testbenches 12:50pm – 1:00pm All Q & A
Putting Together UVM Testbenches •Ambar Sarkar Paradigm Works, Inc.
Agenda DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 31 • Case studies – Several UVM1.0 environments deployed – Currently in production – Novice to sophisticated teams • Getting started with UVM is relatively easy – Basic tasks remain simple – Were able to use a “prescriptive” approach – Iteratively developed and scales to any complexity • Advanced uses – Unit to system-level – VIP Stacking/Layering
Implementing Basic Steps Connect DUT to testbench Send clocks and resets Initialize the DUT Send traffic Add checking Write tests Once plumbing in place, a simple prescriptive approach works DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 32 Increasing sophisticatio n, but scalable
Example Host Interface Read/Write Packet Input Packet Output 1 Channel Engine Packet Output 3 Packet Output 2 DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 33
Example Environment in UVM DUT test cases ... unit_tb interrupt scoreboar d packet scoreboard host agent Config: active Config: active pi agent clk_rst agent Config :active po agent ppooaagg eennt t CConoafni cgfit:giv : e a catci vtiev e Config: [x3 ] DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 34
Connect DUT to Testbench • Always use SystemVerilog interface • Use clocking blocks for testbench per interface • Use modports for DUT Pass interface to the environment Use uvm_config_db Channel Engine Host Interface Read/Write Packet Input Packet Output 1 Packet Output 3 Packet Output 2 DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 35 Set (Top level initial block) uvm_config_db#(virtual host_if)::set( null, “my_tb.*”,“vif”, vif); Get (In build phase of the agent) if(! uvm_config_db#(virtual host_if)::get( this,,"vif",vif)) `uvm_fatal(“NOVIF”, . . . );
Connect Clock and Resets Combine clock and reset as agents in one env Define reset as sequences class clk_rst_env extends uvm_env; clk_rst_cfg cfg; //! VIP configuration object //! bring ports out for convenience uvm_analysis_port #(uvm_transaction) rst_mon_ap_out; //! Agents in env clk_agent clk_agt; rst_agent rst_agt; . . . task clk_rst_reset_pulse_sequence::body(); `uvm_do_with(change_sequence, { level == 0; hold_cycles == init_cycles; `uvm_do_with(change_sequence, { level == 1; hold_cycles == assert_cycles; `uvm_do_with(change_sequence, { level == 0; hold_cycles == negate_cycles; DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 36
Initializing the DUT Add transaction definitions for configuration interface (host) Add driver code for host Setup host initialization seq class host_transaction extends uvm_sequence_item; ... rand bit[31:0] hi_addr; rand bit[7:0] hi_wr_data; . . . task pwr_hi_master_driver::drive_transaction(host_transaction trans); if (trans.trans_kind == PWR_HI_WR) begin intf.hif_address = trans.hi_addr; intf.hif_data = trans.hi_wr_data; . . . task my_env_init_sequence::body(); regmodel.R1.write(...); regmodel.R2.read(...); . . . DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 37
Sending traffic DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 38 Similar to initialization Sequences differ //! sequence body. task pi_sequence::body(); pi_transaction#(. . .) req_xn; cfg_inst = p_sequencer.cfg; forever begin p_sequencer.peek_port.peek(req_xn); if (!this.randomize()) begin `uvm_fatal({get_name(), "RNDFLT"}, "Can't randomize"); end `uvm_do_with(this_transaction, { trans_kind == req_xn.trans_kind; read_vld_delay inside { [0:15] }; . . . }); . . .
Checking and Writing Tests Add checking in the environment Add monitor code for all components Connect the scoreboards class my_env extends uvm_env; unit_scoreboard#(uvm_transaction, uvm_transaction) sb; function void my_env::build_phase(uvm_phase phase); ... sb = unit_scoreboard#(uvm_transaction, uvm_transaction) ::type_id::create({get_name(), "_sb"}, this); function void pwc_env::connect_phase(uvm_phase phase); . . . pi_mon.mon_ap_out.connect(sb.post_export); po_mon.mon_ap_out.connect(sb.check_export); Add test-specific checking in the test as needed DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 39
Connecting Unit to System Level DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 40
• Scoreboarding • Reuse SB encapsulated within sub-envs • Chain the scoreboards • Functional Coverage • Needed to filter coverage points • Reuse monitors • Avoid duplicated instances • Gate Simulations • Disable monitors • Disable internal scoreboards • Registers • Register abstraction reused, but different interfaces used • Configurations • Defined separate system configuration • Top level instantiated sub-env configurations • Sequences • Virtual sequencer only at the system level • Initialization sequences reused from unit-level • Traffic sequences created from scratch at the system level DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 41 Connecting Unit to System Level: Reuse
Connecting Unit to System Level: Prescription For each sub-env class Extend sub-env base class Make all internal components passive Added sub-env config object to your system config Turn off virtual sequencer at the unit level Declare at system-level: unit_env_cfg unit_env_cfg_inst; `uvm_field_object(unit_env_cfg_inst, UVM_REFERENCE) DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 42
VIP Stacking/Layering VIP Agent Bottom Config is_active=1 has_interface=1 Sequencer Monitor vi Driver vi Analysis VIP Agent Top Monitor Design Under Test Analysis Config is_active=1 has_interface=0 Convert Monitor Convert Sequencer Sequencer Converts upwards Converts Downwards DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 43
Summary DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 44 • Getting started with UVM was relatively easy Once initial plumbing in place Basic tasks remain simple Were able to use a “prescriptive” approach • Able to iteratively develop testbench Scales to any complexity Unit to system Stacking of VIPs • Deployed across projects and simulation vendors
Workshop Outline DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 45 10:00am – 10:05am Dennis Brophy Welcome 10:05am – 10:45am Sharon Rosenberg UVM Concepts and Architecture 10:45am – 11:25am Tom Fitzpatrick UVM Sequences and Phasing 11:25am – 11:40am Break 11:40am – 12:20pm Janick Bergeron UVM TLM2 and Register Package 12:20pm – 12:50pm Ambar Sarkar Putting Together UVM Testbenches 12:50pm – 1:00pm All Q & A
Questions? • Download UVM from www.accellera.org – Reference Guide – User Guide – Reference Implementation – Discussion Forum DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 46
Accellera at DAC DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 47 • Accellera Breakfast at DAC: UVM User Experiences – An Accellera event sponsored by Cadence, Mentor, and Synopsys – Tuesday, June 7th, 7:00am-8:30am, Room 25AB • Accellera IP-XACT Seminar – An introduction to IP-XACT, IEEE 1685, Ecosystem and Examples – Tuesday, June 7th, 2:00pm-4:00pm, Room 26AB • Birds-Of-A-Feather Meeting – Soft IP Tagging Standardization Kickoff – Tuesday, June 7, 7:00 PM-8:30 PM, Room 31AB
Lunch in Room 20D Show your Workshop Badge DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems for entry
Thank You DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 49

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Workshop Outline ppt on UVM using sv.pptx

  • 1.
    Workshop Outline DAC Workshopon Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 1 10:00am – 10:05am Dennis Brophy Welcome 10:05am – 10:45am Sharon Rosenberg UVM Concepts and Architecture 10:45am – 11:25am Tom Fitzpatrick UVM Sequences and Phasing 11:25am – 11:40am Break 11:40am – 12:20pm Janick Bergeron UVM TLM2 and Register Package 12:20pm – 12:50pm Ambar Sarkar Putting Together UVM Testbenches 12:50pm – 1:00pm All Q & A
  • 2.
    Accellera at DAC DACWorkshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 2 • Accellera Breakfast at DAC: UVM User Experiences – An Accellera event sponsored by Cadence, Mentor, and Synopsys – Tuesday, June 7th, 7:00am-8:30am, Room 25AB • Accellera IP-XACT Seminar – An introduction to IP-XACT, IEEE 1685, Ecosystem and Examples – Tuesday, June 7th, 2:00pm-4:00pm, Room 26AB • Birds-Of-A-Feather Meeting – Soft IP Tagging Standardization Kickoff – Tuesday, June 7, 7:00 PM-8:30 PM, Room 31AB
  • 3.
    Workshop Outline DAC Workshopon Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 3 10:00am – 10:05am Dennis Brophy Welcome 10:05am – 10:45am Sharon Rosenberg UVM Concepts and Architecture 10:45am – 11:25am Tom Fitzpatrick UVM Sequences and Phasing 11:25am – 11:40am Break 11:40am – 12:20pm Janick Bergeron UVM TLM2 and Register Package 12:20pm – 12:50pm Ambar Sarkar Putting Together UVM Testbenches 12:50pm – 1:00pm All Q & A
  • 4.
    UVM Transaction LevelModeling (TLM2) • Janick Bergeron Synopsys
  • 5.
    TLM-1.0 • Unidirectional put/getinterfaces •Initiator •Target •Initiator •Target •put •get • Simple message-passing semantics • No response model – E.g. What did I read back?? • Never really caught on in SystemC DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 5
  • 6.
    Why TLM-2.0? DAC Workshopon Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 6 • Better interoperability over TLM- 1.0 – Semantics – Pre-defined transaction for buses • Performance – Pass by reference (in SystemC) – Temporal decoupling
  • 7.
    TLM-2.0 in SVvs SC • Blocking transport interface • Nonblocking transport interfaces • Direct memory interface • Debug transport interface • Initiator sockets • Target sockets • Generic payload • Phases • Convenience sockets • Payload event queue • Quantum keeper • Instance-specific extensions • Non-ignorable and mandatory extensions • Temporal decoupling DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 7
  • 8.
    TLM-2.0 Semantics • Blockin g –When the call returns, the transaction is done – Response is annotated • Nonblocking – Call back and forth • Protocol state changes • Transaction is updated •Initiat or •Targe t •Initiat or •Targe t DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 8
  • 9.
    Generic Payload Attributes DACWorkshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 9 Attribute Type Modifiable? Command uvm_tlm_command_e No Address bit [63:0] Interconnect only Data byte unsigned [ ] Yes (read command) Data length int unsigned No Byte enable pointer byte unsigned [ ] No Byte enable length int unsigned No Streaming width int unsigned No Response status uvm_tlm_response_status_e Target only Extensions uvm_tlm_extension_base [ ] Yes • Pre-defined bus transaction
  • 10.
    Connecting to SystemC •Tool-specific mechanism – Not part of UVM • SystemVerilog • SystemC •Copy across at method call and return DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 10
  • 11.
    TLM-2.0 Bridge BetweenSV & SC • Proxy sockets terminate the TLM2 connections in each language – Create SV/SC bridge •Initiat or •Targe t •Pack/unpack •Proxy Trgt •Proxy Init •TLM2 Bridge •Predefine d for GP in VCS • User-defined for GP extensions or non-GP • Unaware of language crossing • Unaware of language crossing DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 11
  • 12.
    UVM Register Model •Janick Bergeron Synopsys
  • 13.
  • 14.
    Specification & Generation RegisterModel IP-XACT Generator System RDL SQL CSV MS- Word ... UVM UVM X EDA Vendors Generator Generator Generator DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 14
  • 15.
    Physical Interfaces • Registermodel abstracts – Physical interfaces – Addresses – Endiannes s Register Model User perspectiv e R1.read(...); ... R2.write(...); ... R3.read(...); R1 R2 R3 DUT may change DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 15 Perspective stays the same
  • 16.
    Mirror • Register modelmirrors content of registers in DUT – “Scoreboard” for registers – Updated on read and write() – Optionally checked on read() Register Model R1 R2 R3 R1 R3 R2 API DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 16
  • 17.
    Back-door Access • Mustdefine HDL path to register in DUT – Generator-specific • Access RTL directly in zero-time via VPI – May affect simulator performance R1 R2 R3 R1 R3 R2 API Mirror is DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 17 implicitly updated
  • 18.
    Programmer’s View R0 R1 R2 R0 F1 F2F3 F4... ...F4 F5 F6 F5 F6 F5 F6 F7 F8 F9 F10 F7 F8 F9 F10 F7 F8 F9 F10 M0 erifying Blocks to IP to SOCs and Systems A[0] A[1] A[255] RF0[0] RF1[0] RF0[0] RF1[0] RF0[7] RF1[7] M0[0..65535] Array of Registers Array of Register Files Memory Multi-address Register DAC Workshop on Universal Verification Methodology (UVM) - V 18
  • 19.
    Class View • Oneclass per field • One class per register – Name – Addres s – Contained fields – Read/Write methods F1 F2 F3 R0 R0 R1 R2 F5 F6 F5 F6 F5 F6 A[0] A[1] A[255] F7 F8 F9 F10 RF0[0] RF1[0] RF0[0] RF1[0] F9 F10 F7 F8 F9 F10 RF0[7] RF1[7] M0[0..65535] F4... ...F4 M0 erifying Blocks to IP to SOCs and Systems F7 F8 class R1_reg extends uvm_reg; uvm_reg_field F1; uvm_reg_field F2; uvm_reg_field F3; endclass Generated Make sure names are different from base class methods DAC Workshop on Universal Verification Methodology (UVM) - V 19
  • 20.
    Class View • Oneclass per block – Name, Base address – Contained registers, register files, memories • May be arrays • Optional: contained fields R1 R0 R2 A[0] A[1] A[255] RF0[0] RF1[0] RF0[0] RF1[0] RF0[7] RF1[7] class B_blk extends uvm_reg_block; R0_reg R0; R1_reg R1; R2_reg R2; A_reg A[256]; RF_rfile ovm_ral_mem RF[8]; M0; endclass Generate d Make sure names are different from base class methods R0 F1 F3F 2 F4... ...F4 F5 F6 F5 F6 F5 F6 F7 F8 F9 F10 F7 F8 F9 F10 F7 M0[0..65535] DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 20
  • 21.
    API View • Methodsin relevant class instance R0 R1 R2 R0 F1 F2 F3 F4... ...F4 F5 F6 F5 F6 F5 F6 F7 F8 F9 F10 F7 F8 F9 F10 F7 F8 F9 F10 M0 erifying Blocks to IP to SOCs and Systems A[0] A[1] A[255] RF0[0] RF1[0] RF0[0] RF1[0] RF0[7] RF1[7] blk.R0.get_full_name() blk.F4.read(...) blk.A[1].write(...) blk.A[255].F5.write(...) foreach (blk.RF[i]) begin blk.RF[i].R0.F7.read(..._); end blk.M0.read(...) M0[0..65535] DAC Workshop on Universal Verification Methodology (UVM) - V 21
  • 22.
    Reading and Writing DACWorkshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 22 • Specify target register by hierarchical reference in register model – Compile-time checking • Use read() and write() method on – Registe r – Field – Memor y blk.blk[2].regfile[4].reg.fld blk.blk[2].regfile[4].reg.fld.read(...); blk.mem.write(...); By-name API also available
  • 23.
    Register Sequences DAC Workshopon Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 23 • Sequences accessing registers should be virtual sequences – Not associated with a particular sequencer type • Contain a reference to register model • Access registers in body() task class my_test_seq extends uvm_sequence; my_dut_model regmodel; virtual task body(); regmodel.R1.write(...); regmodel.R2.read(...); ... endtask endclass
  • 24.
    Register Sequences DAC Workshopon Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 24 • Includes pre-defined sequences – Check reset values – Toggle & check every bit – Front-door/back-door accesses – Memory walking
  • 25.
    Introspection • Rich introspection API Block Register Field RegisterFile Map get_regfile() get_maps() is_in_map() get_offset() get_block() get_blocks() get_parent() get_parent() get_fields() get_maps() get_registers() get_access() get_reset() get_n_bits() get_lsp_pos() is_volatile() DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 25
  • 26.
    Coverage Models • Registermodels may contain coverage models – Up to the generator • Not instantiated by default – Can be large. Instantiate only when needed. – To enable: • Not collected by default – To recursively enable uvm_reg::include_coverage(“*”, UVM_CVR_ALL); All coverage models In all blocks and registers blk.set_coverage(UVM_CVR_ALL); All coverage models in block DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 26
  • 27.
    Customization Opportunities Register Model Spec GeneratorPre-Build Post-Build Best Options, value- add DON’T! Factory Callbacks DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 27
  • 28.
    There’s a LOTmore! DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 28 • DUT integration • Multiple interfaces • Randomization • Vertical Reuse • “Offline” access • User-defined front-door accesses • Access serialization • Pipelined accesses
  • 29.
    Workshop Outline DAC Workshopon Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 29 10:00am – 10:05am Dennis Brophy Welcome 10:05am – 10:45am Sharon Rosenberg UVM Concepts and Architecture 10:45am – 11:25am Tom Fitzpatrick UVM Sequences and Phasing 11:25am – 11:40am Break 11:40am – 12:20pm Janick Bergeron UVM TLM2 and Register Package 12:20pm – 12:50pm Ambar Sarkar Putting Together UVM Testbenches 12:50pm – 1:00pm All Q & A
  • 30.
    Putting Together UVMTestbenches •Ambar Sarkar Paradigm Works, Inc.
  • 31.
    Agenda DAC Workshop onUniversal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 31 • Case studies – Several UVM1.0 environments deployed – Currently in production – Novice to sophisticated teams • Getting started with UVM is relatively easy – Basic tasks remain simple – Were able to use a “prescriptive” approach – Iteratively developed and scales to any complexity • Advanced uses – Unit to system-level – VIP Stacking/Layering
  • 32.
    Implementing Basic Steps ConnectDUT to testbench Send clocks and resets Initialize the DUT Send traffic Add checking Write tests Once plumbing in place, a simple prescriptive approach works DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 32 Increasing sophisticatio n, but scalable
  • 33.
    Example Host Interface Read/Write Packet Input Packet Output 1 Channel Engine PacketOutput 3 Packet Output 2 DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 33
  • 34.
    Example Environment inUVM DUT test cases ... unit_tb interrupt scoreboar d packet scoreboard host agent Config: active Config: active pi agent clk_rst agent Config :active po agent ppooaagg eennt t CConoafni cgfit:giv : e a catci vtiev e Config: [x3 ] DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 34
  • 35.
    Connect DUT toTestbench • Always use SystemVerilog interface • Use clocking blocks for testbench per interface • Use modports for DUT Pass interface to the environment Use uvm_config_db Channel Engine Host Interface Read/Write Packet Input Packet Output 1 Packet Output 3 Packet Output 2 DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 35 Set (Top level initial block) uvm_config_db#(virtual host_if)::set( null, “my_tb.*”,“vif”, vif); Get (In build phase of the agent) if(! uvm_config_db#(virtual host_if)::get( this,,"vif",vif)) `uvm_fatal(“NOVIF”, . . . );
  • 36.
    Connect Clock andResets Combine clock and reset as agents in one env Define reset as sequences class clk_rst_env extends uvm_env; clk_rst_cfg cfg; //! VIP configuration object //! bring ports out for convenience uvm_analysis_port #(uvm_transaction) rst_mon_ap_out; //! Agents in env clk_agent clk_agt; rst_agent rst_agt; . . . task clk_rst_reset_pulse_sequence::body(); `uvm_do_with(change_sequence, { level == 0; hold_cycles == init_cycles; `uvm_do_with(change_sequence, { level == 1; hold_cycles == assert_cycles; `uvm_do_with(change_sequence, { level == 0; hold_cycles == negate_cycles; DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 36
  • 37.
    Initializing the DUT Addtransaction definitions for configuration interface (host) Add driver code for host Setup host initialization seq class host_transaction extends uvm_sequence_item; ... rand bit[31:0] hi_addr; rand bit[7:0] hi_wr_data; . . . task pwr_hi_master_driver::drive_transaction(host_transaction trans); if (trans.trans_kind == PWR_HI_WR) begin intf.hif_address = trans.hi_addr; intf.hif_data = trans.hi_wr_data; . . . task my_env_init_sequence::body(); regmodel.R1.write(...); regmodel.R2.read(...); . . . DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 37
  • 38.
    Sending traffic DAC Workshopon Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 38 Similar to initialization Sequences differ //! sequence body. task pi_sequence::body(); pi_transaction#(. . .) req_xn; cfg_inst = p_sequencer.cfg; forever begin p_sequencer.peek_port.peek(req_xn); if (!this.randomize()) begin `uvm_fatal({get_name(), "RNDFLT"}, "Can't randomize"); end `uvm_do_with(this_transaction, { trans_kind == req_xn.trans_kind; read_vld_delay inside { [0:15] }; . . . }); . . .
  • 39.
    Checking and WritingTests Add checking in the environment Add monitor code for all components Connect the scoreboards class my_env extends uvm_env; unit_scoreboard#(uvm_transaction, uvm_transaction) sb; function void my_env::build_phase(uvm_phase phase); ... sb = unit_scoreboard#(uvm_transaction, uvm_transaction) ::type_id::create({get_name(), "_sb"}, this); function void pwc_env::connect_phase(uvm_phase phase); . . . pi_mon.mon_ap_out.connect(sb.post_export); po_mon.mon_ap_out.connect(sb.check_export); Add test-specific checking in the test as needed DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 39
  • 40.
    Connecting Unit toSystem Level DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 40
  • 41.
    • Scoreboarding • ReuseSB encapsulated within sub-envs • Chain the scoreboards • Functional Coverage • Needed to filter coverage points • Reuse monitors • Avoid duplicated instances • Gate Simulations • Disable monitors • Disable internal scoreboards • Registers • Register abstraction reused, but different interfaces used • Configurations • Defined separate system configuration • Top level instantiated sub-env configurations • Sequences • Virtual sequencer only at the system level • Initialization sequences reused from unit-level • Traffic sequences created from scratch at the system level DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 41 Connecting Unit to System Level: Reuse
  • 42.
    Connecting Unit toSystem Level: Prescription For each sub-env class Extend sub-env base class Make all internal components passive Added sub-env config object to your system config Turn off virtual sequencer at the unit level Declare at system-level: unit_env_cfg unit_env_cfg_inst; `uvm_field_object(unit_env_cfg_inst, UVM_REFERENCE) DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 42
  • 43.
    VIP Stacking/Layering VIP AgentBottom Config is_active=1 has_interface=1 Sequencer Monitor vi Driver vi Analysis VIP Agent Top Monitor Design Under Test Analysis Config is_active=1 has_interface=0 Convert Monitor Convert Sequencer Sequencer Converts upwards Converts Downwards DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 43
  • 44.
    Summary DAC Workshop onUniversal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 44 • Getting started with UVM was relatively easy Once initial plumbing in place Basic tasks remain simple Were able to use a “prescriptive” approach • Able to iteratively develop testbench Scales to any complexity Unit to system Stacking of VIPs • Deployed across projects and simulation vendors
  • 45.
    Workshop Outline DAC Workshopon Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 45 10:00am – 10:05am Dennis Brophy Welcome 10:05am – 10:45am Sharon Rosenberg UVM Concepts and Architecture 10:45am – 11:25am Tom Fitzpatrick UVM Sequences and Phasing 11:25am – 11:40am Break 11:40am – 12:20pm Janick Bergeron UVM TLM2 and Register Package 12:20pm – 12:50pm Ambar Sarkar Putting Together UVM Testbenches 12:50pm – 1:00pm All Q & A
  • 46.
    Questions? • Download UVMfrom www.accellera.org – Reference Guide – User Guide – Reference Implementation – Discussion Forum DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 46
  • 47.
    Accellera at DAC DACWorkshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 47 • Accellera Breakfast at DAC: UVM User Experiences – An Accellera event sponsored by Cadence, Mentor, and Synopsys – Tuesday, June 7th, 7:00am-8:30am, Room 25AB • Accellera IP-XACT Seminar – An introduction to IP-XACT, IEEE 1685, Ecosystem and Examples – Tuesday, June 7th, 2:00pm-4:00pm, Room 26AB • Birds-Of-A-Feather Meeting – Soft IP Tagging Standardization Kickoff – Tuesday, June 7, 7:00 PM-8:30 PM, Room 31AB
  • 48.
    Lunch in Room20D Show your Workshop Badge DAC Workshop on Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems for entry
  • 49.
    Thank You DAC Workshopon Universal Verification Methodology (UVM) - Verifying Blocks to IP to SOCs and Systems 49