Ankur Sharma is seeking a position that allows him to utilize his skills and gain professional growth. He has a M.Tech in VLSI Design from Nirma University and a B.E. in Electronics and Communication from Devi Ahilya Vishwavidyalaya. He has over 2 years of experience in VLSI design and verification with Intel and over 1 year of experience as an Associate Software Engineer with Accenture. He has expertise in Perl scripting, Verilog, SystemVerilog, C/C++, Java and tools like JasperGold. He is competent at problem solving and teamwork. He has undertaken various projects and internships and received several awards and appreciations.

1. Ankur Sharma
Phone: 09844365121
Email: ankur110889@gmail.com
Career Objective
To work with a leading organization that offers a motivating work culture where I can utilize best of my
potential, with strength to perform as team player and learn the new concepts along with gaining
professional growth.
Educational Qualification
Percentage /
CPI
Year of
Passing
Board/UniversityName of School/UniversityDegree
8.5June -2015Nirma UniversityNirma Institute of Technology,
Ahmedabad(G.J(
M.Tech. (VLSI Design(
7.29May-2011Devi Ahilya
Vishwavidyalaya
Institute of Engineering &
Technology Indore (M.P(
B.E.- Electronics &
Communication
72.6March-2006State BoardLokmanya Tilak SchoolHSC (12th- Science(
82.6March-2004State BoardLokmanya Tilak SchoolSSC (10th
- General(
Industrial Experience & Job Responsibilities
• Intern at In Intel Technology India Pvt. Ltd., Bangalore (Jun, 2014 – Till date).
Designation: Graduate Technical Intern.
• Worked on converge front end flows, methodology, Electronic Design Automation (EDA) tools
flow support, design flow automation, enhancements, verification and QA for different
projects.
• Had got exposure to different Intel specific flows used in complex projects for design
simulation and verification.
• Formal property verification and new methodologies used in RTL design and validation.
• Automated formal property verification tool flow, integrated it with FE flow. Automation
involved all steps like environment setting, design data gathering, compile and elaboration
options preparations, .f file and Tcl script generation for tool invocation, test execution and
final report generation.
• Time savings utility for RTL design verification and report generation.
• Tools flow enhancements, debugging and new feature development to facilitate front end
process and providing support to SoC teams.
• Working closely with chip designers to understand their technical challenges, and to create
proprietary Computer Aided Design (CAD) solutions.
• Expertise in Advance Perl Scripting and System Verilog Assertions.
• Interacting with tool vendors and contributing to engineering documentations.
• Associate Software Engineer at Accenture Services Pvt. Ltd., Mumbai (Jun, 2011 – Jul 2012).
Designation: Associate Software Engineer.
• Worked as Oracle lodestar resource, responsible to work on Meta Data and Standing Data and
data models for quote management and meter data management.
• Major projects executed in Utility (Energy and Resource) domain.
• Major clients include Green Mountain Energy Company (US), Energy de France (UK).
• Experienced in interacting with clients to understand the actual requirement and analyze the
business process and transforming requirements into documenting and rolling out the
deliverable.
• Involved in UTP’s, installation of Oracle Lodestar and creating Technical Design document and
Functional Design document
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2. Technical Summary
Scripting language Perl, Perl OOP and hands on experience in shell scripting
HDL Verilog and Basics of System Verilog
Programming language C,C++, Core JAVA, SQL
Tools
Formal Property Verification- Jaspergold apps (Cadence)
RTL Simulation- Xilinx ,VCS (Synopsys)
Synthesis- Xilinx ISE
Understanding of Front End Flows, methodology and tools flow enhancement and new features
developments.
Comprehensive experience on automating flows, quality analysis and verification.
Good understanding of Digital circuits, ASIC flow, tool flow concept System Verilog Assertion and Formal
Property Verification.
Good understanding of LINUX/UNIX environments.
Key Strengths
• Competent in analysing problem and able to come up with solutions fast.
• Skilful in constructing the required programs for products.
• A highly motivated team player with good inter-personal skills.
Industry Trainings Undertaken and Certifications
• One year VLSI technical internship at Intel (Front End support team).
• Oracle Lodestar, Mainframe Cobol, DB2, CICS Training at Accenture.
• Completed 45 days major training at Nokia Siemens Networks.
• Completed utility L1 and L2 certification at Accenture.
• Completed Empower certification of Ericsson.
Projects Undertaken and Seminars Presented:
Advance automated mechanism for design compilation and verification flows for complex
Soc design.
• Worked on various VLSI flow required for design compilation and validation of SoC design.
• Formal property verification and advance Perl scripting are major areas.
• Worked for integration of new flows.
• Designed various utilities to facilitate the task.
Design and Implementation of shift register with serial and parallel in/out capability
• Behavioural level to RTL level design was prepared using Xilinx ISE in VHDL.
• Implemented on Spartan 3 FPGA kit.
Using PERL: Implementation of Fault modelling algorithm for verification of VLSI Chip.
• Working on implementation of fault equivalence and dominance algorithms to get the reduced
• Single stuck at faults set from the given ISCAS netlist format.
Seminar: Limitation of Shrink technology
• Main purpose is to understand the technology limitation and its effect on performance of
devices.
Function design by transmission gate
• Implementation of 5 variable Boolean function using transmission gate technologies.
• Layout design in Microwind.
Mismatch detector tool
• Developed a tool which can generate reverse metadata and detect mismatch in different
working environment.
• Received celebrating performance points for the same.
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3. ALU Design using VHDL
• Behavioural level to RTL level design was prepared using Xilinx ISE in VHDL.
• Implemented on Spartan 3 FPGA kit.
Term Paper on QMF Filter
• Presented paper on two channel QMF filter bank and implemented the logic using MATLAB.
Real Time Surveillance System
• Designed and constructed an automated vehicle capable of moving on the path which is
managed through the remote computer. The navigation of vehicle is done through a RFID
module working in ISM band.
Minor Project 1
• Designed a project on Speed Control of D.C. Motor using Pulse Width Modulation through
C programming language.
Minor Project 2
• Autonomous Guided Vehicle Using Microcontroller programming.
Under Water Robot
• Designed a robot capable of performing task underwater.
• Received appreciation for the same from IIT Kharagpur.
Designed several application specific robots.
Achievements:
• Received celebrating performance points several times from last organization.
• Received letter of appreciations from university.
• Winner of national level robotics competition at Techniche, the techno-management fest of IIT
Guwahati.
• Winner of national level robotics competition at Kshitij, the techno-management fest of IIT
Kharagpur.
• Received best mechanical design award at Kshitij, the techno-management fest of IIT
Kharagpur.
• Volunteered in many social service and environmental service tasks.
Personal Details
Name Ankur Sharma
Gender Male
Birth Date 11-Aug-1989
Language proficiency English, Hindi
Permanent Address 8 Indore Gate Ujjain Madhya Pradesh
Nationality Indian
Email ankur.sharma112@gmail.com
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