Prajwal provides a concise summary of his background and qualifications. He aims to use his skills and knowledge to deliver value and job satisfaction while achieving personal and organizational goals. He has a bachelor's degree in technology and specialized training in VLSI design and verification. His experience includes internships in mechatronics, satellite technology, and FPGA development. He has strong skills in Verilog, SystemVerilog, simulation tools, and microcontrollers. Prajwal has received awards for his innovative student projects and publications. He seeks to contribute as a team player with communication skills and leadership abilities.

1. About Me
To work in the organization where I can use my skills and knowledge to
deliver value added results that provides me job satisfaction and self-
development which help to achieve personal as well as organization goals
Professional Training
Advanced VLSI Design and Verification Course.
Maven Silicon VLSI Design and Training Center, Bangalore
October 2019 till date
Education
Bachelor, Technology
Sri Venkateshwara College Of Engineering Graduated, July 2019
Visvesvaraya Technological University
Bangalore, Karnataka
10+2(PCMB)
Narayana PU College Graduated, March 2015
Karnataka PU Board
Bangalore, Karnataka
10
U A S Campus School Graduated, April 2013
Karnataka State Board
Bangalore,Karnataka
Industrial Exposure
 HMT machine tools limited
July 2018 - August 2018
As an Intern
Bangalore Complex, Jalahalli, HMT P.O, Bangalore 560 013
Engaged in all phases of the Mechatronics which include
electronics, control system, CNC design and coding, responding
to outages and creating application system models. Worked in
electronic assembly session, test and debug session to meet
business needs.
 INMCC/ISTRAC/ISRO
January 2019 – June 2019
As a Project Intern
Peenya Industrial Estate Bangalore-58
Engaged in all phases of satellite rescue technology and
satellite constellation and I work on real-time project on MEO-
SAR constellation in INMCC department of ISTRAC/ISRO
 Questa-Sim – Mentor Graphics
 ISE – Xilinx
Other Skills
Prajwalreddy1997@gmail.com
+91 8867258699
R T Nagar Bangalore,
Karnataka
https://www.linkedin.com/in/pra
jwal-reddy-110485150
VLSI Domain Skills
HDL
 Verilog
 System Verilog
EDA Tools
 Questa-Sim – Mentor Graphics
 ISE – Xilinx
Knowledge
 RTL Design & Coding
 UVM
 FSM based design
 Simulation
 Code Coverage
 Functional Coverage
 Static Timing Analysis
 Assertions
 FPGA
 CMOS fundamentals
 UART
Other Skills
 Basics of C & C++
 Matlab-Simulink
 Python
 Pic Microcontroller
 Arduino IDE
Prajwal A N

2. Career Highlights
 I was awarded “Student Innovator of the Year 2018” by the ICT
academy.
 Participate in ANVESHANA 2018 and 2019 science and engineering
fair which was jointly organized by Agastya international foundation
and Synopsys for the project on “biomedical device” and “Reality in
Education” respectively.
 Secured 2nd
runner up in “SS12-2018 AGE OF INNOVATION”
which was jointly organized by Q-Rides, SVCE, and IEEE Sri Lanka
society for the project entitled “smart navigation cane”.
 Secured 1st Place in YESIST12 -2019 under the theme Innovation
project which was organized by the IEEE society for the project
entitled “Integrated ISCHAF-C Robot”.
 Participated in the hardware edition of the "Smart India
Hackathon" 2018 and gave a solution for smart irrigation.
 My final year project Integrate SCHAF-C UAV has won 2nd place in
state-level project exhibition organized by Karnataka science and
technology academy (KSTA) Department of science and technology,
the government of Karnataka and we received project funds from
Karnataka state council for science and technology (KSCST).
Projects Undertaken
VLSI Project
 Router 1x3 – RTL design and Verification
HDL: Verilog
TB Methodology: Verilog
EDA Tools: Questasim and ISE
Description: The router accepts data packets on a single 8-bit port and
routes them to one of the three
Output channels, channel0, channel1 and channel2.
Responsibilities:
 Architected the block level structure for the design
 Implemented RTL using Verilog HDL.
 Architected the verification environment using Verilog.
 Verified the RTL model using Verilog. Code coverage for
the RTL.
 Synthesized the design.
Other Projects
 Design And Implementation Of Automatically Trigged IOT
Based Wearable Safety Device For Girl And Women
 Visibility Analysis And Scheduling Of GPS/SAR Satellites With
Multi-Antenna System
(INMCC, ISRO)
 Integrated Secure Columnist Hexapod All-Terrain Full Time
Counter-Foe Master (I-SCHAF-C)
 Smart Navigation Cane For Visually Impaired People
 Smart Irrigation
 Reality In Education
Soft Skills
Communication Skill
Team player
Public Speaking
Leadership
Puzzles /
Brain Games
Volunteer Work
Reading
Gardening
Hindi
Telugu
Kannada
English
Prajwal A N
Soft Skills
Communication Skill
Team player
Leadership
Public Speaking
Personal Interest
Reading
Volunteer Work
Puzzles /
Brain Games
Gardening
Languages
English
Hindi
Kannada
Telugu

3. Publication
 Published a paper entitled “Integrated Secular Columnist
Hexapod All Terrain Full Time Counter -For Master” in 2019 4th
IEEE International Conference on recent trends on electronics,
information, communication & technology (RTEICT-2019)
Declaration
I, Prajwal A N, hereby declare that the information contained herein is true
and correct to the best of my knowledge and belief
Prajwal A N
Prajwal A N