This document discusses using advanced standardized test languages like TTCN-3, UML testing profile, and TDL to test system architectures. It provides an overview of TTCN-3, including its design principles, domains of use in telecom and other industries, and examples of test system architectures using TTCN-3. Key benefits of TTCN-3 include its ability to test distributed systems, support various test types, and enable graphical test development, documentation and analysis.
Test System Architectures using Advanced Standardized Test LanguagesAxel Rennoch
The document discusses standardized test languages for defining test system architectures. It introduces TTCN-3, the UML Testing Profile (UTP), and the Test Description Language (TDL). TTCN-3 is highlighted as the most mature language, with examples showing how it can be used to define test components, ports, behavior, and system configurations for various domains including telecom, automotive, and medical. Lessons learned are provided on using libraries, synchronization, and modeling tools with TTCN-3. UTP and TDL are newer standards that aim to provide higher-level modeling capabilities but have seen less adoption than TTCN-3.
Advanced Testing with TTCN-3 and UML Testing ProfileAxel Rennoch
The document discusses advanced test modeling and execution using the standardized techniques TTCN-3 and UTP. It provides an overview of TTCN-3 concepts, tools, and applications in industrial domains and model-based testing. It also discusses the UML Testing Profile and how it can be used for test modeling. TTCN-3 is highlighted as an internationally standardized language for formally defining test scenarios and has been widely adopted in industries such as telecommunications, automotive, and others. UTP is a standard profile for modeling tests using UML and can generate TTCN-3 code for test execution.
The document discusses the testing and test control notation TTCN-3. It provides an introduction and history of TTCN-3, describes its current status and concepts/tools, and outlines its future including latest releases and extensions. TTCN-3 is a standardized language for testing telecommunications protocols and distributed systems, with a focus on black box testing through message or procedure-based communication ports.
TTCN-3 is an internationally standardized testing language used for black-box testing of systems. It allows for the automation of functional testing and is designed for testing concurrent behaviors. TTCN-3 tests can be executed on multiple platforms as it is platform independent. The language is maintained and developed by ETSI to support various applications like telecommunications, automotive, and more.
1. TTCN was originally developed to test telecommunication systems but has expanded to other industries like automotive. It aims to make testing more efficient, automated, and reproducible.
2. TTCN-3 introduced new capabilities like procedure-based communication and dynamic test configuration control to broaden the scope of testable applications. It also standardized target adaptation interfaces.
3. TTCN is used for black box testing where tests stimulate interfaces and check responses without knowledge of internal implementation. It uses abstract test cases, parallel test components, and standardized interfaces to connect executable test suites to the system under test.
The document discusses kernel logging from the printk function in the kernel to log files in user space. It explores the printk API, how log messages move from the kernel ring buffer to user space via the syslog system call, and how rsyslog manages logs in user space.
An integrated approach for designing and testing specific processorsVLSICS Design
This paper proposes a validation method for the des
ign of a CPU on which, in parallel with the
development of the CPU, it is also manually describ
ed a testbench that performs automated testing on t
he
instructions that are being described. The testbenc
h consists of the original program memory of the CP
U
and it is also coupled to the internal registers, P
ORTS, stack and other components related to the pro
ject.
The program memory sends the instructions requested
by the processor and checks the results of its
instructions, progressing or not with the tests. Th
e proposed method resulted in a CPU compatible with
the
instruction set and the CPU registers present into
the PIC16F628 microcontroller. In order to shows th
e
usability and success of the depuration method empl
oyed, this work shows that the CPU developed is
capable of running real programs generated by compi
lers existing on the market. The proposed CPU was
mapped in FPGA, and using Cadence tools, was synthe
sized on silicon.
This document provides an outline for a tutor session on UNIX shell script programming. It introduces shells and shell scripts, and covers topics like variables, data operations, decision statements like if-else and switch-case, and iteration statements like for loops and while loops. Examples are provided throughout to illustrate different shell script programming concepts and syntax. Links to additional online resources on shell scripting are also included at the end.
Test System Architectures using Advanced Standardized Test LanguagesAxel Rennoch
The document discusses standardized test languages for defining test system architectures. It introduces TTCN-3, the UML Testing Profile (UTP), and the Test Description Language (TDL). TTCN-3 is highlighted as the most mature language, with examples showing how it can be used to define test components, ports, behavior, and system configurations for various domains including telecom, automotive, and medical. Lessons learned are provided on using libraries, synchronization, and modeling tools with TTCN-3. UTP and TDL are newer standards that aim to provide higher-level modeling capabilities but have seen less adoption than TTCN-3.
Advanced Testing with TTCN-3 and UML Testing ProfileAxel Rennoch
The document discusses advanced test modeling and execution using the standardized techniques TTCN-3 and UTP. It provides an overview of TTCN-3 concepts, tools, and applications in industrial domains and model-based testing. It also discusses the UML Testing Profile and how it can be used for test modeling. TTCN-3 is highlighted as an internationally standardized language for formally defining test scenarios and has been widely adopted in industries such as telecommunications, automotive, and others. UTP is a standard profile for modeling tests using UML and can generate TTCN-3 code for test execution.
The document discusses the testing and test control notation TTCN-3. It provides an introduction and history of TTCN-3, describes its current status and concepts/tools, and outlines its future including latest releases and extensions. TTCN-3 is a standardized language for testing telecommunications protocols and distributed systems, with a focus on black box testing through message or procedure-based communication ports.
TTCN-3 is an internationally standardized testing language used for black-box testing of systems. It allows for the automation of functional testing and is designed for testing concurrent behaviors. TTCN-3 tests can be executed on multiple platforms as it is platform independent. The language is maintained and developed by ETSI to support various applications like telecommunications, automotive, and more.
1. TTCN was originally developed to test telecommunication systems but has expanded to other industries like automotive. It aims to make testing more efficient, automated, and reproducible.
2. TTCN-3 introduced new capabilities like procedure-based communication and dynamic test configuration control to broaden the scope of testable applications. It also standardized target adaptation interfaces.
3. TTCN is used for black box testing where tests stimulate interfaces and check responses without knowledge of internal implementation. It uses abstract test cases, parallel test components, and standardized interfaces to connect executable test suites to the system under test.
The document discusses kernel logging from the printk function in the kernel to log files in user space. It explores the printk API, how log messages move from the kernel ring buffer to user space via the syslog system call, and how rsyslog manages logs in user space.
An integrated approach for designing and testing specific processorsVLSICS Design
This paper proposes a validation method for the des
ign of a CPU on which, in parallel with the
development of the CPU, it is also manually describ
ed a testbench that performs automated testing on t
he
instructions that are being described. The testbenc
h consists of the original program memory of the CP
U
and it is also coupled to the internal registers, P
ORTS, stack and other components related to the pro
ject.
The program memory sends the instructions requested
by the processor and checks the results of its
instructions, progressing or not with the tests. Th
e proposed method resulted in a CPU compatible with
the
instruction set and the CPU registers present into
the PIC16F628 microcontroller. In order to shows th
e
usability and success of the depuration method empl
oyed, this work shows that the CPU developed is
capable of running real programs generated by compi
lers existing on the market. The proposed CPU was
mapped in FPGA, and using Cadence tools, was synthe
sized on silicon.
This document provides an outline for a tutor session on UNIX shell script programming. It introduces shells and shell scripts, and covers topics like variables, data operations, decision statements like if-else and switch-case, and iteration statements like for loops and while loops. Examples are provided throughout to illustrate different shell script programming concepts and syntax. Links to additional online resources on shell scripting are also included at the end.
The document provides an introduction to assembly language programming including:
- The basic elements of assembly language such as instructions, directives, constants, identifiers, and comments.
- A flat memory program template that includes TITLE, MODEL, STACK, DATA, CODE, and other directives.
- An example program that adds and subtracts integers and calls a procedure to display registers.
- An overview of the assemble-link-debug cycle used to develop assembly language programs.
This document provides an introduction to assembly language programming. It discusses how assembly language works at a low level directly with a computer's processor. It outlines the basic components of an assembly language program like editors, assemblers, linkers and debuggers. It also describes the instruction sets, addressing modes, and common directives supported by the 8086 microprocessor. Finally, it provides an example of a simple assembly language program to perform an 8-bit number subtraction.
This document provides an introduction to C programming for embedded systems using microcontrollers. It reviews basics of C programming syntax and shows examples of simple C programs for an 8051 microcontroller. Key topics covered include C program templates, directives like #include and #define, variables, functions, loops, conditional statements, and arrays. The goal is to provide sufficient knowledge to develop more complex C programs for small embedded systems using microcontrollers. Example programs are provided and discussed to illustrate various C programming concepts.
This document provides information about the fourth semester subject "Microprocessor and Programming" for the Computer Engineering group. It includes the teaching and examination scheme, rationale, objectives, learning structure, and contents of the course. The course aims to teach students about the architecture and instruction set of 8085 and 8086 microprocessors. It covers topics such as assembly language programming, procedures, macros, and interfacing with memory. The goal is to enable students to design 8086-based programs and systems. Assessment includes theory exams, practical exams, and sessional work based on bi-weekly tests.
The document discusses the process of compilation. It has 4 main steps - lexical analysis, syntactic analysis, intermediate code generation, and code generation.
In lexical analysis, the source code is scanned and broken into basic elements like identifiers, literals, and symbols. Tables are created to store this tokenized information.
Syntactic analysis recognizes syntactic constructs and interprets their meaning. It checks for syntactic errors. Intermediate code like a parse tree or matrix is generated to represent the program.
Storage is allocated to variables during intermediate code generation. Optimization techniques are also applied at this stage.
Finally, machine code is generated from the intermediate representation based on tables containing code templates. Assembly code is then produced to resolve references
* Memory types (RAM, ROM, EEPROM, etc).
* Program memory segments.
* Static vs. Dynamic memory allocation.
* Static vs. Dynamic linking.
* Function call with respect to stack, i/p, o/p and i/o parameters and return value.
* Functions types (Synch. vs. ASynch, Reentrant vs. non-Reentrant, Recursive, Inline function vs. function-like macro).
The document provides information about a C programming course, including:
1) An introduction to computer hardware and software concepts like computer generations, types, bits, bytes, CPU, memory, ports, input/output devices and networks.
2) An overview of the C programming language including the basic structure of a C program, executing a program, and data types like constants, variables, integers, floats etc.
3) Examples of C programs to calculate the area and perimeter of shapes like circles and rectangles, along with the basic components of a C program like preprocessor directives, main function, declaration and executable parts.
The GO4IT project aims to:
1) Raise awareness and prepare users for the transition to IPv6.
2) Expand the IPv6 user community.
The project provides a free IPv6 validation environment including test tools, test suites, and related services. BUPT's tasks include designing abstract test suites in TTCN-3 for conformance and interoperability testing of technologies like mobile IPv6. BUPT will also work on software components for test development and execution like the TTCN-3 compiler and test adapters.
The document provides a summary of Michael Joshua S's professional experience and skills. It summarizes over 12 years of experience in embedded systems testing and validation across various industries. Key roles included consulting test engineer, team lead, and project engineer. Technical skills include test automation using National Instruments hardware and software, system engineering, verification and validation, and embedded software development.
Functional and non-functional testing with IoT-TestwareAxel Rennoch
The Internet of Things (IoT) is omnipresent. More and more hardware devices get connected and will collect and share huge amounts of data in the near future. This progress will lead to a digital and hyper-connected world. Though, in such growing networks of interconnected things, quality assurance (QA) will become a continuous challenge. Especially aspects like conformance, interoperability and security but also performance and robustness will require an increased attention from QA perspective.
Vijayananda Mohire worked as an assistant engineer on a project from 1996-2000 in Bangalore, India to develop an Engineering Test Station (ETS) to test avionic units for aircraft. The ETS was used to simulate conditions and test devices like flight control computers and communication devices. As an assistant engineer, Mohire's role included analyzing devices, designing hardware and software interfaces, developing test cases, and validating units. He leveraged equipment like oscilloscopes and bus testers at the test station to interface devices and confirm their proper functioning. Mohire adapted strategies like observing colleagues, keeping an official diary, and collaborating with others on the team.
Srivaishnavi Sivagnanam is pursuing a Master of Science in Electrical Engineering expected in 2015 from International Technological University in California. She has a Master's in IT & Management from Illinois Institute of Technology and a Bachelor's in IT from Anna University in India. She has experience as an LTE Verification Engineer at T-Mobile and LTE Systems Test Engineer at Motorola/Nokia Siemens Network testing eNodeB and other wireless systems. Currently she is a Research Assistant developing an OpenCV/C program for stereo vision image processing at ITU.
The presentation provides an overview of behavioral synthesis and SystemC. It discusses what behavioral synthesis is, the synthesis process which includes data flow optimization, scheduling, clustering, allocation and binding, and control logic generation. It notes some limitations of behavioral synthesis. It then defines SystemC as a C++ library with HDL features that allows modeling concurrent processes using plain C++ syntax. It outlines some key features of SystemC like modules, ports, processes and channels.
Martin Gijsen - Effective Test Automation a la Carte TEST Huddle
EuroSTAR Software Testing Conference 2009 presentation on Effective Test Automation a la Carte by Martin Gijsen. See more at conferences.eurostarsoftwaretesting.com/past-presentations/
“eXtending” the Automation Toolbox: Introduction to TwinCAT 3 Software and eX...Design World
The document provides an overview of TwinCAT 3 software and eXtended Automation (XA) from Beckhoff Automation. It discusses (1) how TwinCAT 3 addresses customer wishes from TwinCAT 2 like integration, C/C++ support, and migration capabilities, (2) the key aspects of XA including engineering (XAE), architecture (XAA), and runtime (XAR) environments, and (3) new TwinCAT 3 capabilities such as support for multi-core systems, connectivity tools, and migration from TwinCAT 2 projects.
Accelerating system verilog uvm based vip to improve methodology for verifica...VLSICS Design
In this paper we present the development of Acceleratable UVCs from standard UVCs in System Verilog
and their usage in UVM based Verification Environment of Image Signal Processing designs to increase
run time performance. This paper covers development of Acceleratable UVCs from standard UVCs for
internal control and data buses of ST imaging group by partitioning of transaction-level components and
cycle-accurate signal-level components between the software simulator and hardware accelerator
respectively. Standard Co-Emulation API: Modeling Interface (SCE-MI) compliant, transaction-level
communications link between test benches running on a host system and Emulation machine is established.
Accelerated Verification IPs are used at UVM based Verification Environment of Image Signal Processing
designs both with simulator and emulator as UVM acceleration is an extension of the standard simulationonly
UVM and is fully backward compatible with it. Acceleratable UVCs significantly reduces development
schedule risks while leveraging transaction models used during simulation.
In this paper, we discuss our experiences on UVM based methodology adoption on TestBench-Xpress
(TBX) based technology step by step. We are also doing comparison between the run time performance
results from earlier simulator-only environment and the new, hardware-accelerated environment. Although
this paper focuses on Acceleratable UVC’s development and their usage for image signal processing
designs. Same concept can be extended for non-image signal processing designs.
This document proposes a presentation on using a common mediation port in TTCN-3 to execute scripts from test cases. A mediation port is defined that accepts messages containing a script name and parameters. A TRI connects this port to a mediation server hosting scripts in languages like Shell and Perl. Test cases can call scripts by sending messages to the port. This allows tasks like controlling non-SUT devices and databases through scripts without recompiling test suites. Benefits include reduced compilation times when changes are needed and the ability to develop new interfaces quickly by moving functionality to reusable scripts.
Summarizing Software API Usage Examples Using Clustering TechniquesNikos Katirtzis
This document presents CLAMS, an approach for automatically mining API usage examples from client code. It clusters API usage sequences, generates summarized snippets from the top clusters, and selects the most representative snippet from each cluster. The methodology can be easily adapted to new programming languages as it relies on abstract syntax trees and API call sequences rather than detailed semantic analysis. The system is evaluated on datasets from several Java libraries and is shown to produce more concise, readable snippets that better match handwritten examples compared to approaches that output API call sequences or less summarized snippets. The clustering approach that allows similar rather than just identical sequences leads to improved results.
DCCN 2016 - Tutorial 1 - Communication with LAN/WLANrudndccn
The document introduces a tutorial on simulating communication between devices within LAN and WLAN networks using the Network Simulator 3 (NS-3). It describes creating a virtual machine with NS-3 and Eclipse for developing network simulations and demonstrates simulating a simple network topology with point-to-point, CSMA/CD Ethernet, and CSMA/CA WiFi links between nodes, including capturing traffic between an echo client and server using pcap tracing.
09 basics operating and monitoring v1.00_enconfidencial
The document discusses the basics of operating and monitoring a PCS 7 system. It describes the general functions of the operator station (OS) and how it can be configured as a single station or multiple station system. It also covers plant hierarchy settings, the OS-AS connection, compiling projects, layouts, block icons and faceplates. The key points are:
- The OS is based on WinCC and used for process visualization, alarm logging, tag logging, and more.
- A system can be a single OS or multiple OSs connected to one or more automation stations. Redundant servers provide high availability.
- Plant hierarchy settings determine how data is structured in pictures and tag names on the
The document discusses openness in the AXE telecommunications system from Ericsson. It defines two types of openness: network openness, which refers to the ability to interconnect with other networks using standard protocols, and system openness, which involves using commercially available standard hardware and software components to build the AXE system. The document outlines how Ericsson has increased system openness over time by introducing more standard components like commercial processors, Windows NT, and off-the-shelf hardware, while focusing proprietary development on the interface between components. This allows Ericsson to benefit from advances in other industries while concentrating on its core switching capabilities.
This document proposes a presentation on integrating the TTCN-3 testing framework with the Robot test automation framework and Jenkins continuous integration tool to provide end-to-end test automation. The integration allows TTCN-3 test cases to trigger Robot tests for GUI or web validations, with Robot notifying TTCN-3 when validations are complete. Jenkins is used to schedule and monitor repeated executions of Robot test cases across multiple environments. The approach provides benefits like GUI validation during TTCN-3 tests, configuration changes on remote systems during testing, and end-to-end test automation.
The document provides an introduction to assembly language programming including:
- The basic elements of assembly language such as instructions, directives, constants, identifiers, and comments.
- A flat memory program template that includes TITLE, MODEL, STACK, DATA, CODE, and other directives.
- An example program that adds and subtracts integers and calls a procedure to display registers.
- An overview of the assemble-link-debug cycle used to develop assembly language programs.
This document provides an introduction to assembly language programming. It discusses how assembly language works at a low level directly with a computer's processor. It outlines the basic components of an assembly language program like editors, assemblers, linkers and debuggers. It also describes the instruction sets, addressing modes, and common directives supported by the 8086 microprocessor. Finally, it provides an example of a simple assembly language program to perform an 8-bit number subtraction.
This document provides an introduction to C programming for embedded systems using microcontrollers. It reviews basics of C programming syntax and shows examples of simple C programs for an 8051 microcontroller. Key topics covered include C program templates, directives like #include and #define, variables, functions, loops, conditional statements, and arrays. The goal is to provide sufficient knowledge to develop more complex C programs for small embedded systems using microcontrollers. Example programs are provided and discussed to illustrate various C programming concepts.
This document provides information about the fourth semester subject "Microprocessor and Programming" for the Computer Engineering group. It includes the teaching and examination scheme, rationale, objectives, learning structure, and contents of the course. The course aims to teach students about the architecture and instruction set of 8085 and 8086 microprocessors. It covers topics such as assembly language programming, procedures, macros, and interfacing with memory. The goal is to enable students to design 8086-based programs and systems. Assessment includes theory exams, practical exams, and sessional work based on bi-weekly tests.
The document discusses the process of compilation. It has 4 main steps - lexical analysis, syntactic analysis, intermediate code generation, and code generation.
In lexical analysis, the source code is scanned and broken into basic elements like identifiers, literals, and symbols. Tables are created to store this tokenized information.
Syntactic analysis recognizes syntactic constructs and interprets their meaning. It checks for syntactic errors. Intermediate code like a parse tree or matrix is generated to represent the program.
Storage is allocated to variables during intermediate code generation. Optimization techniques are also applied at this stage.
Finally, machine code is generated from the intermediate representation based on tables containing code templates. Assembly code is then produced to resolve references
* Memory types (RAM, ROM, EEPROM, etc).
* Program memory segments.
* Static vs. Dynamic memory allocation.
* Static vs. Dynamic linking.
* Function call with respect to stack, i/p, o/p and i/o parameters and return value.
* Functions types (Synch. vs. ASynch, Reentrant vs. non-Reentrant, Recursive, Inline function vs. function-like macro).
The document provides information about a C programming course, including:
1) An introduction to computer hardware and software concepts like computer generations, types, bits, bytes, CPU, memory, ports, input/output devices and networks.
2) An overview of the C programming language including the basic structure of a C program, executing a program, and data types like constants, variables, integers, floats etc.
3) Examples of C programs to calculate the area and perimeter of shapes like circles and rectangles, along with the basic components of a C program like preprocessor directives, main function, declaration and executable parts.
The GO4IT project aims to:
1) Raise awareness and prepare users for the transition to IPv6.
2) Expand the IPv6 user community.
The project provides a free IPv6 validation environment including test tools, test suites, and related services. BUPT's tasks include designing abstract test suites in TTCN-3 for conformance and interoperability testing of technologies like mobile IPv6. BUPT will also work on software components for test development and execution like the TTCN-3 compiler and test adapters.
The document provides a summary of Michael Joshua S's professional experience and skills. It summarizes over 12 years of experience in embedded systems testing and validation across various industries. Key roles included consulting test engineer, team lead, and project engineer. Technical skills include test automation using National Instruments hardware and software, system engineering, verification and validation, and embedded software development.
Functional and non-functional testing with IoT-TestwareAxel Rennoch
The Internet of Things (IoT) is omnipresent. More and more hardware devices get connected and will collect and share huge amounts of data in the near future. This progress will lead to a digital and hyper-connected world. Though, in such growing networks of interconnected things, quality assurance (QA) will become a continuous challenge. Especially aspects like conformance, interoperability and security but also performance and robustness will require an increased attention from QA perspective.
Vijayananda Mohire worked as an assistant engineer on a project from 1996-2000 in Bangalore, India to develop an Engineering Test Station (ETS) to test avionic units for aircraft. The ETS was used to simulate conditions and test devices like flight control computers and communication devices. As an assistant engineer, Mohire's role included analyzing devices, designing hardware and software interfaces, developing test cases, and validating units. He leveraged equipment like oscilloscopes and bus testers at the test station to interface devices and confirm their proper functioning. Mohire adapted strategies like observing colleagues, keeping an official diary, and collaborating with others on the team.
Srivaishnavi Sivagnanam is pursuing a Master of Science in Electrical Engineering expected in 2015 from International Technological University in California. She has a Master's in IT & Management from Illinois Institute of Technology and a Bachelor's in IT from Anna University in India. She has experience as an LTE Verification Engineer at T-Mobile and LTE Systems Test Engineer at Motorola/Nokia Siemens Network testing eNodeB and other wireless systems. Currently she is a Research Assistant developing an OpenCV/C program for stereo vision image processing at ITU.
The presentation provides an overview of behavioral synthesis and SystemC. It discusses what behavioral synthesis is, the synthesis process which includes data flow optimization, scheduling, clustering, allocation and binding, and control logic generation. It notes some limitations of behavioral synthesis. It then defines SystemC as a C++ library with HDL features that allows modeling concurrent processes using plain C++ syntax. It outlines some key features of SystemC like modules, ports, processes and channels.
Martin Gijsen - Effective Test Automation a la Carte TEST Huddle
EuroSTAR Software Testing Conference 2009 presentation on Effective Test Automation a la Carte by Martin Gijsen. See more at conferences.eurostarsoftwaretesting.com/past-presentations/
“eXtending” the Automation Toolbox: Introduction to TwinCAT 3 Software and eX...Design World
The document provides an overview of TwinCAT 3 software and eXtended Automation (XA) from Beckhoff Automation. It discusses (1) how TwinCAT 3 addresses customer wishes from TwinCAT 2 like integration, C/C++ support, and migration capabilities, (2) the key aspects of XA including engineering (XAE), architecture (XAA), and runtime (XAR) environments, and (3) new TwinCAT 3 capabilities such as support for multi-core systems, connectivity tools, and migration from TwinCAT 2 projects.
Accelerating system verilog uvm based vip to improve methodology for verifica...VLSICS Design
In this paper we present the development of Acceleratable UVCs from standard UVCs in System Verilog
and their usage in UVM based Verification Environment of Image Signal Processing designs to increase
run time performance. This paper covers development of Acceleratable UVCs from standard UVCs for
internal control and data buses of ST imaging group by partitioning of transaction-level components and
cycle-accurate signal-level components between the software simulator and hardware accelerator
respectively. Standard Co-Emulation API: Modeling Interface (SCE-MI) compliant, transaction-level
communications link between test benches running on a host system and Emulation machine is established.
Accelerated Verification IPs are used at UVM based Verification Environment of Image Signal Processing
designs both with simulator and emulator as UVM acceleration is an extension of the standard simulationonly
UVM and is fully backward compatible with it. Acceleratable UVCs significantly reduces development
schedule risks while leveraging transaction models used during simulation.
In this paper, we discuss our experiences on UVM based methodology adoption on TestBench-Xpress
(TBX) based technology step by step. We are also doing comparison between the run time performance
results from earlier simulator-only environment and the new, hardware-accelerated environment. Although
this paper focuses on Acceleratable UVC’s development and their usage for image signal processing
designs. Same concept can be extended for non-image signal processing designs.
This document proposes a presentation on using a common mediation port in TTCN-3 to execute scripts from test cases. A mediation port is defined that accepts messages containing a script name and parameters. A TRI connects this port to a mediation server hosting scripts in languages like Shell and Perl. Test cases can call scripts by sending messages to the port. This allows tasks like controlling non-SUT devices and databases through scripts without recompiling test suites. Benefits include reduced compilation times when changes are needed and the ability to develop new interfaces quickly by moving functionality to reusable scripts.
Summarizing Software API Usage Examples Using Clustering TechniquesNikos Katirtzis
This document presents CLAMS, an approach for automatically mining API usage examples from client code. It clusters API usage sequences, generates summarized snippets from the top clusters, and selects the most representative snippet from each cluster. The methodology can be easily adapted to new programming languages as it relies on abstract syntax trees and API call sequences rather than detailed semantic analysis. The system is evaluated on datasets from several Java libraries and is shown to produce more concise, readable snippets that better match handwritten examples compared to approaches that output API call sequences or less summarized snippets. The clustering approach that allows similar rather than just identical sequences leads to improved results.
DCCN 2016 - Tutorial 1 - Communication with LAN/WLANrudndccn
The document introduces a tutorial on simulating communication between devices within LAN and WLAN networks using the Network Simulator 3 (NS-3). It describes creating a virtual machine with NS-3 and Eclipse for developing network simulations and demonstrates simulating a simple network topology with point-to-point, CSMA/CD Ethernet, and CSMA/CA WiFi links between nodes, including capturing traffic between an echo client and server using pcap tracing.
09 basics operating and monitoring v1.00_enconfidencial
The document discusses the basics of operating and monitoring a PCS 7 system. It describes the general functions of the operator station (OS) and how it can be configured as a single station or multiple station system. It also covers plant hierarchy settings, the OS-AS connection, compiling projects, layouts, block icons and faceplates. The key points are:
- The OS is based on WinCC and used for process visualization, alarm logging, tag logging, and more.
- A system can be a single OS or multiple OSs connected to one or more automation stations. Redundant servers provide high availability.
- Plant hierarchy settings determine how data is structured in pictures and tag names on the
The document discusses openness in the AXE telecommunications system from Ericsson. It defines two types of openness: network openness, which refers to the ability to interconnect with other networks using standard protocols, and system openness, which involves using commercially available standard hardware and software components to build the AXE system. The document outlines how Ericsson has increased system openness over time by introducing more standard components like commercial processors, Windows NT, and off-the-shelf hardware, while focusing proprietary development on the interface between components. This allows Ericsson to benefit from advances in other industries while concentrating on its core switching capabilities.
This document proposes a presentation on integrating the TTCN-3 testing framework with the Robot test automation framework and Jenkins continuous integration tool to provide end-to-end test automation. The integration allows TTCN-3 test cases to trigger Robot tests for GUI or web validations, with Robot notifying TTCN-3 when validations are complete. Jenkins is used to schedule and monitor repeated executions of Robot test cases across multiple environments. The approach provides benefits like GUI validation during TTCN-3 tests, configuration changes on remote systems during testing, and end-to-end test automation.
A NETWORK-BASED DAC OPTIMIZATION PROTOTYPE SOFTWARE 2 (1).pdfSaiReddy794166
The International Journal of Engineering and Science and Research is online journal in English published. The aim is to publish peer review and research articles without delay in the developing in engineering and science Research.The International Journal of Engineering and Science and Research is online journal in English published. The aim is to publish peer review and research articles without delay in the developing in engineering and science Research.
- Ankit Sarin has over 7 years of experience in embedded firmware development, hardware design, and integration testing. He has worked on projects in various domains including industrial automation, SCADA, rail, oil and gas, and consumer products.
- His skills include embedded C/C++, assembly language, various protocols and interfaces. He has experience with development tools and environments on 8/16/32 bit platforms.
- His most recent role is as a senior software engineer at Larsen & Toubro where he works on firmware development for solar inverters and railway products. Previously he has worked on projects for Invensys, Cognizant, and Philips.
As the complexity of the scan algorithm is dependent on the number of design registers, large SoC scan
designs can no longer be verified in RTL simulation unless partitioned into smaller sub-blocks. This paper
proposes a methodology to decrease scan-chain verification time utilizing SCE-MI, a widely used
communication protocol for emulation, and an FPGA-based emulation platform. A high-level (SystemC)
testbench and FPGA synthesizable hardware transactor models are developed for the scan-chain ISCAS89
S400 benchmark circuit for high-speed communication between the host CPU workstation and the FPGA
emulator. The emulation results are compared to other verification methodologies (RTL Simulation,
Simulation Acceleration, and Transaction-based emulation), and found to be 82% faster than regular RTL
simulation. In addition, the emulation runs in the MHz speed range, allowing the incorporation of software
applications, drivers, and operating systems, as opposed to the Hz range in RTL simulation or submegahertz
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Test system architectures using advanced standardized test languages
1. Test System Architectures using Advanced Standardized Test
Languages
1. 1. Axel Rennoch InSTA 2016, Chicago, 10th April 2016 TEST SYSTEM
ARCHITECTURES USING ADVANCED STANDARDIZED TEST LANGUAGES
2. 2. 2 Introduction Advanced standardized test languages TTCN-3 UML
testing profile TDL Test Automation Architecture Conclusions CONTENTS
3. 3. 3 Researcher at Fraunhofer FOKUS in Berlin, Germany User of
standardized Modelling and Test languages LOTOS, SDL/UML Tree and
Tabular Combined notation (TTCN-1&2) TTCN-3 user from the beginning
Developer for ETSI, 3GPP and industry Trainer and consultant Research
projects and evolution team AXEL RENNOCH
4. 4. 4 InSTA 2015: Keynote by Sigrid Eldh on Software Test Architecture
definition & aspects InSTA 2016: Continuation on Advanced Standardized
Test Languages for Test System Architecture means & examples, user
perspective MOTIVATION
5. 5. 5 maschine languages programming languages test description languages
test modelling languages CHALLENGES FOR TEST SYSTEMS Data type
integration SUT interfaces (physical distribution) Logical structure &
distribution Execution mapping
6. 6. 6 Identify SUT access interface points Test objectives: functional, load,
security? Target : standardization body (more abstraction, top down) or
in-house test solution (address concrete tools, bottom up) Parallel test
components (scalability?) Coordination & synchronization (existing
frameworks?) SOME INITIAL QUESTIONS FOR TEST DEVELOPERS
7. 7. 7 Introduction Advanced standardized test languages TTCN-3 UML
testing profile TDL Test Automation Architecture Conclusions CONTENTS
8. 8. 8 Testing and Test Control Notation Internationally standardized testing
language for formally defining test scenarios. Designed purely for testing
WHAT IS TTCN-3? testcase Hello_Bob () { p.send(“How do you do?“); alt {
[]p.receive(“Fine!“); {setverdict( pass )}; [else] {setverdict( inconc )} //Bob asleep!
} }
9. 9. 9 One test technology for different tests Distributed, platform-
independent testing Integrated graphical test development, -documentation
and –analysis Adaptable, open test environment Areas of Testing
Regression Testing Conformance and Functionality Testing Interoperability
and Integration Testing Load/ Stress Testing IDEA & DESIGN PRINCIPLES OF
TTCN-3
2. 10. 10. 10 testcase Hello_Bob () { p.send(“How do you do?“); alt {
[]p.receive(“Fine!“); {setverdict( pass )}; [else] {setverdict( inconc )} //Bob asleep!
} } TTCN-3 EXECUTION SUT System Tester TTCN-3 API / Network API /
Communication
11. 11. 11 TTCN-3 Test Case TTCN-3 IS DESIGNED FOR BLACK-BOX TESTING
Port.send(Stimulus) Port.receive(Response) System Under Test Port •
Assignment of a Test Verdict
12. 12. 12 A TTCN-3 TEST SYSTEM TE – TTCN-3 Executable TM – Test
Management TL – Test Logging CD – Codec CH – Component Handling SA –
System Adapter PA – Platform Adapter SUT – System Under Test ETSI ES 201
873-1 TTCN-3 Core Language (CL) ETSI ES 201 873-5 TTCN-3 Runtime
Interface (TRI) ETSI ES 201 873-6 TTCN-3 Control Interfaces (TCI) TM:
Management TL: Logging TE CD:Codec CH:Component Handling SA: System
Adapter PA: Platform Adapter TRI TCI Test System User System Under Test
(SUT)
13. 13. 13 IMPLEMENTATION ATS TE SUT Communication +TE Test System
14. 14. 14 MAJOR LANGUAGE ELEMENTS OF TTCN-3 NOTATION module
definitions Data Types User defined data types (messages, PDUs, information
elements, …) Test Data Test data transmitted/expected during test execution
(templates, values) Test Configuration Definition of the test components and
communication ports Test Behavior Specification of the dynamic test behavior
Imports Importing definitions from other modules defined in TTCN-3 or other
languages
15. 15. 15 Industrial use Big companies with hundreds of TTCN-3 engineers:
Ericsson, Nokia, Siemens, Motorola large distribution among SME
Standardization bodies standardized test suites: ETSI / 3GPP (LTE!)/ OMA /
TETRA and its members IMS performance benchmark project: Intel, HP, BT,
FOKUS and others Test tool manufacturer: Commercial Tektronix, Catapult,
Nexus, R&S, Spirent, … Certification program based on TTCN-3: e.g. WiMax
forum TTCN-3 DOMAINS: TELECOM
16. 16. 16 Secure UserPlane Location Protocol Single MTC controls e.g.: UlpPort
(Lup interface) IpcPort (IP configuration) smsPort used for SMS UtpPort
for upper tester commands IpiPort (IP information, e.g. release) NwcPort:
network bearer control, e.g. handover trigger SscPort: satellite simulation
control, e.g. scenario trigger TEST SYSTEM EXAMPLE 1: OMA SUPL BSF SUT
(SUPL Terminal) Network Bearer TCP/UDP/IP SMS Upper Tester Adapter e.g.
text utp Upper Tester Server IUT (SUPL Implementation) ulp sms TLS (PSK) ipi
MTC ssc DNS bsf TTCN-3 Executable SUT Adapter Satellite Simulator ipc
3. dnsnwc SUT (SUPL Terminal) Network Bearer TCP/UDP/IP MT_SMS, WAP_Push,
SIP_Push Upper Tester Adapter e.g. text utp Upper Tester Server IUT (SUPL
Implementation) ulp sms TLS (PSK) ipi MTC ssc TTCN-3 Executable SUT
Adapter Satellite Simulator ipcnwc
17. 17. 17 E-UTRAN (LTE air interface): 3GPP TS 36.523-3 V12.4.0 (2015-12)
Each radio access technology (RAT) is hosted by a separate TTCN-3 parallel
component: E-UTRAN, UTRAN, GERAN, others. PTCs are controlled by the
TTCN-3 main test component (MTC) which: is independent from the RAT;
may host the upper tester for MMI and AT commands; TEST SYSTEM
EXAMPLE 2: 3GPP UE TESTING Host-PC TTCN-3 generated code Codec Test
control, Logging System Adaptor (SA) Platform Adaptor (PA) System
dependent layers System Simulator HW internal interface UESystem
dependent layers Protocol layers internal interface air interface
18. 18. 18 Multiple of configurations Several PTCs Cooperating
Communicating TEST SYSTEM EXAMPLE 2: 3GPP UE TESTING
19. 19. 19 Simple scenario Reuse of nested component types for MTC, PTCs
and TSI TEST SYSTEM EXAMPLE 2: 3GPP UE TESTING
20. 20. 20 More complex configuration Nested component types Illustration
using Visual Paradigm TEST SYSTEM EXAMPLE 2: 3GPP UE TESTING
21. 21. 21 Car communication systems Daimler, Volkswagen, SiemensVDO
edutainment bus system (test suite) Standardization groups: AUTOSAR
consortium MOST cooperation Car-to-car communication TTCN-3
DOMAINS: AUTOMOTIVE Telematics Applications in the Cockpit • Audio (CD /
Radio), Video • Telephone, SMS • Navigation • Speech recognition • User
interface for body electronic loudness playCDTitle Test cases: MOST Bus Head
Unit Tester Speaker Amplifier / Tuner CD Changer
22. 22. 22 Medicine SiemensMED (image processing) HL7 eHealth protocols
(Interoperability) Upcoming E-Health infrastructure for Germany High
security requirements (e.g. certificates, cryptography) Test development prior
to SUT availability Multiple heterogenous interfaces: cardterminals,, card
simulations, Webservices, OCSP server etc. TTCN-3 DOMAINS: MEDICINE
23. 23. 23 Complex configuration Illustration using IBM Rational Enterprise
Architect: - PTC, - simulators, - SUT (mock), - real server, - adaptation code
TEST SYSTEM EXAMPLE 3: E-HEALTH “KONNEKTOR”
24. 24. 24 Source STF 276 (IPv6 project) Set of TTCN-3 functions to e.g.
Start and control parallel components Exchange synchronization signals
between components Set of charstring constants for synchronization points
preambleDone, sync1, sync2 testbodyDone Predefined timers e.g. to
4. avoid deadlocks at synchronization points http://www.ttcn-
3.org/index.php/development/devlibraries/devlib-libcommon ETSI
FRAMEWORK FOR SYNCHRONISATION
25. 25. 25 Synchronization occurs between parallel TTCN-3 components (using
signals via MTC) Sync 1 ensures the completion of senders procedure
Sync 2 confirms the arrival of a message at receivers side SYNCHRONIZATION
SAMPLES Sender Receiver sync 2 S U T sync 1
26. 26. 26 Test suite specific code testcase, test (component) functions Test
suite specific library Component types, test configuration, pre/postamble
Interface/protocol specific library SIP, DNS, IPv6 etc. Interface/protocol
independent library synchronizaton MODULE IMPORT „LAYERING“ Low level:
(High reusability) high level: (low reusability)
27. 27. 27 400 subscribers per component Handler Component Sender
initializes/provides data requests for load-generator 5.000 - 10.000 IMS
subscribers (per server) Up to 250 requests per second (per server) EXAMPLE
4: IMS BENCHMARK TEST CONFIGURATION Sender Component usr1 usr2
usrN Handler 1 Component usrN+1 Handler 2 Component System Adapter
(SUT Interface) usrN+2 usrN+3 Load Generator SUT
28. 28. 28 Study access interface points (Test System Interface) Available Test
solution plugins? Test objectives: functional, load, security? Consider
synchronization overhead (e.g. ETSI’s LibCommon) Consider performance
issues (e.g. encoded data preparation) Concurrent test components with
separated traces & verdicts (easier failure analysis) Consider test tool
logging functions Improve decomposition using libraries for handling
single interface types Nested component types (to be extended) Use
modelling tools for the illustration of the TTCN-3 architecture LESSONS
LEARNED WITH TTCN-3
29. 29. 29 29 TTCN-3 is used in several domains as binding link between
modelling and execution Commercial tools do generate TTCN-3 code for
test execution lots of academic prototype tools Selection of industrial case
studies: e.g. European MIDAS project pilots in SOA testing automation (later)
BEYOND TTCN-3: MBT
30. 30. 30 Objective: To develop an efficient test platform fulfilling industrial
testing requirements To execute high-level test models, e.g. UML testing
profile Industrial Testing Requirements ... UML 2.0 Testing Profile System
DesignEmbedded Systems Avionics Railway Systems Mobile Communication
Automotive TTCN-3 Test Design An efficient test platform Methods, Tools,
Guidelines Test Results Approach TTCN-3 LINK TO UTP
5. 31. 31. 31 Introduction Advanced standardized test languages TTCN-3
UML testing profile TDL Test Automation Architecture Conclusions
CONTENTS
32. 32. 32 Standard by the Object Management Group: Version 1.0 (2004),
current version 1.2 (2013), revised draft version 2.0 (Nov 2015) Profile of
UML version 2: Industrial standard for (graphical) modeling of Test
architectures, behavior and data. Conceptual Model: Test context, cases,
objectives, data, configuration, arbitration&verdicts, logs UTP library:
predefined types and values (e.g. ISO 25010 Quality model, ISTQB Test levels)
Extras: Mapping to TTCN-3 (procedure-based communication only) UML
TESTING PROFILE (UTP)
33. 33. 33 Standardized mapping of UTP stereotypes to UML metaclasses TEST
CONFIGURATION OVERVIEW
34. 34. 34 LoginServer test components LoginServer test configuration UTP
TEST CONFIGURATION EXAMPLE (UTP 2.0 ONLY!)
35. 35. 35 Domain-independent test modeling for dynamic testing approaches:
Test environments, test configurations, test case specifications (including test
case derivation), test data specifications/values Test evaluation, i.e.,
managing and visualization of test results Integration of best practices such
as keyword-driven testing, equivalence class testing, etc. Combination with
other UML profiles (e.g., SysML, MARTE, SoaML) E.g. to achieve
requirements traceability, … UTP MAJOR USE
36. 36. 36 Current version 1.2 less industrial use since version 1.0 ten years
ago No big test suites Only some tooling UTP Revision 2.0 is promising
E.g. covers test configuration LESSONS LEARNED WITH UTP
37. 37. 37 Introduction Advanced standardized test languages TTCN-3
UML testing profile TDL Test Automation Architecture Conclusions
CONTENTS
38. 38. 38 New ETSI Standard ES 203 119-1 (V1.2.0, 2015-04) Fills gap
between the high-level test purposes and TTCN-3 Simple Text notation with
graphical presentation TEST DESCRIPTION LANGUAGE
39. 39. 39 Typed components and gates Timers and variables connections
among gates component roles TDL TEST CONFIGURATION
40. 40. 40 Pure testing view Compromise between UTP and TTCN-3 Simple
Executable Not ready to use LESSONS LEARNED WITH TDL
41. 41. 41 Introduction Advanced standardized test languages TTCN-3
UML testing profile TDL Test Automation Architecture Conclusions
CONTENTS
6. 42. 42. 42 THE ISTQB FUNDEMANTAL TEST PROCESS Test Analysis Test
Implementation Test Design Test Execution Test Evaluation Test Closing
Activities Management Control T C SUT T C SUT T C SUT T C SUT T C SUT T C
SUT Test Scripts SUT Automated test design(MBT) Automated test execution
(KDT, DDT, TTCN-3) Test execution tool System under test Knowledge Test
model Test generator Test generator Model transformation Automated test
execution is state of the practice (if ever) in industry
43. 43. 43 ABSTRACTION LEVELS IN TEST AUTOMATION Test design activities
Technical test cases (ABS. LEVEL 2) Test model (ABS. LEVEL 3) Logical test
cases (ABS. LEVEL 3) Actual implementation (ABS. LEVEL 0) Test analysis
activities Adaptation layer (ABS. LEVEL 2->0) Test implementation activities
Test execution activities requires SRS (ABS. LEVEL 4) TestExecution System
Testmodelingand generationtool Executable test cases Logical actions the
system can perform Sequence diagram, Test Descriptions UML Testing Profile,
TDL TTCN-3, XML, Excel Implementation, TRI, SA, CoDEC KDT, DDT, TTCN-3
44. 44. 44 Model is master - Test design independent from adaptation layer or
test execution system - No constraint on the test execution system - Often
used in academic prototypes TOP-DOWN APPROACH SRS (ABS. LEVEL 4)
Adaptation layer (ABS. LEVEL 2->0) Technical test cases (ABS. LEVEL 2) Test
model (ABS. LEVEL 3) Recommendation Feasible for proof-of-concepts, limited
use for industry
45. 45. 45 BOTTOM-UP APPROACH SRS (ABS. LEVEL 4) Test model (ABS. LEVEL 2)
Adaptation layer (ABS. LEVEL 2->0) Technical test cases (ABS. LEVEL 2)
Adaptation layer is master - Ensures immediate automated test exection -
Requires available adaption layer - Test model derived from the adaption layer
Recommendation Only if adaptation layer is clear for test developers
46. 46. 46 Test Execution Layer Test Generation Layer TEST AUTOMATION
ARCHITECTURE: MIDAS MIDAS Test Model FuzzingFunctional Usage-based
Test Definition Layer SOA System MDTA Framework MIDAS TPaaS MIDAS Test
Model + Test Cases TTCN-3 Modules (complete) exhibits import WSDL/XSD
47. 47. 47 Two approaches have been shown Bottom-up approach was
realized in MIDAS Integration of data types (e.g. WSDL) is challenging
(Initial) engineering effort can be quite high LESSONS LEARNT FROM TEST
AUTOMATION ARCHITECTURE
48. 48. 48 Introduction Advanced standardized test languages TTCN-3
UML testing profile TDL Test Automation Architecture Conclusions
CONTENTS
7. 49. 49. 49 TTCN-3 UTP TDL Standardization body ETSI, ITU-T OMG ETSI History
Since 1992 Since 2004 Since 2014 Applicability All domains and testing types
All domains Conformance, interop Execution tools and solutions + proprietary
via C-unit TTCN-3 mapping in preparation Current user groups Industry,
Research Academic, Research n/a SUMMARY: OVERVIEW
50. 50. 50 TTCN-3 UTP 2 TDL Component extension + UML generalization -
(reuse elements) Coordination/ synchronization +via libraries using general
ordering explicitly Import of WSDL, IDL, etc. (+) proprietary via SoaML -
Graphical Test architecture - needed! + + Link to UML - + in preparation
SUMMARY: TEST ARCHITECTURE
51. 51. 51 They significantly increases your system quality. You can focus on
what to test, not on how. They reduce costs and efforts in test system
maintenance. They are independent of access technology, operating system
and implementation domain They support communication between system
development and test department. You can count on available, trained and
certified experts GOOD REASONS FOR STANDARDIZED TEST LANGUAGES
52. 52. 52 TTCN-3, UTP and TDL - international Standards for testing - allow
abstract definitions for testing - (partly) accepted in research and industry -
Tool support (still week) - UML -> UTP/TDL -> TTCN-3 - Test automation
need further enhancements CONCLUSION
53. 53. 53 Online information www.ttcn-3.org TTCN-3 User Conference
2016 in in Budapest, Hungary TTCN-3 Standards, Papers, Book
http://www.ttcn.de/ Quick Reference http://www.blukaktus.com/ Exercises
and Tooling research licenses TTCN-3 SOURCES
54. 54. 54 Online information http://utp.omg.org/ MBT User Conference
2016 in Budapest, Hungary UTP Standards http://www.omg.org/spec/UTP/
MDT/UTP Book http://www.springer.com Exercises and Tooling
research licenses UTP SOURCES
55. 55. 55 Online information http://tdl.etsi.org/ TDL User Conference 2016
in Budapest, Hungary TDL Standards
http://tdl.etsi.org/index.php/downloads Exercises and Tooling (in
preparation) https://portal.etsi.org//STF/STFs/STFHomePages/STF492.aspx
TDL SOURCES
56. 56. 56 Thank you for your attention! www.fokus.fraunhofer.de (System Quality
Center)
57. 57. 57 Fraunhofer FOKUS Kaiserin-Augusta-Allee 31 10589 Berlin, Germany
www.fokus.fraunhofer.de Axel Rennoch Project Manager
axel.rennoch@fokus.fraunhofer.de Phone +49 30 3463-7344 CONTACTS Marc‐