Aec ppt2

PREPARED BY
MS.SHANKHA MITRA SUNANI
ASSISTANT PROFESSOR IN THE DEPARTMENT OF
ELECTRONICS AND TELECOMMUNICATION
ENGINEERING
GOVERNMENT ENGINEERING COLLEGE PMEC
BERHAMPUR,GANJAM,SITALAPALLI

MODULE -1
CHAPTER-1 (BIPOLAR JUNCTION TRANSISTOR-BJT)
i. Introduction to BJT
ii. What is biasing
iii. Need of biasing
iv. Load line analysis
v. Type of biasing and its description
vi. Stabilisation
CHAPTER-2 (FIELD EFFECT TRANSISTOR-FET)
i. Introduction to FET
ii. Difference between BJT &FET
iii. Operation of JFET
iv. JFET Biasing
v. Metal Oxide Semiconductor Field Effect Transistors(MOSFET)
vi. D-MOSFET(Depletion type MOSFET)
vii. E-MOSFET(ENHANCEMENT-MOSFET)
CONT………

CHAPTER-3 SMALL SIGNAL ANALYSIS OF BJT
i. Introduction
ii. re Transistor Model of Common Base (CB) Configuration
iii. re Transistor Model of Common Emitter (CE)Configuration
iv. BJT small signal analysis of CE BYPASS configuration
v. BJT small signal analysis of CE UN BYPASS configuration
vi. Emitter Follower configuration
vii. Effect of RS and RL In CE configuration
cont…….

 Signal Equivalent-Circuit Model
 Small Signal Analysis of CS, CD, CG Amplifiers
 Effects of RSIG and RL on CS Amplifier
 Source Follower and Cascaded System
MODULE-3
High Frequency Response of FETs and BJTs
 High Frequency equivalent models and frequency Response of BJTs and FETs
 Frequency Response of CS Amplifier
 Frequency Response of CE Amplifier
CONT……..

Operational Amplifier
 Introduction to opamp and Ideal Op-Amp
 Op-Amp Parameters, , Non-inverting Configurations, ,
and Inverting Configurations
 Differential Amplifier, Differentiator and Integrator
 Instrumentation amplifier
Feedback amplifier and Oscillators
 Concepts of negative and positive feedback
 Four Basic Feedback Topologies
 Principle of Sinusoidal Oscillator
 Phase Shift and Crystal Oscillator Circuits
 Wein-Bridge Oscillator Circuits

6
MODULE-1 INTRODUCTION TO Transistors
•The word transistor consists of two terms TRANSFER AND RESISTOR.It
is the electronic device that transfer the input signal from one
resistance circuit to other resistance circuit.They are unidirectional
current carrying devices with capability to control the current flowing
through them
• The switch current can be controlled by either current or voltage
•There are mainly two types of transistor
1. Bipolar Junction Transistors (BJT) control current by current
2. Field Effect Transistors (FET) control current by voltage
•They can be used either as switches or as amplifiers.
•Bipolar junction Transistor is a three terminal,two junaction device.
•A junction Transistor is simply a sandwitch of one type of
semiconductor material between two layers of other type. Acoordingly
there are two type of transistors:
1. N-P-N Transistor
2. P-N-P Transistors

The BJT – Bipolar Junction Transistor
Note: Normally Emitter layer is heavily doped, Base layer is lightly doped and
Collector layer has Moderate doping.
The Two Types of BJT Transistors:
npn pnp
n p nE
B
C p n pE
B
C
Cross Section Cross Section
B
C
E
Schematic
Symbol
B
C
E
Schematic
Symbol
• Collector doping is usually ~ 109
• Base doping is slightly higher ~ 1010 – 1011
• Emitter doping is much higher ~ 1017

BJT Current & Voltage - Equations
B
CE
IE IC
IB
-
+
VBE VBC
+
-
+- VCE
B
CE
IE IC
IB
-
+
VEB VCB
+
-
+ -VEC
n p n
IE = IB + IC
VCE = -VBC + VBE
p n p
IE = IB + IC
VEC = VEB - VCB

DC  and DC 
 = Common-emitter current gain
 = Common-base current gain
 = IC  = IC
IB IE
The relationships between the two parameters are:
 =   = 
 + 1 1 - 
Note:  and  are sometimes referred to as dc and dc
because the relationships being dealt with in the BJT
are DC.

10
BJT  and 
•From the previous figure iE = iB + iC
•Define  = iC / iE
•Define  = iC / iB
•Then  = iC / (iE –iC) =  /(1- )
•Then iC =  iE ; iB = (1-) iE
•Typically   100 for small signal BJTs (BJTs that
handle low power) operating in active region (region
where BJTs work as amplifiers)
•Note:  and  are sometimes referred to as dc and dc
because the relationships being dealt with in the BJT are DC

Various Regions (Modes) of Operation of BJT
• Most important mode of operation
• Central to amplifier operation
• The region where current curves are practically flat
Active:
Saturation: • Barrier potential of the junctions cancel each other out
causing a virtual short (behaves as on state Switch)
Cutoff: • Current reduced to zero
• Ideal transistor behaves like an open switch
* Note: There is also a mode of operation called
inverse active mode, but it is rarely used.

Three Possible Configurations of BJT
Biasing the transistor refers to applying voltages to the
transistor to achieve certain operating conditions.
1. Common-Base Configuration (CB) : input = VEB & IE
output = VCB & IC
2. Common-Emitter Configuration (CE): input = VBE & IB
output= VCE & IC
3. Common-Collector Configuration (CC) :input = VBC & IB
(Also known as Emitter follower) output = VEC & IE

Common-Base BJT Configuration
Circuit Diagram: NPN Transistor
+
_
+
_
IC IE
IB
VCB VBE
EC
B
VCE
VBEVCB
Region of
Operation
IC VCE VBE VCB
C-B
Bias
E-B
Bias
Active IB =VBE+VCE ~0.7V  0V Rev. Fwd.
Saturation Max ~0V ~0.7V -0.7V<VCE<0 Fwd. Fwd.
Cutoff ~0 =VBE+VCE  0V  0V Rev.
None
/Rev.
The Table Below lists assumptions
that can be made for the attributes
of the common-base BJT circuit in
the different regions of operation.
Given for a Silicon NPN transistor.

14
The basic function of transistor is amplification. The process of raising the
strength of weak signal without any change in its general shape is
referred as faithful amplification. For faithful amplification it is essential
that:-
1. Emitter-Base junction is forward biased
2. Collector- Base junction is reversed biased
3. Proper zero signal collector current
The proper flow of zero signal collector current and the maintenance of
proper collector emitter voltage during the passage of signal is
called transistor biasing.
WHY BIASING?
If the transistor is not biased properly, it would work inefficiently
and produce distortion in output signal.
HOW A TRANSISTOR CAN BE BIASED?
A transistor is biased either with the help of battery or associating a
circuit with the transistor. The later method is more efficient and is
frequently used. The circuit used for transistor biasing is called the
biasing circuit.

15
 Fixed Bias Circuit
 Fixed Bias with Emitter Resistor/Emitter Stabilized bias
 Collector to Base Bias Circuit
 Potential Divider Bias Circuit
BJT ‘Q’ Point (Bias Point)
• Q point means Quiescent or Operating point
• Very important for amplifiers because wrong ‘Q’ point selection increases
amplifier distortion
• Need to have a stable ‘Q’ point, meaning the the operating point should not be
sensitive to variation to temperature or BJT , which can vary widely

(a) Representation of fixed-bias circuit (b) Equivalent circuit
 Fixed-bias circuit
 Base–emitter loop  Collector–emitter loop
and

Emitter Stabilized Bias circuit
 Base–emitter loop
and the emitter current can be written
as
From above two equation we
get:
 Collector–emitter loop
with the base current known,
IC can be easily calculated by
the relation IC = βIB.
Emitter Stabilized bias circuit

 Voltage-divider bias:- The Thevenins equivalent voltage and resistance for
the input side is given by:
Voltage-divider bias circuit Simplified voltage-divider circuit
and
The KVL equation for the input circuit is given as:

Representation of Voltage-feedback biased circuit
 Voltage-feedback biasing
 Base–emitter loop
Applying KVL for this part, we get:
Thus, the base current can be obtained as:

Fig. 1
 The dc load line is a graph that allows us to determine all possible
combinations of IC and VCE for a given amplifier.
 For every value of collector current, IC, the corresponding value of VCE
can be found by examining the dc load line.
 A sample dc load line is shown in Fig. 1.
Without an ac signal applied to a transistor, specific values of IC and VCE exist at a
specific point on a dc load line This specific point is called the Q point (quiescent
currents and voltages with no ac input signal)
An amplifier is biased such that the Q point is near the center of dc load line
ICQ = ½ IC(sat)
VCEQ = ½ VCC
Base bias provides a very unstable Q point, because IC and VCE are greatly affected by
any change in the transistor’s beta value

21
BIAS STABILITY
 Through proper biasing, a desired quiescent operating point of the
transistor amplifier in the active region (linear region) of the
characteristics is obtained. It is desired that once selected the operating
point should remain stable.
The maintenance of operating point stable is called Stabilisation.
 The selection of a proper quiescent point generally depends on the
following factors:
(a) The amplitude of the signal to be handled by the amplifier and
distortion level in signal
(b) The load to which the amplifier is to work for a corresponding
supply voltage
 The operating point of a transistor amplifier shifts mainly with changes
in temperature, since the transistor parameters — β, ICO and VBE (where
the symbols carry their usual meaning)—are functions of temperature.

The Thermal Stability Factor : SIcoSIco = ∂Ic
∂Ico constant
This equation signifies that Ic Changes SIco times as fast as Ico
Differentiating the equation of Collector Current IC & rearranging the terms we can
write
SIco ═ 1+β
1- β (∂Ib/∂IC)
It may be noted that Lower is the value of SIco better is the stability
Vbe, β
Stability Factor S’:- The variation of IC with VBE is given by the stability factor S’
defined by the partial derivative:
 Stability Factor S″:- The variation of IC with respect to β is represented by
the stability factor, Sβ, given as:

15 V
C
E
B
15 V
200 k 1 k
The Thermal Stability Factor : SIco
SIco = ∂Ic
∂Ico
General Equation of SIco Comes out to be
SIco ═ 1 + β
1- β (∂Ib/∂IC)
Vbe, β
Applying KVL through Base Circuit we can
write, Ib Rb+ Vbe= Vcc
Diff w. r. t. IC, we get (∂Ib / ∂Ic) = 0
SIco= (1+β) is very large
Indicating high un-stability
Ib
Rb
RC
RC

The General Equation for Thermal
Stability Factor,
SIco = ∂Ic
∂Ico
Comes out to be
SIco ═ 1 + β
1- β (∂Ib/∂IC)
Vbe, β
Applying KVL through base circuit
we can write (Ib+ IC) RC + Ib RF+ Vbe= Vcc
Diff. w. r. t. IC we get
(∂Ib / ∂Ic) = - RC / (RF + RC)
Therefore, SIco ═ (1+ β)
1+ [βRC/(RC+ RF)]
Which is less than (1+β), signifying better
thermal stability
VCC
RC
C
E
B
RF
Ic
Ib
VBE
+
- IE

VCC
RC
C
E
B
VCC
R1
RER2
The General Equation for Thermal Stability
Factor, SIco ═ 1 + β
1- β (∂Ib/∂IC)
Applying KVL through input base circuit
we can write IbRTh + IE RE+ Vbe= VTh
Therefore, IbRTh + (IC+ Ib) RE+ VBE= VTh
Diff. w. r. t. IC & rearranging we get
(∂Ib / ∂Ic) = - RE / (RTh + RE)
Therefore,
This shows that SIco
is inversely proportional to
RE and It is less than (1+β), signifying better
thermal stability
VCC
RC
C
E
B
RE
RTh
VTh_
+
Thevenin
Equivalent Ckt
IC
Ib
IC
Ib
IC
Thevenins
Equivalent
Voltage
Self-bias Resistor
Rth
= R1*R2 & Vth
= Vcc R2
R1+R2 R1+R2








ThRR
R
E
E
IcoS


1
1

JFET is a unipolar-transistor, which acts as a voltage
controlled current device and is a device in which current
at two electrodes is controlled by the action of an
electric field at a reversed biased p-n junction.
MOSFET Field effect transistor is a unipolar transistor,
which acts as a voltage-controlled current device and is a
device in which current at two electrodes drain and
source is controlled by the action of an electric field at
another electrode gate having in-between semiconductor
and metal very a thin metal oxide layer .
.

Junction Field Effect Transistor (JFET) A junction field effect
transistor is a three terminal semiconductor device in which current
conduction is by one type of carrier i.e., electrons or holes.
In a JFET, the current conduction is either by electrons or holes and
is controlled by means of an electric field between the gate
electrode and the conducting channel of the device.
The JFET has high input impedance and low noise level.
A JFET consists of a p-type or n-type silicon bar containing two pn
junctions at the sides .
The bar forms the conducting channel for the charge carriers. If the
bar is of n-type, it is called n-channel JFET and if the bar is of p-
type, it is called a p-channel JFET.
The two pn junctions forming diodes are connected *internally and a
common terminal called gate is taken out. Other terminals are
source and drain taken out from the bar as shown. Thus a JFET has
essentially three terminals viz., gate (G), source (S) and drain (D

 Principle. The two pn junctions at the sides form two depletion
layers. The current conduction by charge carriers (i.e. free
electrons in this case) is through the channel between the two
depletion layers and out of the drain.
 The width and hence *resistance of this channel can be controlled
by changing the input voltage VGS.
 The greater the reverse voltage VGS, the wider will be the
depletion layers and narrower will be the conducting channel. The
narrower channel means greater resistance and hence source to
drain current decreases.
 Reverse will happen should VGS decrease. Thus JFET operates on
the principle that width and hence resistance of the conducting
channel can be varied by changing the reverse voltage VGS. In
other words, the magnitude of drain current (ID) can be changed
by altering VGS. Working.

The working of JFET is as under : (i) When a voltage VDS is applied
between drain and source terminals and voltage on the gate is zero
.the two pn junctions at the sides of the bar establish depletion
layers. The electrons will flow from source to drain through a
channel between the depletion layers. The size of these layers
determines the width of the channel and hence the current
conduction through the bar.
(ii) When a reverse voltage VGS is applied between the gate and
source .the width of the depletion layers is increased. This
reduces the width of conducting channel, thereby increasing the
resistance of n-type bar. Consequently, the current from source to
drain is decreased. On the other hand, if the reverse voltage on the
gate is decreased, the width of the depletion layers also decreases.
This increases the width of the conducting channel and hence
source to drain current.

Difference Between JFET and Bipolar Transistor
The JFET differs from an ordinary or bipolar transistor in the
following ways :
(i) In a JFET, there is only one type of carrier, holes in p-type
channel and electrons in n-type channel. For this reason, it is
also called a unipolar transistor. However, in an ordinary
transistor, both holes and electrons play part in conduction.
Therefore, an ordinary transistor is sometimes called a bipolar
transistor.
(ii) As the input circuit (i.e., gate to source) of a JFET is reverse
biased, therefore, the device has high input impedance.
However, the input circuit of an ordinary transistor is forward
biased and hence has low input impedance.
(iii) The primary functional difference between the JFET and the
BJT is that no current (actually, a very, very small current)
enters the gate of JFET (i.e. IG = 0A). However, typical BJT
base current might be a few μA while JFET gate current a
thousand times smaller

(iv) A bipolar transistor uses a current into its base to control a large
current between collector and emitter whereas a JFET uses voltage on the
‘gate’ ( = base) terminal to control the current between drain (= collector)
and source ( = emitter). Thus a bipolar transistor gain is characterised by
current gain whereas the JFET gain is characterised as a transconductance
i.e., the ratio of change in output current (drain current) to the input (gate)
voltage.
(v) In JFET, there are no junctions as in an ordinary transistor. The
conduction is through an n- type or p-type semi-conductor material. For this
reason, noise level in JFET is very small.

Important Terms
In the analysis of a JFET circuit, the following important terms are often
used :
1. Shorted-gate drain current (IDSS)
2. Pinch off voltage (VP)
3. Gate-source cut off voltage [VGS (off)]
1. Shorted-gate drain current (IDSS). It is the drain current with source
short-circuited to gate (i.e. VGS = 0) and drain voltage (VDS) equal to
pinch off voltage. It is sometimes called zero-bias current.
2. JFET circuit with VGS = 0 i.e., source shorted-circuited to gate. This is
normally called shorted-gate condition.

2. Pinch off Voltage (VP). It is the minimum drain-source voltage at which
the drain current essentially becomes constant.
Gate-source cut off voltage VGS (off). It is the gate-source voltage where
the channel is completely cut off and the drain current becomes zero.

Expression for Drain Current (ID)

Parameters of JFET
Like vacuum tubes, a JFET has certain parameters which determine its
performance in a circuit. The
main parameters of a JFET are (i) a.c. drain resistance (ii) transconductance
(iii) amplification factor.
(i) a.c. drain resistance (rd). Corresponding to the a.c. plate resistance,
we have a.c. drain resistance in a JFET. It may be defined as follows :

Fixed bias circuit
Self bias circuit
Potential Divider bias circuit
For all FETs: AIG 0 SD II  2
P
GS
DSSD )
V
V
(1II 
Fixed-Bias Configuration
For the DC analysis,Capacitors are open circuit
and The zero-volt drop across RG permits replacing
RG by a short-circuit
AIG 0 VRARIV GGGRG 0)0( 

Applying kvl in the input loop
•IG=0A, therefore VRG=IGRG=0V
Applying KVL for the input loop,-VGG-VGS=0
VGG= -VGS
•It is called fixed-bias configuration due to VGG is a
fixed power supply so VGS is fixed
•The resulting current
DDSDDDS
P
GS
DSSDS
RIVV
V
V
II








and
1
2
VVS 0
SDDS VVV  SDSD VVV  0SV
SGGS VVV  SGSG VVV  0SV
GSG VV 

Using below tables, we can draw the graph
VGS ID
0 IDSS
0.3VP IDSS/2
0.5 IDSS/4
VP 0mA
43
The fixed level of VGS has been superimposed as a vertical line at
•At any point on the vertical line, the level of VG is -VGG--- the level of ID
must simply be determined on this vertical line.
•The point where the two curves intersect is the common solution to the
configuration – commonly referrers to as the quiescent or operating point.
•The quiescent level of ID is determine by drawing a horizontal line from the
Q-point to the vertical ID axis
GGGS VV 

The controlling VGS is now determined by the voltage across
the resistor RS
44
For the indicated input loop:
SDGS RIV 
Mathematical approach
2
2
1
1














P
SD
DSSD
P
GS
DSSD
V
RI
II
V
V
II

Graphical approach
 Draw the device transfer characteristic ID VERSUS VGS
 Draw the network load line
 Use to draw straight line.
 First point,
 Second point, any point from ID = 0 to ID = IDSS. Choose
 the quiescent point obtained at the intersection of the
straight line plot and the device characteristic curve.
 The quiescent value for ID and VGS can then be
determined and used to find the other quantities of
interest.
SDGS RIV 
0,0  GSD VI
2
2
SDSS
GS
DSS
D
RI
V
then
I
I


45

46
Apply KVL of output loop Use
ID = IS
RDDDSDSD
SDS
DSDDDDS
VVVVV
RIV
RRIVV


 )(

47
IG = 0A ,Kirchoff’s current law requires
that IR1= IR2 and the series equivalent
circuit appearing to the left of the figure
can be used to find the level of VG.
VG can be found using the voltage divider
rule :

21
DD2
G
RR
VR
V


SDGGS
RSGSG
RIVV
VVV

 0
VG can be found using the voltage divider rule :
Using Kirchoff’s Law on the input loop:
Rearranging and using ID =IS:
Again the Q point needs to be established by plotting a
line that intersects the transfer curve.
48

1. Plot the line: By plotting two points: VGS = VG, ID =0 and VGS = 0, ID = VG/RS
2. Plot the transfer curve by plotting IDSS, VP and calculated values of ID.
3. Where the line intersects the transfer curve is the Q point for the circuit.
49

Once the quiescent values of IDQ and VGSQ are determined, the remaining
network analysis can be found.
Output loop )( SDDDDDDS RIRIVV 
DDDDD RIVV 
SDS RIV 

Metal Oxide Semiconductor FET (MOSFET)
The main drawback of JFET is that its gate must be reverse biased
for proper operation of the device i.e. it can only have negative gate
operation for n-channel and positive gate operation for p-channel.
This means that we can only decrease the width of the channel (i.e.
decrease the *conductivity of the channel) from its zero-bias size.
This type of operation is referred to as **depletion-mode operation.
Therefore, a JFET can only be operated in the depletion-mode.
However, there is a field effect transistor (FET) that can be
operated to enhance (or increase) the width of the channel (with
consequent increase in conductivity of the channel) i.e. it can have
enhancement-mode operation. Such a FET is called MOSFET.
A field effect transistor (FET) that can be operated in the
enhancement-mode is called a MOSFET.
A MOSFET is an important semiconductor device and can be used in
any of the circuits covered for JFET. However, a MOSFET has several
advantages over JFET including high input impedance
and low cost of production.

Types of MOSFETs
There are two basic types of MOSFETs viz.
1. Depletion-type MOSFET or D-MOSFET. The D-MOSFET can be operated in
both the depletion- mode and the enhancement-mode. For this reason, a D-
MOSFET is sometimes called depletion/enhancement MOSFET.
2. Enhancement-type MOSFET or E-MOSFET. The E-MOSFET can be
operated only in enhancement-mode. The manner in which a MOSFET is
constructed determines whether it is D-MOSFET or EMOSFET.
1. D-MOSFET the constructional details of n-channel D-MOSFET. It is
similar to n-channel JFET except with the following modifications/remarks :
(i) The n-channel D-MOSFET is a piece of n-type material with a p-type
region (called substrate) on the right and an insulated gate on the left as
shown in Fig. 19.43. The free electrons (Q it is n-channel) flowing from
source to drain must pass through the narrow channel between the gate and
the p-type region (i.e. substrate).
(ii) Note carefully the gate construction of D-MOSFET. A thin layer of
metal oxide (usually silicon dioxide, SiO2) is deposited over a small portion
of the channel. A metallic gate is deposited over the oxide layer. As SiO2 is
an insulator, therefore, gate is insulated from the channel. Note that
the arrangement forms a capacitor. One plate of this capacitor is the gate
and the other plate is the channel with SiO2 as the dielectric. Recall that we
have a gate diode in a JFET.

(iii) It is a usual practice to connect the substrate to the source (S)
internally so that a MOSFET has three terminals viz source (S), gate (G)
and drain (D).
(iv) Since the gate is insulated from the channel, we can apply either
negative or positive voltage to the gate. Therefore, D-MOSFET can be
operated in both depletion-mode and enhancement-mode. However, JFET
can be operated only in depletion-mode.

2. E-MOSFETthe constructional details of n-channel E-MOSFET.
Its gate construction is similar to that of D-MOSFET. The E-MOSFET
has no channel between source and drain unlike the D-MOSFET. Note
that the substrate extends completely to the SiO2 layer so that no
channel exists. The E-MOSFET requires a proper gate voltage to form
a channel (called induced channel). It is reminded that E-MOSFET can
be operated only in enhancement mode.
In short, the construction of E-MOSFET is quite similar to that of the
D-MOSFET except for the absence of a channel between the drain
and source terminals.
Why the name MOSFET ? The reader may wonder why is the
device called MOSFET?
The answer is simple. The SiO2 layer is an insulator. The gate
terminal is made of a metal conductor. Thus, going from gate to
substrate, you have a metal oxide semiconductor and hence the
name MOSFET.Since the gate is insulated from the channel, the
MOSFET is sometimes called insulated-gate FET (IGFET). However,
this term is rarely used in place of the term MOSFET.

Symbols for D-MOSFET
There are two types of D-MOSFETs viz (i) n-channel D-MOSFET and (ii) p-
channel D-MOSFET.
(i) n-channel D-MOSFET, the various parts of n-channel D-MOSFET.
The p-type substrate constricts the channel between the source and drain so
that only a small passage

D-MOSFET Transfer Characteristic
the transfer characteristic curve (or transconductance curve) for n-channel
D-MOSFET.The behaviour of this device can be beautifully explained with the
help of this curve as under :

Depletion-Type MOSFET BIASING TECHNIQUES
Depletion-type MOSFET bias circuits are similar to JFETs. The only difference
is that the depletion-Type MOSFETs can operate with positive values of VGS
and with ID values that exceed IDSS.
The DC Analysis
 Same as the FET calculations
 Plotting the transfer characteristics of the device
 Plotting the at a point that VGS exceeds the 0V or more positive values
 Plotting point when VGS=0Vand ID=0A
 The intersection between Shockley characteristics and linear characteristics
defined the Q-point of the MOSFET
 The problem is that how long does the transfer characteristics have to be
draw?
 We have to analyze the input loop parameter relationship.
 As RS become smaller, the linear characteristics will be in narrow slope
therefore needs to consider the extend of transfer characteristics for example
of voltage divider MOSFET
SDGGS
RSGSG
RIVV
VVV

 0
 The bigger values of VP the more positive values we should draw for
the transfer characteristics

 How to analyze dc analysis for the shown network?
 It is a …. Type network ,Find VG or VGS ,Draw the linear characteristics
 Draw the transfer characteristics
 Obtain VGSQ and IDQ from the graph intersection
1. Plot line for VGS = VG, ID = 0 and ID = VG/RS, VGS = 0
3. Where the line intersects the transfer curve is the Q-point.Use the ID at the Q-point to
solve for the other variables in the voltage-divider bias circuit. These are the same
calculations as used by a JFET circuit.

1. Plot line for VGS = VG, ID = 0 and ID = VG/RS, VGS = 0
3. Where the line intersects the transfer curve is the Q-point.
Use the ID at the Q-point to solve for the other variables in the voltage-
divider bias circuit. These are the same calculations as used by a JFET circuit.
61

E-MOSFET
Two things are worth noting about E-MOSFET. First, E-MOSFET operates only
in the enhancement mode and has no depletion mode. Secondly, the E-
MOSFET has no physical channel from source to drain because the substrate
extends completely to the SiO2 layer

(ii) When gate is made positive (i.e. VGS is positive) it attracts
free electrons into th p region. The free electrons combine with the
holes next to the SiO2 layer. If VGS is positive enough, all the holes
touching the SiO2 layer are filled and free electrons begin to flow
from the source to drain. The effect is the same as creating a thin
layer of n-type material (i.e. inducing a thin n-channel) adjacent to
the SiO2 layer. Thus the E-MOSFET is turned ON and drain current
starts flowing form the source to the drain.The minimum value of
VGS that turns the E-MOSFET ON is called threshold voltage [VGS
(th)].
(iii) When VGS is less than VGS (th), there is no induced channel
and the drain current ID is zero. When VGS is equal to VGS (th),
the E-MOSFET is turned ON and the induced channel conducts drain
current from the source to the drain. Beyond VGS (th), if the value
of VGS is increased, the newly formed channel becomes wider,
causing ID to increase. If the value of VGS decreases [not less than
VGS (th)], the channel becomes narrower and ID will decrease. This
fact is revealed by the transconductance
curve of n-channel E-MOSFET shown in Fig. 19.56. As you can see, ID
= 0 when VGS = 0. Therefore, the value of IDSS for the E-MOSFET is
zero. Note also that there is no drain current until VGS reaches
VGS (th).

IG =0A, therefore VRG = 0V
Therefore: VDS = VGS
Which makes
DDDDGS RIVV 
65

1. Plot the line using VGS = VDD, ID = 0 and ID = VDD / RD and VGS = 0
2. Plot the transfer curve using VGSTh , ID = 0 and VGS(on), ID(on); all given in the
specification sheet.
3. Where the line and the transfer curve intersect is the Q-Point.
4. Using the value of ID at the Q-point, solve for the other variables in the
bias
circuit.
66
 Find k using the datasheet or specification given;
ex: VGS(ON),VGS(TH)
 Plot transfer characteristics using the formula
ID=k(VGS – VT)2. Three point already defined that is ID(ON), VGS(ON) and
VGS(TH)
 Plot a point that is slightly greater than VGS
 Plot the linear characteristics (network bias line)
 The intersection defines the Q-point

Again plot the line and the transfer curve to find the Q-point.
Using the following equations:
21
DD2
G
RR
VR
V


)( DSDDDDS
SDGGS
RRIVV
RIVV


Input loop :
Output loop :
67
1. Plot the line using VGS = VG = (R2VDD)/(R1 + R2), ID =
0 and ID = VG/RS
and VGS = 0
2. Find k
3. Plot the transfer curve using VGSTh, ID = 0 and
VGS(on), ID(on); all given in the specification sheet.
4. Where the line and the transfer curve intersect is
the Q-Point.
5. Using the value of ID at the Q-point, solve for the
other variables in the bias circuit.

=
= -
-
=
-=
- + )(
=
= -
+
= - )( +
=
=
-
)( ++ -
=
=
68

=-
=
=
= -
= -
= -
=
+
-=
= - +( )
=
= -
=
=
+
-
69

For p-channel FETs the same calculations and graphs are used, except
that the voltage polarities and current directions are the opposite.
The graphs will be mirrors of the n-channel graphs.
70

Small Signal BJT Equivalent Circuit
The small-signal model can be used when the BJT is in the active
region. The small-signal active-region model for a CE circuit is shown
below:
iB re
iE
iC
iB
B C
E
re= 26mv
IE
 = IC / IB

• Coupling capacitor CC and Emitter bypass capacitor CE are replaced by short circuits.
• DC voltage supply is replaced with short circuits, which in this case is connected to
ground.
•D C Equivalent for the BJT Amplifier
R1IIR2=RB
Ro
All capacitors in the original amplifier circuit are replaced by open circuits,
disconnecting vI, RI, and R3 from the circuit and leaving RE intact. The the

100kΩ4.3kΩ
3
R
C
RR
30kΩ10kΩ
2
R
1
R
B
R


• By combining parallel resistors into equivalent RB and R, the equivalent AC
circuit above is constructed. Here, the transistor will be replaced by its
equivalent small-signal AC model (to be developed).
All externally connected capacitors are assumed as short circuited elements for
ac signal
1) Determine DC operating point and calculate small signal parameters
2) Draw the AC equivalent circuit of Amp.• DC Voltage sources are shorted to
ground • DC Current sources are open circuited
• Large capacitors are short circuits • Large inductors are open circuits
3) Use a Thevenin circuit (sometimes a Norton) where necessary. Ideally the
base should be a single resistor + a single source. Do not confuse this with the
DC Thevenin you did in step 1.
4) Replace transistor with small signal model
5) Simplify the circuit as much as necessary Steps to Analyze a Transistor Amplifier
6) Calculate the small signal parameters and gain etc

 OPAMP is a high gain differential amplifier which is used for
different operation like
addition,subastraction,integration,differentiation etc.and it is also
used for amplification that’s why it is known as operational
amplifier.it has basically five terminal,two input terminal,one
output terminal,two supply source positive voltage supply
source,negative voltage supply source

OPAMP terminals
• OPAMP has two input terminal that is inverting input
and non inverting input
• If input is applied to non inverting input terminal, then
output will be in-phase with input ‘so it is known as non
inverting input terminal
• If input is applied to inverting input terminal, then
output will be 180 degrees out of phase with input so it is
known as inverting input terminal
• If inputs are applied to both terminals, then output will
be proportional to difference between the two inputs
• Two DC power supplies (dual) are required
• Magnitudes of both may be same
• The other terminal of both power supplies are connected to
common ground
• All input and output voltages are measured with reference to
the common ground

Ideal Operational Amplifier characteristic
Operational amplifier (Op-amp) is made of many transistors,
diodes, resistors and capacitors in integrated circuit technology.
Ideal op-amp is characterized by:
Infinite input impedance
Infinite gain for differential input
Zero output impedance
Infinite frequency bandwidth

Op-amp are almost always used with a negative feedback:
Part of the output signal is returned to the input with negative sign
Feedback reduces the gain of op-amp
Since op-amp has large gain even small input produces large output,
thus for the limited output voltage (lest than VCC) the input voltage vx
must be very small.
Practically we set vx to zero when analyzing the op-amp circuits.
Inverting Amplifier
with vx =0 i1 = vin /R1
i2 = i1 and
vo = -i2 R2 = -vin R2 /R1
so
Av=vo /vin =-R2 /R1
i1
i2

Inverting Amplifier
Since vo = -i2 R2 = -vin R2 /R1
Then we see that the output voltage does not depend on the load
resistance and behaves as voltage source.
Thus the output impedance of the inverting amplifier is zero.
The input impedance is R1 as Zin=vin/i1=R1

Voltage Follower
=>
vo = v1(1+ R2 /R1)
vo = v1
Special case of noninverting amplifier is a voltage follower
so when R2=0
Since in the noninverting amplifier

Summing Amplifier
The output voltage in summing amplifier is
vo=-if*Rf since vi=0
if=iA+iB=vA/RA+vB/RB => vo=-(vA/RA+vB/RB)*Rf
For n inputs we will have
vo=- Rf *Si(vi/Ri)
+
vi
-
iA
iB
if

Summing Amplifier (Adder)
A
A
A
R
v
i 
B
B
B
R
v
i 
FBA iii 
F
o
F
R
v
i


F
o
B
B
A
A
R
v
R
v
R
v








B
F
B
A
F
Ao
R
R
v
R
R
vv

Difference Amplifier (Subtractor)

 The circuit is analyzed using superposition theorem
 Consider only v1 to be present; v2=0
Now derive expression for output voltage vo1
 Next consider only v2 to be present; v1=0
Derive expression for output voltage v02
 Actual output voltage vo = vo1+vo2

vx







2
1
1
R
R
vv F
xo 













231
31
1
1
R
R
RR
Rv
v F
o

2
22
R
R
vv F
o 
2
2
231
31
21
1
R
R
v
R
R
RR
Rv
vvv FF
ooo 













FR3R2R1Rif21  vv

 Integrator is a circuit whose output is proportional to
(negative) integral of the input signal with respect to
time
 Feedback is given through capacitor to inverting terminal
 Since same current flows through R and C,
dt
dv
C
R
v oin
 


t
0
ino dtvv
RC
1

 Differentiator is circuit whose output is proportional to (negative)
differential of input voltage with respect to time
 Input is given through capacitor, feedback given through resistor to inv
terminal
 Since current through R and C are same,
R
v
dt
dv
C oin

dt
dv
v in
o RC

 Feedback amplifier contains two component namely feedback
circuit and amplifier circuit.
 The purpose of feedback circuit is to return a fraction of the
output voltage to the input of the amplifier circuit.

Both negative feedback and positive feedback are used in amplifier
circuits.
Negative feedback returns part of the output to oppose the input,
whereas in positive feedback the feedback signal aids the input
signal.

Wien-Bridge Oscillator
- One type of sinusoidal feedback oscillator is the Wien-bridge oscillator.
- A fundamental part of the Wien-bridge oscillator is a lead-lag circuit
-

The response curve for the lead-lag circuit indicates that the output voltage
peaks at a frequency called the resonant frequency, .

The Phase-Shift Oscillator
- sinusoidal feedback oscillator called the phase-shift oscillator. Each of the
three RC circuits in the feedback loop can provide a maximum phase shift
approaching 90°.

Aec ppt2

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