This document outlines the design of a Universal Asynchronous Receiver/Transmitter (UART) module using Verilog HDL. It describes the project flow, introduction to UARTs, design of the baud rate generator, transmitter, receiver, and block diagram. It also includes the simulation results, RTL schematic, technology schematic, utilization reports, and power reports from synthesis and implementation. The design is verified through simulation and the document concludes with discussing future work of verification on FPGA and references related work on UART design.

1. CONTENTS
• Project Flow
• Introduction
• UART Design
• Baud Rate Generator
• Transmitter
• Receiver
• Block diagram of UART
• Simulation Result
• RTL Schematic
• Technology Schematic
• Reports
• Conclusion
• Future Work
• References

2. Project Flow
 Literature Survey.
 Design of Baud rate generator.
 Design of receiver and transmitter.
 Debugging of UART.
 Simulation.
 Synthesis.
 Verification.
 Implementation.

3. Introduction
 UART acronym for Universal Asynchronous
Receiver and Transmitter.
 Asynchronous Serial communication
protocol.
 Full Duplex communication.
 Used between the slow and the fast
peripheral devices.

4. Contd..
 Converts the bytes it gets from the computer
along parallel circuits to a single serial bit
stream for outbound transmission.
 For inbound transmission, converts the serial
bit stream to the bytes that the system
handles.
 Adds a parity bit after selection in outbound
transmissions, checks the parity of incoming
bytes (if selected) and rejects the parity bit.

5. UART Design
 A UART frame consists of 1 start bit, a number
of data bits, an optional parity bit and 1, 1.5, or 2
stop bits.
 Signal is 1 (high voltage) when the system is
idle.
 Start bit is 0 and stop bits are 1.
 LSB is first transmitted or received.

6. Contd..
 UART is composed of a Baud Rate Generator
(BRG), a receiver module, and a transmitter
module
 Designed by using Modular design approach.

7. Baud Rate Generator
 Baud rate: The number of bits transmitted per
second. frequently used baud rate: 9600,
19,200.
 n=
𝑓𝑐𝑙𝑘
𝐵𝑚𝑎𝑥×𝐶×2
Where
fclk: system clock Frequency
C: the number of samples per bit cell
Brmax: the maximum baud rate frequency

8. Contd..
 Multiplexer based designing of baud rate
generator is used.

9. RTL Code of Baud Rate
generator
module clk_div(input clk,rst,
output q)
reg [2:0]q1;
always@(posedge clk)
begin if(!rst)
q1<=3'b001;
else
q1<={q1[0],q1[2:1]};
end
assign q=q1[0];
endmodule
module counter_8(input clk,rst,
output reg [7:0]q);
always@(posedge clk)
begin
if(!rst)
q<=8'd0;
else
q<=q+1;
end
endmodule
Clock divide by n Divide by 256

10. Contd..
module mux_8(input [7:0]d,
input [2:0]sel,
output reg y);
always@(d,sel)
begin case(sel)
3'b000:y=d[0];
3'b001:y=d[1];
3'b010:y=d[2];
3'b011:y=d[3];
3'b100:y=d[4];
3'b101:y=d[5];
3'b110:y=d[6];
3'b111:y=d[7];
endcase
end
endmodule
module divide_by_8(input clk,rst,
output q);
reg [2:0]count;
always@(posedge clk,negedge
rst)
begin
if(!rst)
count<=3'd0;
else
count<=count+1;
end
assign q=count[2];
endmodule
Multiplexer Divide by 8

11. Block Diagram of Transmitter
 Logic diagram of the transmitter of a UART.
TDR
Transmitter Control
TE
Parity generator
1 P 0
1
TxD
TxC
Data Bus

12. SM of Transmitter
bct=10

13. Block Diagram of Receiver
 Logic diagram of the receiver of UART
FE OE PE RF
RDR
1 P RSR 0 Receiver Control
DATA BUS
RxD RxC
RcvS
R

14. SM of Receiver

15. Block Diagram

16. SIMULATION RESULTS
 Simulation result of baud
rate generator

17. Contd..
 Simulation result of UART

18. RTL SCHEMATIC

19. Technology Schematic

20. POST SYNTHESIS UTILIZATION
REPORT

21. POST IMPLEMENTATION
UTILIZATION REPORT

22. Power report
 There are 2 power report.
• Post synthesis
• Post route
 Two modes of power estimation
• Vector based
• Vector less

23. POST SYNTHESIS POWER
REPORT

24. POST IMPLEMENTATION
POWER REPORT

25. Conclusion
 UART Module is designed by using Verilog
HDL.
 Design is simulated and verified with the help
of output waveform in Xilinx Vivado HLS.
 The design code if fully synthesizable and has
no latch.

26. Future Work
 Verification of UART.
 Implementation on FPGA.

27. REFERENCES
 U. Nanda and S. K. Pattnaik, “Universal asynchronous
receiver and transmitter (uart),” in Advanced Computing
and Communication Systems (ICACCS), 2016 3rd
International Conference on, vol. 1. IEEE, 2016,pp. 1–5.
 Y.-y. Fang and X.-j. Chen, “Design and simulation of uart
serial communication module based on vhdl,” in Intelligent
Systems and Applications (ISA), 2011 3rd International
Workshop on. IEEE, 2011, pp. 1–4.
 G. B. Wakhle, I. Aggarwal, and S. Gaba, “Synthesis and
implementation of uart using vhdl codes,” in Computer,
Consumer and Control (IS3C), 2012 International
Symposium on. IEEE, 2012, pp. 1–3.
 Y. Wang, and K. Song, “A new approach to realize UART,”
Int’l Conf. on Elect. and Mech. Eng. and IT (EMEIT 2011),
Harbin, Heilongjiang, China, Aug. 2011.