Course material

1. Answer: Introduction Low-power gadgets have gained a lot of attention
Answer:
Introduction
Low-power gadgets have gained a lot of attention in recent years as the need for mobile
computing has increased. Beginning with the advent of electronic wristwatches and
handheld calculators, mobile technology has progressed to today's linked devices and the
"internet of things," which are becoming increasingly widespread in our daily lives. Nodes
for the internet might one day be found in everyday objects including food, transportation,
and home appliances, to mention just a few possibilities. Due of these advances, there is an
increased need for research into ultra-low-power nano-electronic devices that will enable
this technology. For decades after the first integrated circuit was invented in 1958, there
has been a steady increase in the density and speed of transistors in integrated circuits
based on Moore's law. Due to Dennard scaling's ability to reduce capacitance and drive
voltage, this was achievable during the first 40 years, enabling integrated circuits to ramp
up their operating frequency in order to improve performance. This approach has to be
modified to take into account the growing worry about OFF current in recent years. A CMOS
circuit's current determines the amount of power it consumes. In the early days of
Integrated Circuit Research, scaling VDD and Ctot to reduce power dissipation was possible.
When the threshold voltage was lowered to less than 300 mV, the OFF current increased
significantly, making this impossible. In a conventional MOSFET, the switching mechanism
depends on a temperature barrier, which means that there is a thermodynamic limitation.
According to the Fermi distribution, the rate at which the transistor current may vary is
around 60 mV/decade at room temperature (kBTln(10)/q where kB is the Boltzmann's
constant and T is the temperature), which is the lowest limit of transistor current change.
This phenomenon is also known as transistor subthreshold swing (SS). In this case, the
highest ON/OFF ratio for the 300-mV threshold voltage is 105, resulting in a threshold
voltage of 300 mV. Short channel effects, which enhance the subthreshold swing, must be
addressed when devices are scaled up. One of the primary causes of these issues is the
deterioration of electrostatics that happens with the narrowing of channel sizes.
The clock frequency is indicated by this value, where an is the average switching activity,
VDD is the supply voltage, ISC is the short-circuit current between the supply voltage rails,
and IOF F is an indication that the transistor is not operational.

2. Figure 1; This graph depicts current trends in the scaling of integrated circuits (ICs).
This law claims that the number of transistors per die has doubled every 24 months for the
previous 40 years, according to Moore's Law. As a result of the collapse of Dennard scaling,
which allowed clock frequencies to be enhanced every generation, the frequency of
operation has decreased during the last decade. This can be seen in the power dissipation
plot in the same image, which demonstrates that the heat has reached a point where heat
sinks are no longer able to effectively remove it (Andrews., et al, 2020). Scaled nodes are
affected by transistor OFF current, which is why this is the case. Consequently, in the early
twenty-first century, the number of processor cores was raised in order to preserve
performance gains. When the channel is long and the source and drain capacitances are
relatively minor, the gate capacitance controls the barrier only, as was the case in the
preceding example. A larger off-state OFF current is now possible due to a shorter channel
length and the source and drain electrodes' significant influence on barrier height
(increasing barrier height in off state). Short-channel effects such as DIBL (Drain Induced
Barrier Lowering) and other short-channel effects are exacerbated as a consequence of this.
Tunneling current may be inhibited by utilizing high-K dielectrics in order to improve the
control of gate voltages in semiconductor devices. Direct quantum mechanical tunneling
between the two electrodes in the off state may also occur when the distance between the
source and drain is reduced, resulting in an increase in the OFF current. Because of this,
transistor design must be rethought in order to handle scalability difficulties. The
thermodynamic barrier limit may be overcome by two different approaches: 1) improving
electrostatics by changing the geometry or material of the channel, or 2) using tunnel
transistors and negative capacitance to overcome the barrier.
Figure 2; A schematic illustration of the capacitive top of the barrier model used to describe
the functioning of a MOSFET.
The gate capacitance CG, the drain capacitance CD, the source capacitance CS, and finally the
quantum capacitance arising from the charging of the semiconductor channel must be taken
into account in order to manage the electrostatics of a device.
E2V Process Parameters
An electrode (e.g., a gate or a diode) is connected to the substrate through the buried
channel (BC) (ss). ch. is the maximum capacity of the (buried) channel When there is no
stored signal charge, this is the scenario (V). The voltage in the underlying channel is
connected to the electrode voltage via the "channel parameter" ch. This includes the oxide
capacitance per unit area and any fixed charge in the oxide. The factor S of a lightly doped
substrate is 1, whereas the factor S of a substantially doped substrate is zero. As the
electrode voltage decreases, the voltage at the insulator-semiconductor (silicon dioxide-Si)
contact equals that of the substrate. The final distribution is shown in the left schematic of

3. Fig. 1. Ch gets "pinched" if the electrode voltage is decreased even more. The gate voltage is
Vgssp and the maximum pinned value is chp. To determine the values of ch0, chp, and
Vgssp, test transistors may be put around the perimeter of the device (and benchmarking
device simulations).
Figure 3; A CCD pixel in Inverted Mode Operation has an insulating oxide (gate dielectric),
buried channel (BC) and substrate profile (IMO). Is the p-n junction. To compare realistic
and step (box) doping profiles, go here. net dopant density vs. device depth. The backdrop is
colored according to the ATLAS models' material structure: conductor (polysilicon
electrodes, depth 0-0.5 m), insulator (SiO2, depth 0.5-0.63 m), and semiconductor (Si, depth
0.63-16 m). Because doping density is absolute, the p-n junction separates p-type ions from
n-type ions.
Low-Power Electronic Devices On Transition Metal Dichalcogenides.
Radisavljevic created the first single-layer MoS2 transistor back in 2011, and it was able to
display an ON/OFF ratio of up to 108 while maintaining an incredibly low off current. By
exfoliating the monolayer of MoS2 (1.8 eV), the material blocks both direct S-D tunneling
and band–to–band tunneling when the material is exfoliated, allowing this to be done. TMD
materials that can be exfoliated into a few layers and used in the material channel in a
similar fashion have gained increased attention since this discovery. To demonstrate
transistor functioning, several TMDs, such as MoSe2, WS2, and WSe2, were utilized. They
can be utilized for optoelectronics, photovoltaics, and photodetectors since they have a
straight band gap in their monolayer phase (Andrews., et al, 2020). This implies that they
might be employed in high performance flexible electronics in the future. Although the
majority of transistors have a high ON/OFF ratio due to the huge band gap in their
monolayer and few-layer crystalline phases, a considerable contact resistance has been
found that limits the effective mobility, therefore restricting the transistor's ON current and
drivability. It was found by K. Ganapathi that the ON/OFF ratio of scaled monolayer MoS2
could be increased to 1010 with an SS of less than 60 mV/decade and low dielectric
breakdown voltage using an effective mass approach.
Figure 4; Single-layer MoS2 transistors developed by Radisavljevic and his colleagues along
with their corresponding transfer characteristics for various drain biases and back-gate
biases.
The channel has a thickness of around 0.65 nm, the thickness of a single layer of MoS2. In
terms of transmission characteristics, the ON/OFF ratio may reach as high as 108. Changes
in TMD electronic structure from a single layer to several layer result in changes in the
conduction band curvature as well as relative positions of valleys. This all contributes to
energy transport. A transistor's performance is influenced by the density of states and
velocity of particles that contribute to transport (Yazyev & Kis, 2015). As the number of
layers being altered increased, there was also an electrostatic risk that needed to be

4. handled. As the number of layers rises, so does the number of modes that might possibly
contribute to current, but as channel thickness increases, so does the gate control.
Quantum Transport Simulator (QTS) And TCAD
Since transistor technology has advanced and the integrated circuit (I.C.) industry has
grown into a major industry, understanding the working principles of the various
components of an I.C has become increasingly important in order to optimize the I.C design
to provide the best performance at the lowest possible cost. As a result, the pace of
innovation in the industry can be accelerated by using TCAD to investigate new materials
and device geometries. There are three main factors to keep in mind while modeling an
I.C.'s performance: Finally, the circuit simulation is the result of a three-step procedure.
Modeling And Simulation Of The Manufacturing Process
The semiconductor process simulation approach is used to model the production of
semiconductor devices. Bottom-up TCAD flow often begins with simulation of transistor
manufacturing before device properties are retrieved using a simulator for TCAD devices.
Complex and super-scaled devices have often lacked process modeling, despite significant
advances in device simulation. Process simulations are created after each step of the
transistor's manufacturing process has been completed in order to better understand how
the final product will perform. An example of a Sentaurus Process-based representation of a
stress-engineered FINFET is shown in the diagram below. Processes like ion doping,
annealing to activate dopants and allow them to diffuse, etching and deposition can all be
included in a process flow. An important goal of process simulation is to look at relative
trends to help with device production. Two of the most commonly used process simulators
in the semiconductor industry are the Synopsys Sentaurus Process and the SILVACO
ATHENA/VICTORY Process. In addition to predicting active substitutional dopants and their
doping profiles, process modeling must also take into account the interaction between
implantation damage and the dopant. It's also becoming more common to use atomistic
simulation tools and ab initio approaches to simulate process flow with fewer parameters,
which could lead to the creation of more physical models. Device simulation follows process
simulation in order to characterize the transistor's electrical performance after the shape
and doping profiles have been established.
Figure 5; Steps in the MOSFET process flow for the stress-engineered FinFET
In order to simulate the process flow described above, Sentaurus was used to run the Fin
patterning, the STI (Shallow Trench Isolation) formation, the Polygate definition, the Spacer
deposition and doped S/D patterning, and finally the epitaxial growth of the doped S/D.
Device Simulation

5. As soon as a device has been designed or an entirely new one has been thought up, it is
necessary to conduct extensive simulations in order to predict performance and establish
design criteria. Due to the ever-increasing complexity of semiconductor device fabrication,
and the prohibitively high cost of semiconductor device fabrication, device simulation has
become an increasingly important tool for predicting performance trends. Condensed
matter physics was a major force behind the invention of the first transistor and it remains
so today (Mendes., et al, 2018). The drift-diffusion equations, which were developed to
describe charge transport, have been used to simulate device behavior in a semi-classical
manner. In this formalism, electrons and holes were considered to be particles that moved
through a device in response to an electric field and the diffusion of other matter.
rEc(r, t) represents the electric field-induced drift, while Fs represents the diffusive
transport component (r, t). Ec(r, t) is the bottom of the conduction band at r, and hk is the
momentum of the particle at that point in time. I can use MonteCarlo methods or a
probability function to solve the above equation, which leads us to the Boltzmann Transport
Equation.
The probability distribution function (f(r, k, t)) and the electric field (E) indicate electron
scattering, where Cf represents the scattering consequences. Under equilibrium, the Fermi
distribution is f; in non-equilibrium situations, however, the BTE must be solved in order to
get the distribution function. Oddly, the Boltzmann equation's first moment of the
distribution function gives rise to the drift-diffusion equation, which is the first moment of
the distribution function. The equations provided above were acceptable for simulating
devices with weak electric fields in the conducting channel (Feng., et al, 2014). The drift
calculations broke down when the devices were scaled up to 104V/cm, since the electrons'
velocity exceeded their saturation velocity, resulting in the overshoot. This finding led to the
development of hydrodynamic equations to depict kinetic energy-dependent mobility,
rather than field-dependent mobility. These two hypotheses do not stand up to scrutiny
when devices reach their physical limits and electron correlation becomes so significant
that quantum transport formalism must be invented to account for the wave nature of
electrons. TOB (Top-of-the-Barrier) model, which is a colloquialism for ballistic transport,
before quantum transport theory. It's fortunate that the channel is small enough that no
scattering events are likely to take place during its route. Calculating the average injection
or thermal velocity and charge density contributions from both the source and drain are
prerequisites to using this theory. Most materials' bandstructure and electrochemical
potential at their contacts may be used to estimate these quantities, and it is via this method
that the wave description of electrons and holes is first presented.
Where DOS is the density of states at the top of the barrier and EF is the Fermi potential at
the source and drain, the density of states at the top of the barrier is 1. The Non-Equilibrium
Green's Function formalism (NEGF) was subsequently employed to calculate the electron
and hole correlation over the whole device, resulting in a quantum description of charge
transport. Finally, the barrier equations at the very top of the page are simplified to

6. When using the NEGF equations, the transmission or mode density T(E) may be calculated.
T(E) is the transmission density, whereas LDOS(E) is the local density of states. Further
explanations of the NEGF formalism will be provided at that time. When quantum transport
equations or semi-classical equations are utilized to generate transfer characteristics,
compact models may be built that can more accurately explain transistor behavior in a
circuit for circuit simulation rather than computationally demanding device simulation.
Circuit Simulation
After verifying circuit designs and forecasting how they would behave, circuit simulation is
the highest level in the semiconductor device modeling hierarchy. The industry standard for
circuit simulation, SPICE (Simulation Program with Integrated Circuit Emphasis), is now the
most extensively used tool for this purpose. SPICE was born out of the CANCER (Computer
Analysis of Nonlinear Circuits, Excluding Radiation) program at the University of California,
Berkeley. SPICE and later versions contain a variety of semiconductor device models and
analytical compact models. Analytical compact models are built using device simulations.
An important objective of circuit simulation is to accurately predict the behavior and reduce
design and analysis time for large integrated circuits as much as feasible. A wide range of
activities may be performed using circuit simulations, including alternating current
analysis, direct current quiescent point analysis, noise analysis, and transient analysis..
The Characteristics And Synthesis Of MOS2
It is necessary for a material to have a bandgap between its conduction and valence bands
in order for it to be categorized as a semiconductor; that is, there must be a difference in
energy between when the material conducts electricity and when it does not. A total of
eighteen persons have attained this milestone in their lives. Transistors and other switching
devices may be able to use MoS2 as a semiconductor due to its wide bandgap. the ninth
(nine). In the bulk, MoS2 has a 1.2 eV indirect gap, but when it is thinned down to
monolayer thickness, the direct gap rises to roughly 1.9 eV. Because electrons in MoS2 are
trapped in two dimensions, I believe quantum confinement at monolayer thickness caused
the bandgap shift. Ultrathin transistors are being developed using monolayer MoS2, which
has two dimensions and a direct band gap, as the primary focus of present research. To
make monolayer MoS2, one typical technique is mechanical exfoliation, which involves
peeling apart monolayers of MoS2 using Scotch tape 9. MoS2 has been synthesized using
chemical vapor deposition (CVD) 12 instead, since this procedure cannot be scaled up for
commercial use. Even though the Scotch-tape technique can only build micro-scale
monolayers of monolayer MoS2, chemical procedures such as CVD can produce full
monolayer MoS2 wafers at industrial scale (as opposed to the Scotch-tape method). It's the
12th grade, and here is when things start to get fancy. For microelectronic circuits,
monolayer MoS2 must be transferred to a conducting substrate such as Si/SiO2 since MoS2
cannot be generated on an insulating substrate such as sapphire. Mechanically exfoliated

7. MoS2 and chemically produced monolayer MoS2 share structural similarities, according to a
variety of characterization methods. When it comes to Raman fingerprints, which show the
molecular structure's vibrational modes in the molecular structure, they are similar. Due to
structural similarity, transistors made from chemically synthesized MoS2 and those made
from mechanically exfoliated MoS2 exhibit electrical characteristics that are almost
identical. Because of this, I conclude that chemical methods can produce monolayer MoS2
transistors on a large scale.
Analysis And Synthesis Of 2D Non-Structural Elements
In the future, semiconductor nanoparticles may be used in photonics and optoelectronics
systems with varying properties based on their size and shape. Nanocrystals made from
group IV elements are one of the fastest-growing scientific topics in the world right now.
These honeycomb-like nanocrystals are formed of carbon and are half-dimensional (2D)
(such as graphene). Second, MoS2 is a newly discovered transition-metal dichalcogenide
semiconductor. MoS2 has a better bandgap than either group IV semiconductors or
graphene in some applications, according to some simulations. Nanoscale MoS2 has 100%
oxidation resistance in the presence of water, making it more durable for chip production
than group IV Nano sheets (NS). It has been anticipated and experimentally demonstrated
that fullerene-like (MoS2 NS) structures exist. They're significant because of the unique
traits that set them apart. Polyhedral closed-caged NS is currently understood to be more
thermodynamically stable than isolated lamellar basal sheets. Because of their potential
applications in micro lubrication oil processing, photocatalysis, and photodetector
applications, these MoS2 NS have recently received a lot of attention Using MoS2 in a two-
dimensional ultrathin atomic layer structure demonstrates a number of unique properties.
Its unique properties make two-dimensional MoS2 NS especially well-suited for
heterogeneous catalysis, hydrogen separation, lithium-magnesium ion batteries, and a wide
range of biological applications. 2D MoS2NS is used in a broad range of electrical and
optoelectronic devices because of its promising photoelectric capabilities, which are
determined by the physical layer thickness of the material. The large direct band gap of 1.8
eV and low mobility of single-layer MoS2 justified its use in the manufacturing of a single-
layer transistor. In optoelectronics, this thesis laid the foundations for the usage of MoS2.
Additionally, for MoS2-based transistor applications, it is feasible to achieve adequate
electron mobility. MoS2 was also mentioned as a possible material for solar cell applications
in the literature. 2D-MoS2 and its nanoribbons were studied theoretically. The properties
and applications of 2D-MoS2 have been extensively studied. Nanoelectronic applications of
2D MoS2 NS are shown in these two recent investigations. MoS2 NS approaches involve
volatile chemicals like H2S and H2 that are difficult to regulate or store in large amounts.
Another approach that might be used is pulsed laser ablation (PLA). It is feasible to create a
wide variety of noble and semiconductor nanocrystals with a wide variety of structural
morphologies using specialized scientific equipment for laser-matter interaction.
As far as creating colloidal, exceptionally clear, and agent-free NS is concerned, PLA has

8. much more flexibility than any other method, particularly when utilized in liquids. This
process does not use chemical precursors to make PLA. Laser ablation of 3D MoS2 NS,
which seems to be comparable to fullerene in water, has been studied extensively. One
study found that laser-ablated 3D MoS2 NS has properties similar to fullerenes as well as
good solubility and biocompatibility, making it useful in a range of biological applications,
including wound healing. According to the scientists, organic liquid MoS2 NS morphologies
of varied sizes and forms may be generated in a single process (Rai., et al, 2018). To create
colloidal two and three-dimensional MoS2 nanostructures, PLA is used to synthesize 2H-
MoS2 powder. The thickness of the layers in almost all of PLA's MoS2NS products ranges
from micrometers to nanometers (nanometer). a three-dimensionally structured inorganic
polyhedral fullerene The rest of my research is focused on MoS2 NS. Ab initio calculations
were also used to investigate the possible causes of distinct morphologies. To understand
more about MoS2 NS' composition, size, thickness, chemical composition, and optical
characteristics, I employed optical microscopy, electron microscopy, transmission electron
microscopy, X-ray diffraction, Raman spectroscopy, and UV-vis-near-infrared (NIR)
absorption studies. X-ray diffraction research led to the discovery of the hexagonal
crystalline structure of MoS2 NS. Spectroscopy verified the crystallization of MoS2. The
near-infrared to ultraviolet range of Raman Colloidal MoS2 NS's absorption edge tailoring is
vast.
Future Research
The manufacturing process for MoS2 transistors must solve a number of issues in order to
realize their full potential and make them appropriate for use in electronic devices. Put
something in front of someone first and foremost, and you'll get the idea. On top of the MoS2
channel, one problem arises due to the dielectric layer (HfO2) developing in a non-
conformal island pattern. MoS2's mobility can be greatly improved if the conformal
deposition of ultra-thin HfO2 is carried out precisely and consistently. a score of 7 With no
direct deposition option, surface functionalization processes such pre-treating the surface
of MoS2 in order to allow for conformal dielectric layer formation must be used (Feng., et al,
2014). When an oxygen plasma treatment is used to create a layer of Mo-oxide on top of the
MoS2, the surface may then be functionalized to allow for the conformal formation of HfO2.
In contrast, the oxygen plasma treatment degrades the electrical properties of MoS2, which,
in turn, has a negative impact on the device's efficiency. Oxygen plasma treatment results in
functionalized surfaces that may be studied in more detail in future studies. Mo-oxide bonds
may be seen without inflicting major structural damage to the MoS2 crystal structure by
employing this technique. Some other concerns that must be addressed include high contact
resistance between source/drain and the MoS2 channel, which must be solved. Electrons at
the interface must overcome a jump in potential known as a Schottky barrier in order to
make an Ohmic contact in the optimal candidate metal. As far as Schottky barriers go, it
seems that the metal Mo is the best metal contact because of its relatively low barrier of
only 0.1 eV. There are several approaches that may drastically reduce the overall amount of
contact resistance, such as heating and cooling the device after metal deposition. The high

9. contact resistance at the metal-semiconductor interface in monolayer and few-layer MoS2
will be investigated further in future studies.
Conclusion
MoS2's large bandgap when formed as a monolayer makes it an appealing choice for usage
as a semiconductor in future electronics. In this research I focus on chemically synthesizing
MoS2, which might be scaled up for the production of MoS2 transistors in industry. Flexible
electronic circuitry has been built using MoS2 transistors because of their promising
electrical qualities even when bent. Non-conformal deposition of the dielectric layer and
high contact resistance are the most major production challenges, despite the fact that
many more have been discovered. Schottky theory and density functional theory research
will need to be done in the near future to help better understand the physics at the metal-
semiconductor interface in order to minimize the high contact resistance. It is essential that
research be devoted to this purpose in order to increase the performance of devices.
Silicon's performance limit is quickly approaching in current devices.
References
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device performance in MoS2 transistors using a 2D semiconductor interlayer. ACS
nano, 14(5), 6232-6241.
Feng, Q., Zhu, Y., Hong, J., Zhang, M., Duan, W., Mao, N., ... & Xie, L. (2014). Growth of
large?area 2D MoS2 (1?x) Se2x semiconductor alloys. Advanced Materials, 26(17), 2648-
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Mendes, J. B. S., Aparecido-Ferreira, A., Holanda, J., Azevedo, A., & Rezende, S. M. (2018).
Efficient spin to charge current conversion in the 2D semiconductor MoS2 by spin pumping
from yttrium iron garnet. Applied Physics Letters, 112(24), 242407.
Rai, A., Movva, H. C., Roy, A., Taneja, D., Chowdhury, S., & Banerjee, S. K. (2018). Progress in
contact, doping and mobility engineering of MoS2: an atomically thin 2D
semiconductor. Crystals, 8(8), 316.
Yazyev, O. V., & Kis, A. (2015). MoS2 and semiconductors in the flatland. Materials
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