This document discusses power reduction techniques for logic gates operating in the subthreshold region. It analyzes dual-threshold voltage techniques like sleep, sleepy stack, and dual sleep methods for reducing standby power dissipation in dual mode logic (DML) gates. These power gating techniques are also applied to full adder circuit design to reduce power consumption. Simulation results show the dual sleep method reduces power the most for NAND, NOR and pseudo NMOS logic gates compared to other techniques. For full adders, the sleep method reduces power the most. In conclusion, subthreshold DML gates achieve speed improvement compared to CMOS at the cost of more power, while different power gating methods applied to DML further reduce power dissip
Design of 64 bit SRAM using Lector Technique for Low Leakage Power with Read ...IOSRJVSP
: In complementary metal oxide semiconductor (CMOS) the power dissipation predominantly comprises of dynamic as well as static power. Prior to introduction of “Deep submicron technologies” it is observed that in case of technology process with feature size larger than 1micro meter, the consumption of dynamic power out of the overall power consumption of any circuit is more than 90%,while that of static power is negligible. But in the present deep submicron technologies in order to, reduce the dynamic power consumption in VLSI circuits, the power supply is being scaled down, keeping in view the principle that the dynamic power dissipated is directly proportional to the square of the supply voltage (Vdd).The threshold voltage also needs to be reduced since the supply voltage is scaled down. Overcoming the inherent limitations in the existing method for leakage power reduction, The Lector (Leakage controlled transistor) technique which works efficiently both in active and idle states of the circuit and results in better leakage power reduction is now proposed. The proposed system presents the analysis of power on “64-bit SRAM array using leakage controlled transistor technique
A Single-Phase Clock Multiband Low-Power Flexible Dividerijsrd.com
In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers The frequency synthesizer was implemented using a charge-pump based phase-locked loop with a tri-state phase/frequency detector and a programmable pulse-swallow frequency divider. Since the required frequency of operation can be as high as 1.4GHz, the speed of the digital logic used in the frequency divider is a critical design factor. A custom library of digital logic gates was designed using MOS current-mode logic (MCML). These gates were designed to operate at frequencies up to 1.4GHz. This report outlines the design of the phase/frequency detector and the programmable pulse-swallow frequency divider. The design, layout, and simulation of the MCML logic family are also presented.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For Hig...IOSRJVSP
This paper presents a new topology to implement MOS current mod logic (MCML) tri-state buffers. In Mos current mode logic (MCML) current section is improves the performance and maintains low power of the circuit. MCML circuits contains true differential operation by which provides the feature of low noise level generation and static power dissipation. So the amount of current drawn from the power supply does not depends on the switching activity. Due to this MOS current mode logic (MCML) circuits have been useful for developing analog and mixed signal IC’s. The implementing of MCML D-flip flop and Frequency divider done by using MCML D-latches. The proposed MCML D-latch consumes less power as it makes use of low power tri-state buffers. Which promotes power saving due to reduction in the overall current flow in the proposed D flip flop topology is verified though Cadence GPDK-180nM CMOS technology parameters.
VHDL Implementation of Flexible Multiband Dividerijsrd.com
In this paper an efficient multiband flexible divider for Bluetooth, Zigbee and other wireless standards is proposed based on pulse swallow topology and is implemented using Xilinx ISE 13.2 and modalism 6.4c.It consist of a propose wideband multimodulus 32/33/47/48 prescaler, swallow s-counter ,p-counter. As a modification I have implemented a modified multiband flexible divider by combining p and s counters together and by using a modified 2/3 prescaler. Compared to the proposed system modified one will reduce the circuit complexity, power consumption, gate counts etc.
Design of 64 bit SRAM using Lector Technique for Low Leakage Power with Read ...IOSRJVSP
: In complementary metal oxide semiconductor (CMOS) the power dissipation predominantly comprises of dynamic as well as static power. Prior to introduction of “Deep submicron technologies” it is observed that in case of technology process with feature size larger than 1micro meter, the consumption of dynamic power out of the overall power consumption of any circuit is more than 90%,while that of static power is negligible. But in the present deep submicron technologies in order to, reduce the dynamic power consumption in VLSI circuits, the power supply is being scaled down, keeping in view the principle that the dynamic power dissipated is directly proportional to the square of the supply voltage (Vdd).The threshold voltage also needs to be reduced since the supply voltage is scaled down. Overcoming the inherent limitations in the existing method for leakage power reduction, The Lector (Leakage controlled transistor) technique which works efficiently both in active and idle states of the circuit and results in better leakage power reduction is now proposed. The proposed system presents the analysis of power on “64-bit SRAM array using leakage controlled transistor technique
A Single-Phase Clock Multiband Low-Power Flexible Dividerijsrd.com
In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers The frequency synthesizer was implemented using a charge-pump based phase-locked loop with a tri-state phase/frequency detector and a programmable pulse-swallow frequency divider. Since the required frequency of operation can be as high as 1.4GHz, the speed of the digital logic used in the frequency divider is a critical design factor. A custom library of digital logic gates was designed using MOS current-mode logic (MCML). These gates were designed to operate at frequencies up to 1.4GHz. This report outlines the design of the phase/frequency detector and the programmable pulse-swallow frequency divider. The design, layout, and simulation of the MCML logic family are also presented.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For Hig...IOSRJVSP
This paper presents a new topology to implement MOS current mod logic (MCML) tri-state buffers. In Mos current mode logic (MCML) current section is improves the performance and maintains low power of the circuit. MCML circuits contains true differential operation by which provides the feature of low noise level generation and static power dissipation. So the amount of current drawn from the power supply does not depends on the switching activity. Due to this MOS current mode logic (MCML) circuits have been useful for developing analog and mixed signal IC’s. The implementing of MCML D-flip flop and Frequency divider done by using MCML D-latches. The proposed MCML D-latch consumes less power as it makes use of low power tri-state buffers. Which promotes power saving due to reduction in the overall current flow in the proposed D flip flop topology is verified though Cadence GPDK-180nM CMOS technology parameters.
VHDL Implementation of Flexible Multiband Dividerijsrd.com
In this paper an efficient multiband flexible divider for Bluetooth, Zigbee and other wireless standards is proposed based on pulse swallow topology and is implemented using Xilinx ISE 13.2 and modalism 6.4c.It consist of a propose wideband multimodulus 32/33/47/48 prescaler, swallow s-counter ,p-counter. As a modification I have implemented a modified multiband flexible divider by combining p and s counters together and by using a modified 2/3 prescaler. Compared to the proposed system modified one will reduce the circuit complexity, power consumption, gate counts etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Analysis of Sequential Elements for Low Power Clocking System with...IJERA Editor
This paper proposed the design of sequential elements for low power clocking system with low low power techniques for saving the power. Power consumption is a major bottleneck of system performance and is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flop-flops. In this paper, various design techniques for a low power clocking system are surveyed. Among them is an effective way to reduce capacity of the clock load by minimizing number of clocked transistors. To approach this, proposed a novel clocked pair shared flip-flop which reduces the number of local clocked transistors by approximately 40%. A 24% reduction of clock driving power is achieved. In addition, low swing and double edge clocking, can be easily incorporated into the new flip-flop to build clocking systems. As the feature size becomes smaller, shorter channel lengths result in increased sub-threshold leakage current through a transistor when it is off. Dual sleep and sleepy stack methods are proposed to avoid static power consumption; the flip flops are simulated using HSPICE.
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...IJERA Editor
According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.
A novel approach for leakage power reduction techniques in 65nm technologiesVLSICS Design
The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there
by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is
enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over
the world today, the battery-powered electronic system forms the backbone. To maximize the battery life,
the tremendous computational capacity of portable devices such as notebook computers, personal
communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has
to be realized with very low power requirements. Leakage power consumption is one of the major technical
problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power
minimization techniques have been presented in this paper a novel Leakage reduction technique is
developed in Cadence virtuoso in 65nm regim with the combination of stack with sleepy keeper approach
with Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%,
Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24%
with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.
1x2 Digital Optoelectronic Switch using MZI structure and studying the Effect...ijsrd.com
The electro optic switch has wide application in optical network due to capability of route the light path from one port to the desired port. In this paper, we propose a 1x2 digital optoelectronics switch based on mach-zehnder interferometer structure on a single titanium diffuse lithium niobate substrate. The design is simulate on BPM-cad simulator for switch analysis and study the effect of bipolar voltage 0v to ± 5.75v applied at 1st and center electrode region for switching. A short study of wavelength dependent switch for first optical window 8.5 µm and third optical window 1.55 µm has been simulated without use of voltage with changing titanium stripe thickness to 0.07µm.
This paper investigates about the possibility to reduce power consumption in Neural Network using approximated computing techniques. Authors compare a traditional fixed-point neuron with an approximated neuron composed of approximated multipliers and adder. Experiments show that in the proposed case of study (a wine classifier) the approximated neuron allows to save up to the 43% of the area, a power consumption saving of 35% and an improvement in the maximum clock frequency of 20%.
Minimization of redundant internal voltage swing in cmos full addereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Design of very large scale analog integrated circuit (analog VLSI) is very much complex and requires
much compromising nature to achieve application specific objective. With maximizing the efforts to reduce
power consumption and to reduce W/L ratio, the analog integrated circuit industry is constantly
developing smaller power supplies. Now days, challenges of analog integrated circuit designer are to
make block of small power supplies with little or no reduction in performance. The CMOS OTA is
designed in 25.5nm CMOS technology with 1.0V power supply to observe the configurations. In design of
CMOS OTA TANNER EDA TOOL is used. Coding and simulation is done in T-Spice and layout is
prepared in L-Edit. D.C analysis, A.C analysis, slew rate and analysis of transient response have been
done in T-Spice. Waveforms are observed in W-Edit.
A high speed low power consumption d flip flop for high speed phase frequency...IAEME Publication
Phase Frequency Detector (PFD) and Frequency divider are indispensable modules of PLL,
which uses D flip-flop as an integral part. This paper focus on design of High-Speed, Low Power
Consumption D Flip-Flop for High Speed Phase Frequency Detector and Frequency divider. The
designed Frequency divider has been used in the divider counter of the phase locked loop. A divide
counter is required in the feedback loop to scales down the frequency of the VCO output signal. The
conventional and proposed D-Flip flop has been designed in UMC 180nm CMOS Technology with
supply voltage 1.8 using CADENCE spectre tool. Virtuoso Analog Design Environment tool of
Cadence have used to design and simulate schematic. This work has been used in the design of 2.4
GHz CMOS PLL targeting Frequency Multiplier application. The proposed D flip flop circuit is
faster than the conventional circuit as it has fast reset operation. The circuit consumes less power as
it prevents short circuit power consumption.
Design of low power 4 bit full adder using sleepy keeper approacheSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
High performance novel dual stack gating technique for reduction of ground bo...eSAT Journals
Abstract The development of digital integrated circuits is challenged by higher power consumption. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Today leakage power has become an increasingly important issue in processor hardware and software design. So to reduce the leakages in the circuit many low power strategies are identified and experiments are carried out. But the leakage due to ground connection to the active part of the circuit is very higher than all other leakages. As it is mainly due to the back EMF of the ground connection we are calling it as ground bounce noise. To reduce this noise, different methodologies are designed. In this paper, a number of critical considerations in the sleep transistor design and implementation includes header or footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency. Novel dual stack technique is proposed that reduces not only the leakage power but also dynamic power. The previous techniques are summarized and compared with this new approach and comparison of both the techniques is done with the help of Digital Schematic( DSCH ) and Microwind low power tools. Stacking power gating technique has been analyzed and the conditions for the important design parameters (Minimum ground bounce noise) have been derived. The Monte-Carlo simulation is performed in Microwind to calculate the values of all the needed parameters for comparison. Index Terms: Ground Bounce Noise ,Power gating schemes ,Static power dissipation, Dynamic power dissipation, Power gating parameters, Sleep transistors, Novel dual stack approach, Transistor leakage power
A Comparative Study Of Low Power Consumption Techniques In A VLSI CircuitIJERA Editor
Power optimization has become an important factor in designing a VLSI circuit. Earlier dynamic power was single largest concern but as transistor size decreases static power dominates the dynamic power. A comparable analysis of different low power, leakage current reduction techniques like sleep, stack, sleepy keeper and reverse body bias with sleep and stack has been done. Based on simulations performed on a XNOR circuit, the reverse body with sleep and stack achieves up to 60% less power consumption as compared to the base case which is better than other conventional techniques. Simulations to estimate power consumption are done on a TANNER EDA tool at 90 nm technology.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Analysis of Sequential Elements for Low Power Clocking System with...IJERA Editor
This paper proposed the design of sequential elements for low power clocking system with low low power techniques for saving the power. Power consumption is a major bottleneck of system performance and is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flop-flops. In this paper, various design techniques for a low power clocking system are surveyed. Among them is an effective way to reduce capacity of the clock load by minimizing number of clocked transistors. To approach this, proposed a novel clocked pair shared flip-flop which reduces the number of local clocked transistors by approximately 40%. A 24% reduction of clock driving power is achieved. In addition, low swing and double edge clocking, can be easily incorporated into the new flip-flop to build clocking systems. As the feature size becomes smaller, shorter channel lengths result in increased sub-threshold leakage current through a transistor when it is off. Dual sleep and sleepy stack methods are proposed to avoid static power consumption; the flip flops are simulated using HSPICE.
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...IJERA Editor
According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.
A novel approach for leakage power reduction techniques in 65nm technologiesVLSICS Design
The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there
by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is
enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over
the world today, the battery-powered electronic system forms the backbone. To maximize the battery life,
the tremendous computational capacity of portable devices such as notebook computers, personal
communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has
to be realized with very low power requirements. Leakage power consumption is one of the major technical
problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power
minimization techniques have been presented in this paper a novel Leakage reduction technique is
developed in Cadence virtuoso in 65nm regim with the combination of stack with sleepy keeper approach
with Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%,
Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24%
with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.
1x2 Digital Optoelectronic Switch using MZI structure and studying the Effect...ijsrd.com
The electro optic switch has wide application in optical network due to capability of route the light path from one port to the desired port. In this paper, we propose a 1x2 digital optoelectronics switch based on mach-zehnder interferometer structure on a single titanium diffuse lithium niobate substrate. The design is simulate on BPM-cad simulator for switch analysis and study the effect of bipolar voltage 0v to ± 5.75v applied at 1st and center electrode region for switching. A short study of wavelength dependent switch for first optical window 8.5 µm and third optical window 1.55 µm has been simulated without use of voltage with changing titanium stripe thickness to 0.07µm.
This paper investigates about the possibility to reduce power consumption in Neural Network using approximated computing techniques. Authors compare a traditional fixed-point neuron with an approximated neuron composed of approximated multipliers and adder. Experiments show that in the proposed case of study (a wine classifier) the approximated neuron allows to save up to the 43% of the area, a power consumption saving of 35% and an improvement in the maximum clock frequency of 20%.
Minimization of redundant internal voltage swing in cmos full addereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Design of very large scale analog integrated circuit (analog VLSI) is very much complex and requires
much compromising nature to achieve application specific objective. With maximizing the efforts to reduce
power consumption and to reduce W/L ratio, the analog integrated circuit industry is constantly
developing smaller power supplies. Now days, challenges of analog integrated circuit designer are to
make block of small power supplies with little or no reduction in performance. The CMOS OTA is
designed in 25.5nm CMOS technology with 1.0V power supply to observe the configurations. In design of
CMOS OTA TANNER EDA TOOL is used. Coding and simulation is done in T-Spice and layout is
prepared in L-Edit. D.C analysis, A.C analysis, slew rate and analysis of transient response have been
done in T-Spice. Waveforms are observed in W-Edit.
A high speed low power consumption d flip flop for high speed phase frequency...IAEME Publication
Phase Frequency Detector (PFD) and Frequency divider are indispensable modules of PLL,
which uses D flip-flop as an integral part. This paper focus on design of High-Speed, Low Power
Consumption D Flip-Flop for High Speed Phase Frequency Detector and Frequency divider. The
designed Frequency divider has been used in the divider counter of the phase locked loop. A divide
counter is required in the feedback loop to scales down the frequency of the VCO output signal. The
conventional and proposed D-Flip flop has been designed in UMC 180nm CMOS Technology with
supply voltage 1.8 using CADENCE spectre tool. Virtuoso Analog Design Environment tool of
Cadence have used to design and simulate schematic. This work has been used in the design of 2.4
GHz CMOS PLL targeting Frequency Multiplier application. The proposed D flip flop circuit is
faster than the conventional circuit as it has fast reset operation. The circuit consumes less power as
it prevents short circuit power consumption.
Design of low power 4 bit full adder using sleepy keeper approacheSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
High performance novel dual stack gating technique for reduction of ground bo...eSAT Journals
Abstract The development of digital integrated circuits is challenged by higher power consumption. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Today leakage power has become an increasingly important issue in processor hardware and software design. So to reduce the leakages in the circuit many low power strategies are identified and experiments are carried out. But the leakage due to ground connection to the active part of the circuit is very higher than all other leakages. As it is mainly due to the back EMF of the ground connection we are calling it as ground bounce noise. To reduce this noise, different methodologies are designed. In this paper, a number of critical considerations in the sleep transistor design and implementation includes header or footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency. Novel dual stack technique is proposed that reduces not only the leakage power but also dynamic power. The previous techniques are summarized and compared with this new approach and comparison of both the techniques is done with the help of Digital Schematic( DSCH ) and Microwind low power tools. Stacking power gating technique has been analyzed and the conditions for the important design parameters (Minimum ground bounce noise) have been derived. The Monte-Carlo simulation is performed in Microwind to calculate the values of all the needed parameters for comparison. Index Terms: Ground Bounce Noise ,Power gating schemes ,Static power dissipation, Dynamic power dissipation, Power gating parameters, Sleep transistors, Novel dual stack approach, Transistor leakage power
A Comparative Study Of Low Power Consumption Techniques In A VLSI CircuitIJERA Editor
Power optimization has become an important factor in designing a VLSI circuit. Earlier dynamic power was single largest concern but as transistor size decreases static power dominates the dynamic power. A comparable analysis of different low power, leakage current reduction techniques like sleep, stack, sleepy keeper and reverse body bias with sleep and stack has been done. Based on simulations performed on a XNOR circuit, the reverse body with sleep and stack achieves up to 60% less power consumption as compared to the base case which is better than other conventional techniques. Simulations to estimate power consumption are done on a TANNER EDA tool at 90 nm technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
International Journal of Computational Engineering Research (IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Low Power Design of Standard Digital Gate Design Using Novel Sleep Transisto...IJMER
In the nanometer range design technologies static power consumption is very important
issue in present peripheral devices. In the CMOS based VLSI circuits technology is scaling towards
down in respect of size and achieving higher operating speeds. We have also considered these
parameters such that we can control the leakage power. As process model design are getting smaller
the density of device increases and threshold voltage as well as oxide thickness decrease to maintain
the device performance. In this article two novel circuit techniques for reduction leakage current in
NAND and NOR inverters using novel sleepy and sleepy property are investigated. We have proposed a
design model that has significant reduction in power dissipation during inactive (standby) mode of
operation compared to classical power gating methods for these circuit techniques. The proposed
circuit techniques are applied to NAND and NOR inverters and the results are compared with earlier
inverter leakage minimization techniques. All low leakage models of inverters are designed and
simulated in Tanner Tool environment using 65 nm CMOS Technology (1volt) technologies. Average
power, Leakage power, sleep transistor
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
Call for paper 2012, hard copy of Certificate, research paper publishing, where to publish research paper,
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJCER, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, research and review articles, IJCER Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathematics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer review journal, indexed journal, research and review articles, engineering journal, www.ijceronline.com, research journals,
yahoo journals, bing journals, International Journal of Computational Engineering Research, Google journals, hard copy of Certificate,
journal of engineering, online Submission
A NOVEL APPROACH FOR LEAKAGE POWER REDUCTION TECHNIQUES IN 65NM TECHNOLOGIESVLSICS Design
The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over the world today, the battery-powered electronic system forms the backbone. To maximize the battery life, the tremendous computational capacity of portable devices such as notebook computers, personal communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has to be realized with very low power requirements. Leakage power consumption is one of the major technical problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power minimization techniques have been presented in this paper a novel Leakage reduction technique is developed in Cadence virtuoso in 65nm regim with the combination of stack with sleepy keeper approach with Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%, Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24% with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.
Extremely Low Power FIR Filter for a Smart Dust Sensor ModuleCSCJournals
Digital filters are common components in many applications today, also in for sensor systems, such as large-scale distributed smart dust sensors. For these applications the power consumption is very critical, it has to be extremely low. With the transistor technology scaling becoming more and more sensitive to e.g. gate leakage, it has become a necessity to find ways to minimize the flow of leakage in current CMOS logic. This paper studies sub-threshold source coupled logic (STSCL) in a 45-nm process. The STSCL can be used instead of traditional CMOS to meet the low power and energy consumption requirements. The STSCL style is in this paper used to design a digital filter, applicable for the audio interface of a smart dust sensor where the sample frequency will be 44.1 kHz. A finite-length impulse response (FIR) filter is used with transposed direct form structure and for the coefficient multiplication five-bit canonic signed digit [7] based serial/parallel multipliers were used. The power consumption is calculated along with the delay in order to present the power delay product (PDP) such that the performance of the sub-threshold logic can be compared with corresponding CMOS implementation. The simulated results shows a significant reduction in energy consumption (in terms of PDP) with the system running at a supply voltage as low as 0.2 V using STSCL.
Design of subthreshold dml logic gates with power gating techniqueseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Improved Power Gating Technique for Leakage Power Reductioninventy
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A05320107
1. IOSR Journal of Engineering (IOSRJEN) www.iosrjen.org
ISSN (e): 2250-3021, ISSN (p): 2278-8719
Vol. 05, Issue 03 (March. 2015), ||V2|| PP 01-07
International organization of Scientific Research 1 | P a g e
Analysis and Reduction of Power using Gating Techniques Near
Subthreshold Region
A. Biju Anusha1
, Mrs.C.N.Kalaivani2
1
(ECE,DACE/Anna University, India)
2
(ECE,DACE/ Anna University, India)
Abstract: The sub-threshold and gate leakage power consumption in deep submicron CMOS systems are
projected to become a significant part of the total power dissipation. This paper presents several dual-threshold
voltage techniques for reducing standby power dissipation while still maintaining high performance. A dual-
mode logic gate, for selectable operation in either of static and dynamic modes, includes: a static gate which
includes at least one logic input and a logic output; a mode selector, configured for outputting a turn-off signal
to select static mode operation and for outputting a dynamic clock signal to select dynamic mode operation and
a switching element associated with the mode selector static gate, comprising a first input connected to a
constant voltage, a second input for inputting the mode selection signal from the mode selector, and an output
connected to a logic output of the static gate. The switching elements switches the logic gate operation from
static to dynamic mode, by applying the appropriate signal to the switching element. As transistor sizes scale
down and levels of integration increase, leakage power has become a critical problem in VLSI designs. In this
paper, an industry-standard technique known as power-gating is explored, whereby transistors are used to
disconnect the power from idle portions of a chip.This paper discusses the evolution of full adder circuits in
terms of lesser power consumption high speed. The power gating techniques are implemented to design a full
adder by reducing the number of transistors which also leads to the reduction of chip size.
Keywords: Dual Mode Logic, Sub-threshold, Power Gating
I. INTRODUCTION
The power consumption has become a primary focus in the VLSI design. There are number of portable
applications requiring small area low power high throughput circuitry. The sub-threshold logic technique is the
main area for low power applications. The supply voltage of the sub-threshold region is less than the threshold
voltages of the transistors so the static and dynamic power can be reduced. The dual mode logic (DML), which
operates in the sub-threshold region. The DML logic can be operated in two modes: static CMOS like mode and
dynamic np - CMOS- like mode. In the static mode the dual mode logic gate features very low power
dissipation with moderate performance while in dynamic mode they attain higher performance, though
with huge power dissipation. Low power utilization to be the most important for design of microprocessors
and system mechanism addition is one of the fundamental arithmetic operations. It is used in many VLSI
systems such as application specific DSP architectures and microprocessors.
II. POWER GATING TECHNIQUES
Power gating is a technique used in integrated circuit design to reduce power consumption, by shutting
off the current to blocks of the circuit that are not in use. In addition to reducing standby or leakage power,
power gating has the benefit of enabling Iddq testing. Shutting down the blocks can be accomplished either by
software or hardware. Driver software can schedule the power down operations. Hardware timers can be
utilized. A dedicated power management controller is another option. An externally switched power supply is a
very basic form of power gating to achieve long term leakage power reduction.
2.1.Sleep Method
The Sleep method is the basic power gating method. The sleep transistors isolate the logic networks and the
sleep transistor technique or the sleep method dramatically reduces leakage power during sleep mode. Fig.1
shows Type B Dynamic DML NAND with sleep gating technique.
2. Analysis and Reduction of Power using Gating Techniques Near Subthres hold Region
International organization of Scientific Research 2 | P a g e
Fig(1): Type B dynamic NAND sleep method
2.2.Sleepy Stack Method
The sleepy stack approach merges the sleep and stack approaches. The sleepy stack technique splits the existing
transistors into two half Size transistors like the stack approach. The activity of the sleep transistors in the sleepy
stack method is same as the activity of the sleep transistors in the sleep method. The sleep transistors are turned
on during the active mode and they are turned off during the sleep mode. Fig.2 shows Type A static NOR gate
with Sleepy Stack Gating Technique.
Fig(2): Type A static NOR sleepy stack method
2.3.DualSleep Method
The Dual sleep approach has the advantage of using the two extra pull up and two extra pull down transistors in
sleep mode either in OFF state or in ON state. In normal mode when S=1 the pull down NMOS transistor is in
ON state and in the pull up network the PMOS sleep transistor is in ON state since S‟=0. During sleep mode
state S is forced to 0 and hence the pull down NMOS transistor is in OFF state and PMOS transistor is in ON
state and in the pull up network, PMOS sleep transistor is OFF while NMOS sleep transistor is ON. So in sleep
mode state a PMOS is in series with an NMOS both in pull up network and pull down network which reduces
the power dissipation. Fig.3 shows Type B Dynamic PSEUDO NMOS with Dual Sleep Gating Technique.
Fig(3): Type B dynamic PSEUDO NMOS dual sleep method
3. Analysis and Reduction of Power using Gating Techniques Near Subthres hold Region
International organization of Scientific Research 3 | P a g e
The NAND Dual mode logic gate is compared in terms of power consumption for different gating
techniques like sleep method, sleepy stack method and dual sleep method in Table 1.
Table(1): Comparison between NAND DML gates with different gating techniques
The NOR Dual mode logic gate is compared in terms of power consumption for different gating
techniques in Table 2.
Table(2): Comparison between NOR DML gates with different gating techniques
The Pseudo nMOS logic is compared in terms of power consumption for different gating techniques in Table 3.
Table(3): Comparison between PSEUDO NMOS DML gates with different gating techniques
Gating
Techniques
Modes
NAND SLEEP NAND
SLEEPY STACK
NAND
DUAL SLEEP
0-2
v
2-5
v
5-50
v
0-2
v
2-5
v
5-50
v
0-2
v
2-5
v
5-50
v
Conventional 26
uW
42
uW
230
mW
200
uW
460
uW
270
mW
330
uW
820
uW
940
mW
Type A static 28
uW
44
uW
280
mW
350
uW
740
uW
310
mW
500
uW
1.2
mW
1000
mW
Type A dynamic 38
uW
60
uW
280
mW
330
uW
700
uW
310
mW
480
uW
1.1
mW
1000
mW
Type B static 320
uW
620
uW
290
mW
380
uW
840
uW
330
mW
350
uW
880
uW
900
mW
Type B dynamic 300
uW
640
uW
290
mW
370
uW
800
uW
340
mW
350
uW
840
uW
900
mW
Gating
Techniques
Modes
NOR SLEEP NOR SLEEPY STACK NOR DUAL SLEEP
0-2
v
2-5
v
5-50v 0-2
v
2-5
v
5-50v 0-2
v
2-5
v
5-
50v
Conventional 180
uW
340
uW
190
mW
170
uW
370
uW
190
mW
320
uW
780
uW
190
mW
Type A static 230
uW
460
uW
320
mW
270
uW
580
uW
320
mW
400
uW
920
uW
320
mW
Type A
dynamic
220
uW
440
uW
320
mW
230
uW
450
uW
320
mW
370
uW
900
uW
320
mW
Type B static 180
uW
350
uW
160
mW
160
uW
350
uW
160
mW
330
uW
780
uW
160
mW
Type B
dynamic
180
uW
350
uW
160
mW
160
uW
370
uW
160
mW
330
uW
780
uW
160
mW
Gating
Techniques
Modes
PSEUDO NMOS SLEEP PSEUDO NMOS
SLEEPY STACK
PSEUDO NMOS
DUAL SLEEP
0-2
v
2-5
v
5-50
v
0-2
v
2-5
v
5-50
v
0-2
v
2-5
v
5-50
v
Conventional 130
uW
240
uW
170
mW
15
uW
25
uW
170
mW
270
uW
700
uW
170
mW
Type A static 10
uW
15
uW
240
µW
200
uW
450
uW
240
µW
340
uW
860
uW
240
µW
Type A dynamic 19
uW
30
uW
500
µW
170
uW
400
uW
500
µW
320
uW
840
uW
500
µW
Type B
static
8
uW
12
uW
200
µW
82
uW
210
uW
200
µW
280
uW
680
uW
200
µW
Type B dynamic 16
uW
25
uW
400
µW
100
uW
240
uW
400
µW
280
uW
680
uW
400
µW
4. Analysis and Reduction of Power using Gating Techniques Near Subthres hold Region
International organization of Scientific Research 4 | P a g e
III. FULL ADDER CIRCUITS
A one-bit full adder adds three one-bit numbers, and it is written as A, B, and Cin. A and B are the
operands, and Cin is a bit carried in from the previous less significant stage. The full adder is a component in a
cascade of adders, which adds 8, 16, 32, etc. bits binary numbers. The circuit produces a two-bit outputs. The
outputs are carry and sum typically represented by the signals Cout and S. The expression for sum and carry can
be represented as,
Sum = 𝐴 ⊕B ⊕C
𝐶𝑎𝑟𝑟𝑦 = 𝐴. 𝐵 + (𝐶 (𝐴 ⊕ 𝐵))
The full adder consists of two half adders and one OR gate. The circuit diagram for one bit full adder is shown
in fig.4.
Fig(4): 1-bit Full Adder
The conventional full adder is a basic full adder and it consists of 32 transistors. The schematic of conventional
full adder is shown in Fig.5.
Fig(5): Schematic of Conventional Full Adder
The full adder sleep method consists of 34 transistors. The power gating technique is used to reduce the
leakage power by placing the sleep transistor between actual ground rail and circuit ground. The low leakage
NMOS is used as a sleep transistor. The sizing of the transistor reduces the standby leakage current to a very
great extent. The major drawback of sleepy technique is it cannot retain the values when it enters into sleep
mode, since there will be no supply the output values cannot be retained. For combinational circuits it will be
fine but for sequential circuits it will fail as they depends on previous outputs. The schematic of full adder sleep
method is shown in Fig.6.
5. Analysis and Reduction of Power using Gating Techniques Near Subthres hold Region
International organization of Scientific Research 5 | P a g e
Fig(6): Schematic of Full Adder Sleep method
The full adder sleepy stack method consists of 36 transistors. The drawback of sleep method is avoided
by using sleepy stack method. In active mode the dissipation of power is active power. The active power
consists of dynamic power as well as static power. so it is named as an active power. In static mode the both
header and footer switches will be off there will be no 𝑉𝑑𝑑 supply and ground connected to the circuit. So the
power dissipation will be very less. The schematic of full adder sleepy stack method is shown in fig.7.
Fig(7): Schematic of Full Adder Sleepy Stack method
The full adder dual sleep method consists of 36 transistors. Two sleep transistors in every NMOS or
PMOS block are used. One sleep transistor is in ON state and alternative is in OFF state. Once more in OFF
state a block containing each PMOS and NMOS transistors are utilized in order to scale back the outflow power.
The schematic of full adder dual sleep method is shown in fig.8.
6. Analysis and Reduction of Power using Gating Techniques Near Subthres hold Region
International organization of Scientific Research 6 | P a g e
Fig(8): Schematic of Full Adder Dual Sleep method
The transmission gate full adder consists of 22 transistors. The transmission gate full adder enforced
with minimum number of transistors compared to conventional full adder design. The consecutive connected
PMOS and NMOS arrangement act as a switch and is thus referred to as transmission gate. A transmission gate
or analog switch is an electronic element that will selectively block or pass a signal level from the input to the
output. The schematic of transmission gate full adder is shown in fig.9.
Fig(9): Schematic of Transmission Gate Full Adder
The power analysis of different gating techniques is shown in Table 4.
Circuit Power (mW)
Conventional Full Adder 30
Full Adder Sleep method 0.7
Full Adder Sleepy Stack 9.4
Full Adder Dual Sleep 3.1
Full Adder Transmission Gate 12
Table (4): Power analysis of different Power Gating Techniques
7. Analysis and Reduction of Power using Gating Techniques Near Subthres hold Region
International organization of Scientific Research 7 | P a g e
IV. CONCLUSION
The result obtained leads to the conclusion that while operating in the dynamic mode, sub threshold
DML gates achieve an improvement in speed compared to a standard CMOS, while dissipating more power and
in the static mode, a reduction of power dissipation is achieved, at the expense of a decrement in performance.
The different methods of power gating applied to the DML logic have reduced the power dissipation.
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