This document discusses electronic packaging trends. It provides a brief history of electronic packaging from the transistor to modern technologies like 3D stacking. It describes the hierarchy of packaging from the chip level to board and system levels. Recent trends include advanced packaging for mobile devices and future technologies like 3D integration. The document aims to provide an overview of electronic packaging and sources for further study.

1. Electronic Packaging Trends
By Tom Terlizzi
Vice President
GM Systems
Briarcliffe College,
October 5, 2011
Bethpage, NY

2. Purpose
• Discuss “Electronic Packaging Trends”.
• Discuss “Why” electronic packaging is valuable.
to circuit designers and consultants.
• Describe some basic tutorial information and sources for further study.
• Generate CEU Credits.
2

3. Outline
• A
Short
History
of
Electronic
Packaging
• Func8ons
of
Electronic
Packaging
• Packaging
Hierarchy
/
Levels
• Packaging
Technology
Drivers
• Packaging
Electrical
Design
Considera8ons
• Recent
Trends
in
Advanced
Packaging
Industries
• Electronic
Package
Trends
based
on
Mobile
PlaDorm
• Future
of
Electronic
Packaging
Technology
3 • Ques8ons
and
Answers
Session.

4. 4

5. History of Electronic Packaging
5 http://www.computerhistory.org/semiconductor/timeline.html

6. History of Electronic Packaging
6

7. History of Electronic Packaging
7

8. History of Electronic Packaging
8

9. History of Electronic Packaging
9

10. History of Electronic Packaging
10

11. History of Electronic Packaging
Jack Kilby Texas Instrument
11

12. History of Electronic Packaging
12

13. Transistor Radio
13

14. History of Electronic Packaging
Commercialized by Bryant “Buck” Rogers and Rex Rice
of Fairchild first in ceramic then plastic.
Dr. Nathan Pritikin Patent
14

15. History of Electronic Packaging
15

16. History of Electronic Packaging
16

17. History of Electronic Packaging
17

18. Packaging Hierarchy / Levels
18

19. Function of Electronic Packaging
• Interconnec8on
• Signal
Distribu8on
• Power
Distribu8on
• Physical
Support
• Environmental
• Heat
Dissipa8on
19

20. Function of Electronic Packaging
Signals In Signals Out
20

21. Constraints on Electronic Packaging
• Performance
• Size
• Weight
• Testability
• Reliability
• Cost
21

22. Packaging Hierarchy / Levels
• Level
0
“On
Chip”
Connec8ons
• Transistor
to
Transistor
• Gate
to
Gate
• Gate
to
Input/Output
(I/O)
• Level
1
Single
Chip
Packages
• Chip
(Die)
to
package
• (Level
1.5)
Mul8
Chip
Packages,Hybrids,
Chip
On
Board
• Level
2
Chip
Packages
to
PWB/PWA/MLB
• Level
3
Rack
&
Card
,
Board
to
Board,
Backplanes,Cables.
22

23. Packaging Hierarchy / Levels
23

24. Packaging Hierarchy / Levels
Wire Bonded
Singulated
Die
Wafer Die
Level 0 Level 1 Level 2
“On Chip” Connections
Chip (Die) to package
Chip Packages to PWB/PWA/MLB
24

25. Packaging Hierarchy / Levels
• Level
0
“On
Chip”
Connec8ons
• Top
Metal
is
aluminum
~100µ L
&
W
on
60µ pitch
• Level
1
Single
Chip
Packages
• Chip
(Die)
to
package
• Gold
wire
bonding
~0.7
to
2
mils
in
diameter,
60µ pitch
• Aluminum
wire
bonding
~1
to
25
mils
in
diameter
• Flip
chip
with
bumps
&
micro
bumps
• Combina8on
of
above
• Level
2
Chip
Packages
to
PWB/PWA/MLB
• “Thru”
hole
•
Surface
Mount
Technology
(SMT)
25

26. Packaging Hierarchy / Levels
Electronic Flame Off (EFO)
26

27. Packaging Hierarchy / Levels
27

28. Packaging Hierarchy / Levels
125 µ diameter
C4NP Lead Free SnAg
31µ diameter
IBM’s C4 used evaporation and 19µ space
28 to deposit 95/5 PbSn 50 µ pitch

29. Chip On Board (COB)
2.5” X 3.5”
LCD Display
Flex Cable
0.375” diameter
Glob Top
over Wire Bonded Die
PWB
Front Side Back Side of $1 Calculator
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30. Packaging Hierarchy / Levels
Fine Pitch BGA
Package on Package Package in Package
Ball Grid Array
30

31. 3-D Packaging
TSV
1960
3D stacked chips
1960-1970’s
1950’s
Cord Wood Modules
Project Tinker Toy
31 Micro Module

32. About :
• Strategic
Consul8ng,
including
business
plan
&
sales
strategy
development
for
high
technology
products,
acquisi8ons
and
partnership.
•
Proposal
support,
cri8que,
evalua8on
and
genera8on
• Failure
analysis
of
thin
film
and
thick
film
resistors,
integrated
circuits
and
board
level
problems
• Electronic
Design
engineering
and
so]ware
support
• Technology
review
and
research
for
consumer
electronics,
internet
devices,
solar
energy,
MEMS,
nanotechnology,
microelectronics,
SMT,
and
health
care
so]ware
products.
32