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- 1. Introduction CHAPTER 2 Counter - A counter is a sequential logic circuit consisting of a set of flip-flops which can go through a sequence of states. COUNTER 1 2 Introduction (continue) Counters Counters are formed by connecting flip-flops together Types of counter are; Asynchronous counter Synchronous counters Asynchronous Clock pulse is applied to Also known as ripple counter (Ripple counter) each FF simultaneously The first flip-flop is driven by external clock while the The output of one FF drives successive flip-flops by the output of preceding flip-flop the input of the next one High Speed Slow speed 3 4
- 2. Introduction (continue) Synchronous All flip-flops are simultaneously driven by common clock Asynchronous counter Each type of counter are classified by; Sequence i.e up or down Number of states i.e 2-bit will have 4 states (2N) Number of flip-flops i.e same as number of bits 5 6 Asynchronous counter Up counter and down counter for negative edge clock Also known as ripple counter. Ripple counters are the simplest type of binary counters because they require the fewest components to produce a given counting operation. 3-bit binary up counter Each FF output drives the CLK input of the next FF. FFs do not change states in exact synchronism with the applied clock pulses. There is delay between the responses of successive FFs. 3-bit binary down counter It is also often referred to as a ripple counter due to the way the FFs respond one after another in a kind of rippling effect. 8
- 3. Asynchronous Counter Operation Up counter and down counter for positive edge clock For example, 2-bit asynchronous binary counter using J-K FF 3-bit binary down counter CLK is only connected to 1st FF0, LSB FF The 2nd FF clock is driven by Q0 of 1st FF Both FF input are always HIGH Q0 changes state at the positive-edge clock 3-bit binary up counter Q1 change at the positive-edge of the Q0 Note that the two FFs do not triggered at the same time because clock and Q0 transitions do not occur at the same time 9 10 Asynchronous Counter Operation (continue..) Asynchronous Counter Operation (continue..) Timing diagram for 2-bit asynchronous binary counter Binary state sequence for 2-bit asynchronous binary counter Four clock pulses are applied, assume initially all LOW The counter is in up sequence (Q1 is MSB, Q0 is LSB) Q0 (LSB) is always toggle at positive-edge clock (J and K are HIGH) Count from 0 to 3 in binary sequence Q0 is reciprocal of Q0 The term ‘recycle’ refers to the transition from final state to original state Q1(MSB) is toggle at positive-edge of Q0 Therefore, 2-bit asynchronous counter has four state and consists of two FF At 4th clock pulse, the counter is recycle to its original state (both FF are LOW) 11 12
- 4. A 3-bit Asynchronous Binary Counter A 3-bit Asynchronous Binary Counter (continue..) Draw 3-bit asynchronous up counter using J-K FFs Tabulate the state sequence for 3-bit asynchronous up counter Sketch the timing diagram for 3-bit asynchronous up counter Conclusion, 3-bit asynchronous up counter consists of three J-K FFs and counts from 0 to 7 (8 states) 13 14 Disadvantages of asynchronous counter: Propagation Delay Disadvantages of asynchronous Propagation delay in 3-bit asynchronous counter (ripple clocked) binary counter as shown below counter (continue) Asynchronous counters are not useful at very high frequencies, especially for counters with large number of bits. Another problem caused by propagation delays in asynchronous counters occurs Propagation delay occurs through FF0 cause Q0 lags some time compare to CLK when we try to electronically detect (decode) This effect ‘ripples’ the next FF resulting Q1 delay some time from Q0 the counter’s output states. The cumulative delay of asynchronous counter is the major disadvantage of this counter in many applications. It limits the rate at which the counter can be clocked and creates decoding problems. The maximum cumulative delay in a counter must be less than the period of the clk waveform. 15 16
- 5. Exercise: A 4-bit Asynchronous Binary Counter Disadvantages of asynchronous counter (continue) Draw the timing diagram for 4-bit asynchronous up counter given below Eg: If you look closely at the figure below, for a short period of time (50ns) right after state 011, you see that state 010 occurs before 100. This is obviously not the correct binary counting sequence and while the human eye is much too slow to see this temporary state, our digital circuits will be fast enough to detect it. These erroneous count patterns can generate what are called glitches in the signals that are produced by digital systems using asynchronous counters. In spite of their simplicity, these problems limit the usefulness of asynchronous counters in digital applications. 17 18 A 4-bit Asynchronous Binary Counter (Continue) Asynchronous MOD counter Each flip-flop has a propagation delay for 10ns. Determine the total propagation delay time from the triggering edge of a clock pulse until a corresponding change can occur in the state of Q3. Also determine the maximum clock MOD number is generally equal to the frequency at which the counter can be operated. number of states that the counter goes Answer: For the total delay time, the effect of CLK8 or CLK16 must propagate through 4 through in each complete cycle before it flip-flops before Q3 changes. recycles back to its starting state. tp(tot) = 4 x 10ns = 40ns MOD number can be increased simply by The maximum clock frequency is adding more FFs to counter. MOD number = fmax = 1/tp(tot) = 1/40ns = 25MHz 2N * The counter should be operated below this frequency to avoid problems due to the propagation delay. 19 20
- 6. Asynchronous MOD counter Changing the MOD number (continue) Determine the MOD number of the counter in Example Fig. 6-6(a). Also determine the frequency at the A photocell and light source combination is used D output. to generate a single pulse each time an item Ans.) Mod-14 ripple counter, 30/14 = 2.14 kHz crosses its path. The counter must be able to count as many as 1000 items. How many FFs are required? ans.) 2n = 1000 n = log1000/log2 = 10 FFs 21 Changing the MOD number Frequency Division Construct a MOD-10 counter that will count from Each flip-flop provides an output waveform 0000 through 1001. that is exactly half the frequency of the waveform at its CLK input. In any counter, the signal at the output of the last flip-flop (i.e; the MSB) will have a frequency equal to the input clock frequency divided by the MOD number of the counter. 24
- 7. Frequency Division (continue) Example E.g: in a MOD-16 counter, the output from the last FF will have a frequency of 1/16 of the input clock frequency. Thus, it can also be called a divide-by-16 counter. Likewise, a MOD-8 counter has an output frequency of 60-Hz signal is fed into a Schmitt-trigger, pulse-shaping circuit 1/8 the input frequency; it is a divide-by-8 counter. to produce a square wave. 60Hz square wave is then put into a MOD-60 counter, which is used to divide the 60-Hz frequency by exactly 60 to produce a 1-Hz waveform. 1-Hz waveform is fed to a series of counters, which then count Ss, Ms, Hs, and so on. How many FFs are required for the MOD-60 counter? 6 FFs 25 Asynchronous Decade Counter Asynchronous Decade Counter (continue..) Counters can be designed to have a number of states in their sequence that is Timing diagram and binary state sequence for decade counter less than the maximum of 2N. This type of sequence is called a truncated sequence. For example, asynchronous modulus ten (MOD-10) counter or decade counter 0 1 0 1 NAND gate inputs are derived from Q3 AND Q1 Note that 10 is 1010 which is Q3 AND Q1 are HIGH CLR is produced and then reset all FFs to recycle The counter count again 27 28
- 8. Asynchronous Decade Counter Exercise Exercise Modify MOD-10 asynchronous counter to have MOD-12 and draw the timing diagram (1100) 0 0 1 1 1. What is the difference of operation between asynchronous and synchronous counter? 29 30 Answer: Exercise (continue) 2. Draw the circuit for asynchronous counter according to these attributes: MOD 13 counter using JK flip-flops. Negative edge triggered Down counter Active low preset and clear input 31 32
- 9. Answer: Synchronous counter 33 34 Synchronous counter Excitation table Also known as parallel counter. The flip-flop inputs are based on excitation table. Synchronous counters eliminate the propagation delay problem because all the clock inputs (cp) are tied to a common clock. Can operate at higher clock frequencies. Asynchronous counters are not useful at very high frequencies, especially for large number of bits. Requires more circuitry than the asynchronous counterpart. The design starts with State diagram Truth table K-map & equation circuit 35 36
- 10. Types of synchronous counter Design step for synchronous up counter Up counter. Eg: 0123 Example: Design a 2 bit counter using D, T and Down counter. Eg: 3210 JK flip-flop based on the sequence 0123. Irregular binary sequence counter. Eg:0347 Synchronous mod-counter Step 1: Draw the state diagram Up/down counter or bidirectional counter (a control input is required for selection of modes). Up counter or down counter with asynchronous inputs (active high or active low preset and clear). 37 38 Design step for synchronous up counter Design step for synchronous up counter (continue) (continue) Step 2: Fill in the truth table Step 3: Generate k-map Step 4: Draw logic circuit # The flip-flop inputs are based on the excitation table 39 40
- 11. Up counter using T flip-flop Up counter using JK flip-flop Using JK flip-flop Using T flip-flop 41 42 Design of Synchronous Counter Exercise 1 Design of Synchronous Counter Exercise 1 (continue..) Design a counter to produce 3-bit binary counter using J-K FF Design a counter to produce 3-bit binary counter using J-K FF State diagram State and excitation tables K-maps PRESENT NEXT STATE FLIP-FLOP INPUTS STATE Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0 0 0 0 0 0 1 0 X 0 X 1 X 0 0 1 0 1 0 0 X 1 X X 1 0 1 0 0 1 1 0 X X 0 1 X 0 1 1 1 0 0 1 X X 1 X 1 Counter implementation 1 0 0 1 0 1 X 0 0 X 1 X 1 0 1 1 1 0 X 0 1 X X 1 1 1 0 1 1 1 X 0 X 0 1 X 1 1 1 0 0 0 X 1 X 1 X 1 43 44
- 12. Design of Synchronous Counter Exercise 2 Design of Synchronous Counter Exercise 2 (continue..) Design a counter to produce 3-bit binary counter using D FF Design a counter to produce 3-bit binary counter using D FF State diagram State and excitation tables K-maps Q0 Q0 Q0 PRESENT NEXT STATE FLIP-FLOP INPUTS Q2Q1 0 1 Q2Q1 0 1 Q2Q1 0 1 STATE 00 0 0 00 0 1 00 1 0 Q2 Q1 Q0 Q2 Q1 Q0 D2 D1 D0 01 0 1 01 1 0 01 1 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 11 1 0 11 1 0 11 1 0 0 1 0 0 1 1 0 1 1 10 1 1 10 0 1 10 1 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 D2 map D1 map D0 map 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 45 46 Design of Synchronous Counter Exercise 2 (continue..) Irregular Binary Counter Design a counter to produce 3-bit binary counter using D FF Counting without according to regular sequence. Counter implementation Eg: Design a counter with the irregular binary count sequence 0347 using D flip-flop. Answer: 47 48
- 13. Synchronous mod-counter Synchronous mod-counter (continue) Eg: Design a mod-5 synchronous counter using D flip-flop. How many states does this counter have? What is the minimum number of flip-flop required? Answer: The counter will count from 04. Therefore there are 5 states. 3 flip-flop are required. 49 50 Design of Synchronous Counter Exercise 3 Design of Synchronous Counter Exercise 3 (continue..) Design MOD5 synchronous counter using D FF Design MOD5 synchronous counter using D FF State diagram State and excitation tables K-maps Q0 Q0 Q0 PRESENT NEXT STATE FLIP-FLOP INPUTS Q2Q1 0 1 Q2Q1 0 1 Q2Q1 0 1 STATE 00 0 0 00 0 1 00 1 0 Q2 Q1 Q0 Q2 Q1 Q0 D2 D1 D0 01 0 1 01 1 0 01 1 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 11 0 0 11 0 0 11 0 0 0 1 0 0 1 1 0 1 1 10 0 0 10 0 0 10 0 0 0 1 1 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 D2 map D1 map D0 map 1 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 51 52
- 14. Design of Synchronous Counter Exercise 3 (continue..) Design of Synchronous Counter Exercise 4 Design MOD5 synchronous counter using D FF Design MOD5 synchronous counter using T FF Counter implementation State diagram State and excitation tables PRESENT NEXT STATE FLIP-FLOP INPUTS STATE Q2 Q1 Q0 Q2 Q1 Q0 T2 T1 T0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 1 1 53 54 Design of Synchronous Counter Exercise 4 (continue..) Design of Synchronous Counter Exercise 4 (continue..) Design MOD5 synchronous counter using T FF Design MOD5 synchronous counter using T FF K-maps Counter implementation Q0 Q0 Q0 Q2Q1 0 1 Q2Q1 0 1 Q2Q1 0 1 00 0 0 00 0 1 00 1 1 01 0 1 01 0 1 01 1 1 11 1 1 11 1 1 11 0 1 10 1 1 10 0 0 10 0 1 T2 map T1 map T0 map 55 56
- 15. Exercise Topic: Design a 3 bit synchronous counter for the Up/down counter or bidirectional counter sequence 0642 using Cascaded counter a) D flip-flop Asynchronous cascaded counter b) T flip-flop Synchronous cascaded counter c) JK flip-flop Counter decoding Decoding glitches Strobing technique 57 58 Up/Down Synchronous Counter (bidirectional counter) Up/Down Synchronous Counter design procedure • Bidirectional counters, also referred to as UP/DOWN counters, are capable of Eg: Design a 2 bit up/down counter using T flip-flop based on the progressing in either direction through any given count sequence. Recall that in state diagram below. Assume up = 1 and down = 0. general, bidirectional counters can be reversed at any point in their count sequence. Answer: • Capable to count in either direction through a certain sequence • For example 3-bit up/down synchronous counter Able to count from 0 to 7 or 7 to 0
- 16. Cascaded Counters Cascaded Counters (continue) • Counters can be connected to achieve higher modulus Asynchronous cascading operation. Two asynchronous counters connected in cascade for a 2 bit and a 3 bit ripple counter. The overall modulus of the two cascaded • Cascading means that the last stage output of one counter counters is 4 x 8 = 32; that is they act as a divide-by-32 counter. drives the input of the next counter. • A mod-M and a mod-N counter in cascade give a mod-MN counter. • 2 types of cascading: Asynchronous cascading and synchronous cascading 62 Cascaded Counters (continue) Cascaded Counters (continue) Synchronous cascading In synchronous cascaded counter, it is necessary to use the count enable (CTEN) and the terminal count (TC) functions to achieve higher modulus Example 1: The figure below shows a mod-10 counter operation. and mod-8 counter connected in cascade. What is the Terminal count (TC) is analogous to ripple clock or ripple carry out (RCO) on some IC counters. overall modulus of these two cascaded counter? Determine the frequency at B if fin is 20kHz. Answer: Overall modulus = 10 x 8 =80 = mod-80 counter Frequency at B = fin/80 = 250Hz • 64
- 17. Cascaded Counters (continue) Cascaded Counters (continue) Example 3: Determine the overall modulus of the two cascaded Example 2: counter for (a) and (b) How many decade counters are required to convert a clock of 1 MHz to 1 Hz? Draw the circuit. Answer: fout = fin/10n 1 = (1x106)/10n n = log (1x106)/log10 n = 6 decade counter Answer: (a) the overall modulus for the 3 counter configuration is 8 x 12 x 16 = 1536 = mod-1536 (b) the overall modulus for the 4 counter configuration is 10 x 4 x 7 x 5 = 1400 = mod-1400 65 66 Decade Counters/BCD counters Counter Decoding (decoding a counter) Mentally decoding the binary states of the LEDs Decade counter Becomes inconvenient as the size of the counter Any counter has 10 distinct states, no matter what increases the sequence. Electronically decoding To determine when the counter is in a certain binary states in its sequence using decoders or logic gates. BCD counter 3 types of decoding: A decade counter counts in sequence from 0000 1. Active-High Decoding (AND gate) (zero) through 1001(decimal 9). 2. Active-Low Decoding (NAND gate) 3. BCD counter decoding 67 68
- 18. Counter Decoding (decoding a counter) Counter Decoding (decoding a counter) • Example: to decode binary state 6 (110) of a 3 bit Example: A 3-bit counter with active-HIGH decoding of binary counter. When Q2=1, Q1=1 and Q0=0, a HIGH count 2 and count 7. appears on the output of the decoding gate. 70 Decoding glitches Example of glitches The decoding process may resort to glitches. What is glitch? Glitch is an erroneous count patterns or unwanted output voltage caused by the propagation delay effect. Figure: a basic BCD/decade counter Occurs to (a) Asynchronous counter – propagation delay due to ripple effect (b) Synchronous counter – propagation delay from the clock to the Q output of every flip-flop Figure: Outputs with glitches
- 19. Solution to eliminate glitches Example without glitches Strobing - enable the decoded outputs at a time after the glitches have had time to disappear. Accomplished in the case of an active high clock by using the low level of the clock to enable the decoder. Figure: the basic decade counter and decoder to with strobing to eliminate glitches Figure: Strobed decoder outputs Exercise 1 Design a 3 bit up/down counter using JK flip-flop based on the state diagram below. Assume up = 1 and down = 0.