This document discusses digital electronics and memory devices. It covers the following topics: 1. Different types of memory devices like ROM, PROM, EPROM, EEPROM, RAM, and their basic structures and workings. 2. Programmable logic devices like PLA, PAL, and FPGA and how they can be used to implement combinational logic circuits. 3. Digital integrated circuits concepts like logic levels, propagation delay, power dissipation, fan-out, noise margin and different logic families like RTL, TTL, ECL, and CMOS.

1. R.M.K COLLEGE OF ENGINEERING & TECHNOLOGY
DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
EC8392- DIGITAL ELECTRONICS
UNIT-V
By
S.Sesha Vidhya /ASP/ECE

2. UNIT V
MEMORY DEVICES AND DIGITAL INTEGRATED CIRCUITS
Basic memory structure – ROM -PROM – EPROM – EEPROM –
EAPROM, RAM – Static and dynamic RAM
Programmable Logic Devices – Programmable Logic Array (PLA) -
Programmable Array Logic (PAL) – Field Programmable Gate
Arrays(FPGA) - Implementation of combinational logic circuits using
PLA, PAL.
Digital integrated circuits: Logic levels, propagation delay, power
dissipation, fan- out and fan in, noise margin, logic families and their
characteristics-RTL,TTL, ECL, CMOS 2

3. Basic Memory Structure
Memory Unit
• Memory unit is a collection of storage cells with associated circuits needed to
transfer information in and out of the device.
• It stores data or binary information in groups of bits called ‘words.’ Each word
consists of a sequence of 0’s and 1’s.
• A word may represent a number, an instruction, one or more Alphanumeric
characters or any other binary information’s.
• Each word stored in a memory location is represented by an ‘Address’.
• The communication between a memory and its environment is achieved through data
input/output lines, Address selection lines and control lines that specify the
direction of transfer.
3

4. Memory Unit
Memory Types
4

5. Read Only Memory
(ROM)
• ROM is a memory device in which permanent binary information
is stored. The binary pattern must be specified by the designer
and then embedded in the unit to form the required
interconnection pattern.
• Once the pattern is established, it stays within the unit even
when the power is turned off.
• A ROM is programmed for a particular purpose during the
manufacturing process and a user cannot alter its function.
• The memory from which we can only read but cannot write on
it. This type of memory is non-volatile.
• The information is stored permanently in such memories during
manufacture.
• A ROM stores such instructions that are required to start a
computer. This operation is referred to as bootstrap.
• ROM chips are not only used in the computer but also in other
electronic items like washing machine and microwave oven.
5

6. Types of ROM
6

7. ROM CELLS Advantages of ROM
• The presence of a connection from a row line to the base of
a transistor represents 1 at that location.
• When row line is taken high, all transistors with base
connection to that row line turn ON and connect the HIGH
to the associated column lines.
• When there is no base connection, zero value is stored.
• Non-volatile in nature
• Cannot be accidentally changed Cheaper than
RAMs
• Easy to test
• More reliable than RAMs
• Static and do not require refreshing
• Contents are always known and can be verified
7

8. Internal structure of 32 x 8 ROM
• ROM is a combinational logic circuit. It includes
decoder and the OR gates within a single IC
package.
• ROM is characterized by 2n
x m.
• In the given example 32 x 8 implies 25
x 8, where 5
represents address lines and 8 represents number
of OR gates (output).
• This structure has 32 x 8 = 256 internal
connections.
• The programmable intersection between two lines
is called cross-point. Various physical devices are
used to implement cross-point switches. One of
the familiar technologies is “Fuse” that normally
connects the two cross-points (programmable)
• Fuses opened are blown by the application of the
high voltage pulse into the fuse. 8

9. Design a combinational circuit using ROM. The circuit accepts a 3-bit binary number at the
input and generates its square value at the output.
8 x 4 ROM Structure
9

10. Implement the following Boolean function using ROM. F1(A, B, C) = Ʃm(0,1,3,4),
F2(A, B, C) = Ʃm(1,2,3,4,5).
10

11. Implement a Full adder using ROM.
11

12. Random Access Memory(RAM)
• RAM is volatile type of memory, since the stored data will be lost once the
DC power applied to the flipflops is removed.
4x4 RAM Structure
12

13. Types of Random Access Memory
•Static RAM
o Employs bipolar or MOS flipflops
•Dynamic RAM
o Uses MOSFETs and capacitors to store data
13

14. Internal structure of a SRAM
• RAM has address inputs, data inputs and a
read/write control.
• When Read / (Write’) signal is high (read
mode), four data bits from the selected address
appear on the data output.
• When Read / (Write’) signal is low (write
mode), the four data bits that are applied to the
data inputs are stored at the selected address.
Here memory cells are arranged by 256 rows
and 4 columns, totally 1024 bit device. 14

15. SRAM Cell
• SRAM contains an array of flipflops. Data
written into a flipflop remains stored as long
as DC power is maintained.
• The input data bit 1 or 0 is written into a cell
by setting the flipflop for a 1 and resetting the
flipflop for a 0 using Read / (Write’) signal.
15

16. Dynamic RAM
• DRAM is a high density and low cost memory.
• Computers use DRAM for main memory storage
• DRAM stores its binary information in the form of electric charges on capacitors.
• Data are stored as charge on every capacitor which must be recharged or
periodically refreshed in order to retain the stored data.
DRAM
Advantages
• It has large memory arrays on a chip at a lower cost per bit than in static
memories
• Memory devices use an integrated MOS capacitors as basic memory cells instead of a
flipflop
Disadvantages
• MOS capacitor cannot hold the stored charged over an extended period of time.
• Refreshed every few milliseconds 16

17. Dynamic MOS RAM Cell • DRAM consists of an array of memory cells with a single
MOSFET and a capacitor
• Memory cell also needs MOSFET for read and write gating to
operate the cell.
• Data input is connected to storage by a write control signal.
• Due to high packing density memory ICs the capacity of the
memory will continue to grow.
Dynamic Memory Organization
Merits
• Non-destructive read out: read out of a RAM does not
affect the content stored.
• Fast operating speed: access time can be as low as
150 ns with on chip decoding
• Low power dissipation: less than 1 mW per bit for
static RAM and less than 0.5 mW per bit for dynamic
RAM.
• Compatibility: common interface and technology
between sensing and decoding circuitry and the
storage element itself.
• Economy: MOS memories are more economical than
magnetic core for small and medium sized system.
17

18. Basic Structure of 16K Dynamic RAM
18

19. Programmable Logic Devices
• The programmable logic device or PLD is one kind of chip used to implement the
logic circuit. It includes a set of logic circuit elements that can be modified in several
ways.
• A PLD is looked like a black box that consists of programmable switches as well as
logic gates
Different types of PLDs
• SPLD-simple PLD (PLA & PAL),
• CPLD-complex PLD,
• FPGAs-field programmable gate arrays
There are three major types of combinational PLDs and they differ in the placement of
the programmable connections in the AND-OR array. They are
1.Programmable Read-Only Memory (PROM)
2. Programmable Logic Array (PLA)
3. Programmable Array Logic (PAL) 19

20. Configuration of PROM
A PROM consists of a set of fixed (non-programmable) AND array constructed as a
decoder and a programmable OR array. The programmable OR gates implement the
Boolean functions in sum of minterms.
Configuration of PLA
20

21. Configuration of PAL
Array logic
PLDs have hundreds of gates interconnected through hundreds of electronic fuses. It is
sometimes convenient to draw the internal logic of such device in a compact form
referred to as array logic.
Array logic Symbols
21

22. Implementation of Boolean Function using Programmable Logic Arrays(PLA)
1.Implement the following Boolean function using PLA. F1(A,B,C) = Σm(0,1,3,4)
F2(A,B,C) = Σm(1,2,3,4,5).
F1 = B’ C’ + A’ C F2 = A B’ + A’ C + A’B
22

23. PLA Programming Table
Product
Term
Inputs Outputs
A B C F1 F2
1 A’C 0 - 1 1 1
2 B’C’ - 0 0 1 -
3 AB’ 1 0 - - 1
4 A’B 0 1 - - 1
PLA Implementation
F1 = B’ C’ + A’ C
F2 = A B’ + A’ C + A’B
23

24. 2. Implement the following Boolean function using three inputs, four product terms
and two outputs using PLA. F1 = AB’ + AC + A’BC’ F2 = (AC + BC)’
PLA Programming Table
Produ
ct
Term
Inputs Outputs
A B C F1 F2
1 AB’ 1 0 - 1 -
2 AC 1 - 1 1 1
3 BC - 1 1 - 1
4 A’BC’ 0 1 0 1 -
PLA Implementation
24

25. 3. Implement the following Boolean function using 3 x 4 x 2 PLA.
F1(A,B,C) = Σm(0,1,2,4) F2(A,B,C) = Σm(0,5,6,7).
25

26. PLA Implementation
PLA Programming Table
Product
Term
Inputs Outputs
A B C F1 F2
1 AB 1 1 - 1 1
2 AC 1 - 1 1 1
3 BC - 1 1 1 -
4 A’B’C’ 0 0 0 - 1
26

27. 27

28. 1.A combinational circuit is defined by the functions
Implementation using Programmable Array Logic (PAL)
Implement the circuit using PAL
28

29. 29

30. Product
Term
‘AND’ Inputs
‘OR’ Outputs
A B C D W
1 ABC’ 1 1 0 - -
W = ABC’+A’B’CD’
2 A’B’CD’ 0 0 1 0 -
3 - - - - - -
4 A 1 - - - -
X = A+BCD
5 BCD - 1 1 1 -
6 - - - - - -
7 B’D’ - 0 - 0 -
Y = A’B+CD+B’D’
8 A’B 0 1 - - -
9 CD - - 1 1 -
10 AC’D’ 1 - 0 0 -
Z = W + AC’D’ +
A’B’C’D
11 W - - - - 1
12 A’B’C’D 0 0 0 1 -
PAL Programming Table
30

31. 2.Implement FULL Adder using PAL.
PAL PROGRAMMING TABLE
Product
Term
‘AND’ Inputs ‘OR’ Outputs
A B C
1 A’B’C 0 0 1
SUM =
A’B’C+A’BC+AB’C’+ABC
2 A’BC’ 0 1 0
3 AB’C’ 1 0 0
4 ABC 1 1 1
5 AB 1 1 -
CARRY = AB+BC+CA
6 BC - 1 1
7 CA 1 - 1
8 - - - - 31

32. Comparison between PROM, PLA, and PAL
S.No PROM PLA PAL
1
AND array is fixed and
OR array is
programmable
Both AND and OR
arrays are
programmable
OR array is fixed and AND
array is
programmable
2 Cheaper and simpler to
use Costliest and complex Cheaper and simpler
3 All minterms are
decoded
AND array can be
programmed to get
desired minterms
AND array can be
programmed to
get desired minterms
4
Only Boolean
functions in standard
SOP form can be
implemented using
PROM
Any Boolean
functions in SOP
form can be
implemented using
PLA
Any Boolean functions in
SOP form can be
implemented using PAL
32

33. FPGA (Field Programmable Gate Arrays)
• FPGAs are pre-fabricated silicon devices that can be
electrically programmed to become almost any kind of
digital circuit or system.
• Requires 3.3 V/5 V/upto 1.5 V.
• Very less cost of approx. 15$.
• Program is reloaded every time at power up i.e. need
reprogramming each time they are powered up.
• The architecture is complex.
• Larger capacity in terms of gate count.
• Manufacturers – Xilinx, Altera, Atmel, Lattice Semiconductor,
Actel, etc.
33

34. Structure and block diagram of FPGA
34

35. 35

36. 1.A combinational circuit is defined by the functions,
F1 (A, B, C) = ∑m (1, 3, 5)
F2 (A, B, C) = ∑m (5, 6, 7)
Implement the circuit with a PLA having 3 inputs, 3 product terms and 2 outputs.
FOR PRACTICE
36

37. 37

38. 2.Design a BCD to Excess-3 code converter and implement using suitable PLA.
38

39. 39

40. 40

41. 41

42. Logic Families – What is inside of a logic gate?
• A logic family is a collection of different integrated- circuit chips
that have similar input, output, and internal circuit characteristics,
but that perform different logic functions.
• Logic gates are made from transistors.
– RTL( Resistor-Transistor Logic) family gates are made from
resistors and bipolar transistors.
– DTL (Diode transistor logic) family gates are made from resistors
and diodes.
– TTL (Transistor-Transistor Logic) family gates are made from
bipolar transistors.
– ECL( Emitter coupled logic ) family gates are made from R,D & T.
– CMOS (Complementary Metal Oxide Semiconductor) family logic
gates are made from MOS transistors.
42

43. ➢ Fan in :
The number of inputs that the gate can handle properly without
disturbing the output level.
➢ Fan out :
The number of inputs that can driven simultaneously by the
output without disturbing the output level.
➢ Noise immunity :
Noise immunity is the ability of the logic circuit to tolerate the
noise voltage.
43

44. ➢ Noise Margin : The quantative measure of noise immunity is
called noise margin.
➢ Propagation Delay : The propagation delay of gate is the
average transition delay time for the signal to propagate from
input to output.It is measured in nanoseconds
Average Propagation Delay is calculated as, Tpd= (tPHL+tPLH)/2
Where tPHL= time taken by the output to go from High to Low
tPLH= time taken by the output to go from Low to High.
➢ Threshold Voltage : The voltage at which the circuit changes
from one state to another state
44

45. ➢ Operating Speed : The speed of operation of
the logic gate is the time that elapses between
giving input and getting output.
➢ Power Dissipation : The power dissipation is
defined as power needed by the logic circuit.
45

46. ➢ The collector ofthe transistor are tied together at the output
➢ The voltage levels for the circuit are 0.2v for the low level and
from 1 to 3.6v for the high level
CIRCUIT DIAGRAM 46

47. •• The input and Base are connected to VCC
•• Base-Emitter voltage VBE > 0.7v
•• Base-Emitter junction is forward biased
•• Base-Collector junction is forward biased
•• Transistor is “fully-ON” ( saturation region )
•• Max Collector current flows ( IC = Vcc/RL )
•• VCE = 0 ( ideal saturation )
•• VOUT = VCE = ”0″
•• Transistor operates as a “closed switch”
•• The input and Base are grounded ( 0v )
•• Base-Emitter voltage VBE < 0.7v
•• Base-Emitter junction is reverse biased
•• Base-Collector junction is reverse biased
•• Transistor is “fully-OFF” ( Cut-off region )
•• No Collector current flows ( IC = 0 )
•• VOUT = VCE = VCC = ”1″
•• Transistor operates as an “open switch”
47

48. Transistor NAND Gate
48

49. RTL Characteristics
It has a fan-out of
5.
Propagation delay is 25 ns.
Power dissipation is 12 mw.
Noise margin for low signal input is 0.4 v.
Poor noise immunity.
Low speed.
49

50. Circuit Diagram
TTL gates come in three different types of output configuration:
Open-collector output
Totem-pole output
Three-state output
50

51. Advantages of Totem-Pole Configuration
• The circuit power dissipation low.
• It provides very fast rise time waveforms at TTL output.
Disadvantages of Totem-Pole Configuration
1. TTL circuits suffer from internally generated current transients or current spikes
because of the totem-pole connection.
2. Totem-pole outputs cannot be wire ANDed
51

52. Characteristics
Power dissipation is 10mw.
It has fan-in of 8 and fan-out of 10.
Propagation time delay is 5-15nsec.
TTL has greater speed than RTL,DTL.
Less Noise immunity (Noise margin=0.4mV)
52

53. Circuit Diagram
➢ -0.9V logic 1(High)
➢ -1.7Vlogic 0(Low)
53

54. Advantages of ECL logic Family
➢ Current from Supply is always steady.
➢ Still used in super power computers
➢ Used in high-speed special purpose applications.
➢ It can be Wired ORed,
➢ No noise spikes are generated,
➢ Complementary Outputs are also available.
54

55. Disadvantages of ECL
➢ High cost.
➢ Low Noise Margin.
➢ Its negative supply voltage and logic levels are not
compatible with other logic levels.
➢ Problem of cooling.
➢ High power consumption
55

56. Important Characteristics of ECL logic Family
➢ Transistors never Saturate.
➢ Logic levels are negative. i.e.,
➢ -0.9V logic 1(High)
➢ -1.7Vlogic 0(Low)
➢ Noise Margin is less about 250mv(not reliable for heavy
industries)
➢ ECL circuits produce the output and its complement,
and therefore, eliminate the need for inverters.
56

57. ➢Fan-out is large because the output impedance is
low. It is about 25.
➢Power dissipation per gate is large, PD = 40 mW.
➢The total current flow in ECL is more or less
constant. So, no noise spikes will be internally
generated.
Important Characteristics of ECL logic Family
57

58. MOS Transistors – N-type MOSFET
• OFF (open circuit) : when gate is logical zero
• ON (short circuit) : when gate is logical one
58

59. MOS Transistors – P-type MOSFET
• OFF (open circuit) : when gate is logical one
• ON (short circuit) : when gate is logical zero
59

60. CMOS Logic Gates
60

61. Logic Gates
• Gates are basic digital devices.
– A gate takes one or more inputs and produces an output.
– Inputs are either 0 or 1.
• Although they may have very different values of voltage.
– Output is either 0 or 1.
– A logic gate’s operation is fully described by a truth table.
61

62. Inverter
62

63. Inverter
63

64. NAND – Not AND
64

65. NAND
65

66. NOR – Not OR
66

67. Non-inverting Buffer
67

68. AND Gate
68

69. OR Gate
69

70. HOME WORK PROBLEMS
1. A combinational circuit defined by the function F1(A,B,C)=∑m(3,5,6,7)&
F2 (A,B,C)= ∑m( 0,2,4,7) Implement the circuit with PLA having 3 inputs,4 Product terms
and 2 outputs.
2. Draw a PLA circuit to implement the functions F1 = AB + AC + ABC and F2 = (AC + AB +
BC)
3. Tabulate the PLA programming table for the four Boolean functions listed below.
Minimize the numbers of product terms.
A(x, y, z) = (1, 3, 5, 6)
B(x, y, z) = (0, 1, 6, 7)
C(x, y, z) = (3, 5)
D(x, y, z) = (1, 2, 4, 5, 7)
4. Realize the following function using PLA.F (w, x, y, z) = Π (0, 3, 5, 7, 12, 15) + d (2, 9).
5. Demonstrate the realization of the following function using PAL
F1(x, y, z) = ∑ (1, 2, 4, 5, 7). And F2(x, y, z) = ∑ (0,1,3,5,7).
70

71. STAY HOME…
STAY SAFE…
71