2. Types of Logic Circuits
Logic circuits can be:
Combinational Logic Circuits-outputs
depend only on current inputs
Sequential Logic Circuits-outputs
depends not only on current inputs but
also on the past sequence of inputs
7. Memory
We will add memory (or
registers) to our logic circuits.
This will allow us to design
sequential circuits.
8. Registers
We will represent registers with the
following block diagram
R
E
G
ps
ns
clock
reset
Clock and reset are control signals
Ns and ps are data signals
10. Sequential Systems
General Block Diagram
R
E
G
CL
F
CL
H Y
ps
ns
X
clock
reset
Input Vector
Output Vector
Next
State
Present
State
Feedback
Path
CL= Combinational Logic Cloud
Reg= D Registers
Clock
Reset
11. Sequential Systems
General Block Diagram
R
E
G
CL
F
CL
H Y
ps
ns
X
clock
reset
Input Vector
Output Vector
Next
State
Present
State
Feedback
Path
Clock
Reset
X is the input data vector
Y is the output data vector
12. Sequential Systems
Block Diagram
R
E
G
CL
F
CL
H Y
ps
ns
X
clock
reset
Input Vector
Output Vector
Next
State
Present
State
Feedback
Path
Clock
Reset
Ns is the next state data vector
Ps is the present state data vector
13. Sequential Systems
Block Diagram
R
E
G
CL
F
CL
H Y
ps
ns
X
clock
reset
Input Vector
Output Vector
Next
State
Present
State
Feedback
Path
Clock
Reset
Notice we have a feedback path which
combines the ps data vector with the
input vector to generate a new ns data
vector.
14. Sequential Systems
Block Diagram
R
E
G
CL
F
CL
H Y
ps
ns
X
clock
reset
Input Vector
Output Vector
Next
State
Present
State
Feedback
Path
Clock
Reset
,
s s
s
n F X p
Y H p
Mathematically, we say
Or, ns is a function F of X and ps
and Y is a function H of ps.
18. Moore FSM
General Block Diagram
R
E
G
CL
F
CL
H Y
ps
ns
X
clock
reset
Input Vector
Output Vector
Next
State
Present
State
Feedback
Path
CL= Combinational Logic Cloud
Reg= D Registers
Clock
Reset
19. Moore FSM
State Equations
R
E
G
CL
F
CL
H Y
ps
ns
X
clock
reset
Input Vector
Output Vector
Next
State
Present
State
Feedback
Path
Clock
Reset
,
s s
s
n F X p
Y H p
State Equations
20. R
E
G
CL
F
CL
H Y
ps
ns
X
clock
reset
Mealy FSM
Block Diagram and State Equations
,
,
s s
s
n F X p
Y H X p
Input Vector Output Vector
Next
State
Present
State
Feedback
Path
Output Y is also a function
of input X
26. Memory Devices
Data Latch (D-latch)
Flip-flops (edge triggered)
D-FF, D Register
JK-FF
T-FF
27. D-FF Positive Edge Triggered
Block Diagram
Q
Q
SET
CLR
D
Qn+1
D
Clk
Pre
Rst
Symbol
4 inputs: D,Clk,Pre,Rst
One output: Q
D = Data Input
Clk = Clock Input
Pre = Preset Input
Rst = Reset Input
29. D-FF Truth Table
Q
Q
SET
CLR
D
Qn+1
D
Clk
Pre
Rst
D Clk
d d 1 0 0
d d 0 1 1
d 0 1 1
d 1 1 1
0 1 1 0
1 1 1 1
Symbol
Equation (rising clock)
Truth Table
Pre Rst 1
n
Q
n
Q
n
Q
1
n n
Q D
Pre= Preset Input (active low)
Rst = Reset Input (active low)
Highest priority
30. D-FF Truth Table
Q
Q
SET
CLR
D
Qn+1
D
Clk
Pre
Rst
D Clk
d d 1 0 0
d d 0 1 1
d 0 1 1
d 1 1 1
0 1 1 0
1 1 1 1
Symbol
Equation (rising clock)
Truth Table
Pre Rst 1
n
Q
n
Q
n
Q
1
n n
Q D
D = Data Input
Clk = Clock input
Qn = Register Output
43. Example – 2-bit Down Counter
Excitation
Equations
1 1 0
0 0
1 1
0 0
s s s
s s
s
s
n p p
n p
Y p
Y p
44. Recall Moore FSM
R
E
G
CL
F
CL
H Y
ps
ns
X
clock
reset
Input Vector
Output Vector
Next
State
Present
State
Feedback
Path
Clock
Reset
,
s s
s
n F X p
Y H p
State Equations
51. Example – 2-bit Up/Down Counter
Excitation
Equations
1 1 0
0 0
1 1
0 0
s s s
s s
s
s
n p p upn
n p
Y p
Y p
52. Recall Moore FSM
R
E
G
CL
F
CL
H Y
ps
ns
X
clock
reset
Input Vector
Output Vector
Next
State
Present
State
Feedback
Path
Clock
Reset
,
s s
s
n F X p
Y H p
State Equations
55. Example 5– 3-bit Arbitrary Counter
Design a 3-bit arbitrary counter that will
count in the following sequence
3,2,3,1,2,3
If a state is not used reset it to state zero.
• How may states do we have?
• How many registers do we need?
• How many bits do we need for Y?
59. Example – 2-bit Arbitrary Counter
Develop Excitation Equations -- F Logic
2 2 1 0
1 2 1 0
0 2 0
s s s s
s s s s
s s s
n p p p
n p p p
n p p
61. Example – 2-bit Arbitrary Counter
Excitation Equations -- H Logic
1 2 1 0 1 0
0 2 1 0
s s s s s
s s s
y p p p p p
y p p p
62. Recall Moore FSM
R
E
G
CL
F
CL
H Y
ps
ns
X
clock
reset
Input Vector
Output Vector
Next
State
Present
State
Feedback
Path
Clock
Reset
,
s s
s
n F X p
Y H p
State Equations
66. Example 5– 2-bit Up/Down Counter with Active Low Enable and
Synchronous RESET (SRESET)
State Diagram
Clock is implied S0
s3
S2
S1
Resetn
upn en srn
en srn
upn en srn
en srn
en srn
upn en srn
upn en srn
srn
upn en srn
upn en srn
srn
upn en srn
upn en srn
en srn
67. Example – 2-bit Up/Down Counter with
Enable and SRESET
Functional Table
srn en upn Function
0 d d Synchronous Reset (sreset)
1 1 d Hold
1 0 0 Count Up
1 0 1 Count Down
Highest Level of Priority Lowest Level of Priority
69. Truth Table (5 variables!!)
Srn En Upn Ps1 Ps0 Ns0 Ns1 # of Rows
0 d d d d 0 0 16
1 1 d Ps1 Ps0 Ps1 Ps0 8
1 0 0 0 0 0 1 1
1 0 0 0 1 1 0 1
1 0 0 1 0 1 1 1
1 0 0 1 1 0 0 1
1 0 1 0 0 1 1 1
1 0 1 0 1 0 0 1
1 0 1 1 0 0 1 1
1 0 1 1 1 1 1 1
32
Although, we could design this circuit directly from the truth table
we will use design partitioning.
70. Moore FSM Architecture
R
E
G
CL
F
CL
H Y
ps
ns
X
clock
reset
Input Vector
Output Vector
Next
State
Present
State
Feedback
Path
,
s s
s
n F X p
Y H p
82. Kmaps for NS1 and NS0
P1P0
T
00 01 11 10
0 1 1 1
1 1
NS1
1 0 1 1 0
s s s s
ns T p T p p p
P1P0
T
00 01 11 10
0 1 1
1 1 1
NS0
0 1 0 1 0
s s s s
ns T p T p p p
83. Truth Table and Equations for Y
Ps1 Ps0 Y1 Y0
0 0 0 0
0 1 0 1
1 0 1 0
1 1 1 1
Truth Table
1 1 0 0
;
Y PS Y PS
By Inspection
Recall, Moore FSM, so Y will
Not be a function of T
88. D-FF Truth Table
Qn follows D on Rising Edge of CLK
Q
Q
SET
CLR
D
Qn+1
D
Clk
Pre
Rst
D Clk
d d 1 0 0
d d 0 1 1
d 0 1 1
d 1 1 1
0 1 1 0
1 1 1 1
Symbol
Equation (rising clock)
Truth Table
Pre Rst 1
n
Q
n
Q
n
Q
1
n n
Q D
D = Data Input
Clk = Clock input
Qn = Register Output
89. T-FF (Toggle)
Changes state on every tick of CLK
T Clk
D d 1 0 0
D d 0 1 1
d 0 1 1
d 1 1 1
0 1 1
1 1 1
Symbol
Equation (rising clock)
Truth Table
Pre Rst 1
n
Q
n
Q
n
Q
1
n n n
Q TQ TQ
T
Clk
Pre
Rst
Q
Q
SET
CL
R
T
Qn+1
n
Q
n
Q
90. SR-FF
Set =>Qn=1
Reset=>Qn=0
S R Clk
d d d 1 0 0
d d d 0 1 1
d d 0 1 1
d d 1 1 1
0 0 1 1
0 1 1 1 0
1 0 1 1 1
1 1 1 1 ???
n
Q
Symbol
Equation (rising clock)
Truth Table
Pre Rst 1
n
Q
n
Q
n
Q
Rst
Q
Q
SET
CLR
S
R
S
Clk
R
Pre
Qn+1
1
n n
Q SRQ SR
91. JK-FF
J K Clk
d d d 1 0 0
d d d 0 1 1
d d 0 1 1
d d 1 1 1
0 0 1 1
0 1 1 1 0
1 0 1 1 1
1 1 1 1
n
Q
Symbol
Equation (rising clock)
Truth Table
Pre Rst 1
n
Q
n
Q
1
n n n
Q JQ KQ
n
Q
n
Q
Rst
J
Q
Q
K
SET
CLR
J
Clk
K
Pre
Qn+1
92. Example: Design a JK-FF using
only Logic and a D-FF
J K Clk
d d d 1 0 0
d d d 0 1 1
d d 0 1 1
d d 1 1 1
0 0 1 1
0 1 1 1 0
1 0 1 1 1
1 1 1 1
n
Q
Symbol
Truth Table
Pre Rst 1
n
Q
n
Q
n
Q
n
Q
Rst
J
Q
Q
K
SET
CLR
J
Clk
K
Pre
Qn+1
93. Example
S0 S1
Reset
0 1
J K
J
K
J K PS NS Y
0 0 S0 S0 0
0 0 S1 S1 1
0 1 S0 S0 0
0 1 S1 S0 1
1 0 S0 S1 0
1 0 S1 S1 1
1 1 S0 S1 0
1 1 S1 S0 1
State Diagram State Table
Let s0=0 and s1=1
94. JK-FF
J K PS NS Y
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 0 1
1 0 0 1 0
1 0 1 1 1
1 1 0 1 0
1 1 1 0 1
Truth Table
s s s
s
n J p K p
Y p
Logic Equations
95. Recall Moore FSM
State Equations
R
E
G
CL
F
CL
H Y
ps
ns
X
clock
reset
Input Vector
Output Vector
Next
State
Present
State
Feedback
Path
Clock
Reset
,
s s
s
n F X p
Y H p
State Equations
96. JK Example
Circuit Schematic
F Logic D-Register
H Logic
(buffer)
R
E
G
CL
F
CL
H Y
ps
ns
X
clock
reset
X input ns ps
Block Diagram
100. D-Latch
Truth Table
D E
d d 1 0 0
d d 0 1 1
d 0 1 1
0 1 1 1 0
1 1 1 1 1
Symbol Truth Table
Pre Rst 1
n
Q
n
Q
D
E
Pre
Rst
Q
Q
SET
CLR
D
E
Qn+1
101. D-Latch
State Equations
D E
d d 1 0 0
d d 0 1 1
d 0 1 1
0 1 1 1 0
1 1 1 1 1
Symbol
Equation (level clock)
Truth Table
Pre Rst 1
n
Q
n
Q
1
n n n
Q EQ ED
D
E
Pre
Rst
Q
Q
SET
CLR
D
E
Qn+1
102. SR-Latch
State Equations
S R
d d 1 0 0
d d 0 1 1
0 0 1 1
0 1 1 1 0
1 0 1 1 1
1 1 1 1 ???
Symbol
Equation (level clock)
Truth Table
Pre Rst 1
n
Q
n
Q
1
n n
Q SRQ SR
S
R
Pre
Rst
Q
Q
SET
CLR
S
R
Qn+1
106. Shift Registers
Logic Design which manipulates the
bit position of binary data by
shifting it to the left or right.
Major application
Serial Data to Parallel Data converters
107. Example
Design a three-bit shift register with
the following functions
S1 S0 Function
0 0 Synchronous Reset (sreset)
0 1 Shift Right
1 0 Shift Left
1 1 No Shift