1. BY:
Prof. Ruby Pandey
Computer Science Department
SISTec, Bhopal
rubypandey@sistec.ac.in
INSTRUCTION PIPELINING1
SISTec, Bhopal

2. Instruction Pipeline
 An instruction pipeline reads consecutive
instruction from memory while previous
instruction are executed in various stages of
pipeline.
 Instruction execution sequence:
 Instruction fetch
 Instruction decode
 Calculate the effective address
 Fetch the operand
 Execute the instruction
 Store the result
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3. Difficulties in instruction pipeline for
achieving the maximum rate
 Different stages of pipeline may takes different
times to execute.
 Some instruction may skip some stages for
example: immediate addressing and register
addressing may not require effective address
calculation
 The instruction fetch stage and operand fetch
stage will need to access memory at the same
time. In this case one have to wait while other
stage finishes its task.
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4. Combining the stages
 Fetch the Instruction
 Decode and Calculate EA
 Fetch Operand
 Execute and Write Back
 Assume that the processor has the separate
Instruction and data memories so that FI and FO
stage can be processed together.
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5. Timing diagram of Instruction
cycle
Step
s
1 2 3 4 5 6 7 8 9 10
1 FI DA FO EX
2 FI DA FO EX
3 FI DA FO EX
4 FI DA FO EX
5 FI DA FO EX
In
st
ru
ct
io
n
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6. Timing of Instruction pipeline
Step
s
1 2 3 4 5 6 7 8 9 10 11 12 13
1 FI DA FO EX
2 FI DA FO EX
3 FI DA FO EX
4 FI - - FI DA FO EX
5 FI DA FO EX
6 FI DA FO EX
7 FI DA FO EX
Instruction 3 is a branch
instruction
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7. Another Difficulty
 Delay may occur in the pipeline if EX segment
needs to store the result of the operation in the
data memory while the FO segment needs to
fetch an operand. In that case segment FO
must wait until segment EX has finished its
operation.
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8. Pipeline Conflicts
 Resource conflicts
 Data Dependency or Data Hazards
 Branch Difficulties
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9. Resource Conflicts
 It may be caused by access to memory by two
different instruction.
 Example: X=Y+Z
 R1 Y
 R2 R1+Z
 XR2
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10. Conflict in 3 and 4 cycle
Steps 1 2 3 4 5 6 7 8
1 FI DA FO EX
2 FI DA FO EX
3 * * FI DA FO EX
Above Problem be handled by :
Using separate instruction and data Memories
By Stalling of pipe
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11. Data Dependencies
 Conflicts arise when an Instruction depends on
the result of the previous instruction.
 Example :
 Inst 1 :X=Y+Z Inst 2: X1=X+1
1 2 3 4 5 6
1 FI DA FO EX
2 FI DA * FO EX
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12. Shuffling the instruction
 Inst 1: t=3 Inst 2:X=Y+Z Inst
3:X1=X+1
 After Shuffling
 Inst 1:X=Y+Z Inst 2: t=3 Inst 3: X1=X+1
1 2 3 4 5 6
1 FI DA FO EX
2 FI DA FO EX
3 FI DA FO EX
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13. DELAYED LOAD
 1. Load : R1 M[Address 1]
 2. Load : R2 M[Address 2]
 3. ADD : R3R1 + R2
 4. STORE : M[Address 3]  R3
1 2 3 4 5 6 7
1 FI DA FO EX
2 FI DA FO EX
3 FI DA FO EX
4 FI DA FO EX
Conflict
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14. 1 2 3 4 5 6 7 8
1 FI DA FO EX
2 FI DA FO EX
3(NOP
)
FI DA FO EX
4 FI DA FO EX
5 FI DA FO EX
Delayed Load
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15. Operand Forwarding
 Example :
 Inst 1 :X=Y+Z Inst 2: X1=X+1
1 2 3 4 5
1 FI DA FO EX
2 FI DA FO EX
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16. Branch Difficulties
Step
s
1 2 3 4 5 6 7 8 9 10 11 12 13
1 FI DA FO EX
2 FI DA FO EX
3 FI DA FO EX
4 FI - - FI DA FO EX
5 FI DA FO EX
6 FI DA FO EX
7 FI DA FO EX
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17. Types of Branching
 Conditional
 Unconditional
 Handling of Branch
 Prefetch target Instruction
 Branch target Buffer
 Loop Buffer
 Branch Prediction
 Delayed Branch
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18. Prefetch Target Instruction
 For handling conditional Branching
 It stores the address of the target Instruction
and branch Instruction
 If the condition is successful then it continuous
from target Instruction

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19. Branch Target Buffer
 The BTB is an associative memory
 The BTB included in fetch segment of pipeline
 BTB Consist of the address of the previously
executed branch instruction and target instruction
 When the pipeline decode the branch Instruction it
searches in BTB for the address of the instruction.
 If it is found it continuous from the new path.
 If it is not found the pipeline shifts to a new
instruction stream and store the target Instruction
in BTB.
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20. Delayed Branch
 It rearranges the instruction and adding NOP
after a branch instruction.
 Example:
 Load from memory to R1
 Increment R2
 Add R3 to R4
 Subtract R5 from R6
 Branch to address X
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21. By NOP
1 2 3 4 5 6 7 8 9 10
1.Load I A E
2. INC I A E
3. ADD I A E
4. SUB I A E
5. BR
to X
I A E
6. NOP I A E
7. NOP I A E
8. Inst
in X
I A E
I : Inst Fetch A: ALU Operation E: Execute
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22. By Delayed branch
1 2 3 4 5 6 7 8
1.
LOAD
I A E
2. INC I A E
3. BR
TO X
I A E
4. ADD I A E
5. SUB I A E
6. INST
IN X
I A E
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23. Topics Left
 Interconnection Networks
 Single Bus Based Topology
 Crossbar network
 Multistage Network
 Hypercube
 Mesh Network
 Tree Network
 Vector Processor
 Array Processor
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24. Thank You
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