This document discusses instruction pipelining and various techniques used to handle hazards that can occur in pipelined processors. It describes a 6-stage instruction pipeline consisting of fetch, decode, calculate operands, fetch operands, execute, and write-back stages. There are three main types of hazards: resource hazards which occur when instructions need the same processor resource; data hazards which occur when an instruction uses a value not yet ready from a previous instruction; and control hazards which occur when the program flow changes due to a branch. Solutions to handle these hazards include branch prediction, delayed branching, pipeline stalls, and maintaining multiple instruction streams.

1. Afjal Hossain | Emran
Hossain
Raihan Mahmud| Rejuanul
Haque
Toriqul Islam
Department of Software
Instruction Pipelining
SWE-311

2. Pipelining
 A technique used in advanced
microprocessors where the microprocessor
begins executing a second instruction before
the first has been completed.
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3. Two Stage Instruction Pipeline
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4. Six Stage Instruction Pipeline
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5. Six Stage Instruction Pipeline
 Fetch Instruction (FI): Read the next expected
introduction into a buffer
 Decode Instruction (DI): Determine the opcode and the
operand specifiers
 Calculate Operands (CO): Calculate the effective address
of each source operand. This may involve displacement,
register indirect, indirect or other forms of address
calculations.
 Fetch Operands (FO): Fetch each operand from memory.
Operands in register need not be fetched.
 Execute Instruction (EI): Perform the indicated operation
and store the result, if any, in the specified destination
operand location.
 Write Operand (WO): Store result in memory5

6. Types of hazards
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Resource Data Control
HAZARD

7. Resource Hazards
 Two (or more) instructions in pipeline need
same resource
 Executed in serial rather than parallel for part
of pipeline
 Also called structural hazard
 E.g. Assume simplified five-stage pipeline
 Each stage takes one clock cycle
 Ideal case is new instruction enters pipeline
each clock cycle
 Assume main memory has single ports
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8. Data Hazards
 Attempt to use item before it is ready
 Instruction depends on result of prior
instruction still in the pipeline
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9. Types of Data Hazard
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RAW WAR WAW
DATA
HAZARD

10. Read After Write (RAW)
 It is also known as True dependency
 An instruction modifies a register or memory
location
 Hazard if read takes place before write
complete
 B tries to read a register before A has written
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11. Write After Read (WAR)
 It is also known as Anti dependency
 An instruction reads a register or memory
location
 Hazard if write completes before read takes
place
 B tries to write a register before A has read it
 In this case, A uses the new (incorrect) value
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12. Write After Write (WAW)
 It is also known as Output dependency
 Two instructions both write to same location
 Hazard if writes take place in reverse of order
intended sequence
 B tries to write an operand before A has
written it
 After instruction B has executed, the value of
the register should be B's result, but A's result12

13. Control Hazard
 Instructions that disrupt the sequential flow of
control present problems for pipelines.
 Also known as branch hazard
 Control hazards occur because the PC
following a control instruction is not known
until control instruction computes if branch
should be taken or not.
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14. 14

15. Types of Control hazards
o Unconditional branches
o Conditional branches
o Indirect branches
o Procedure calls
o Procedure returns
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16. Dealing with Branches
 Multiple Streams
 Prefetch Branch Target
 Loop buffer
 Branch prediction
 Delayed branching
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17. Solutions for Control Hazards
 Pipeline stall cycles
 Branch delay slots
 Branch prediction
 Indirect branch prediction
 Return address stack (RAS)
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18. Multiple Streams
 Have two pipelines
 Prefetch each branch into a separate pipeline
 Use appropriate pipeline
 Leads to bus & register contention
 Multiple branches lead to further pipelines
being needed
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19. Prefetch Branch Target
 Target of branch is prefetched in addition to
instructions following branch
 Keep target until branch is executed
 Used by IBM 360/91
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20. Loop Buffer
 Very fast memory
 Maintained by fetch stage of pipeline
 Check buffer before fetching from memory
 Very good for small loops or jumps
 Used by CRAY-1
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21. Loop Buffer Diagram
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22. Prediction
 Easy to fetch multiple (consecutive)
instructions per cycle
 Essentially speculating on sequential flow
 Jump: unconditional change of control flow
 Always taken
 Branch: conditional change of control flow
 Taken typically ~50% of the time in applications
 Backward: 30% of the Branch  80% taken = ~24%
 Forward: 70% of the Branch  40% taken = ~28%
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23. What is Branch Prediction
 In a computer architecture, a branch predictor
is a digital circuit that tries to guess which way
a branch. Will go before this is known
definitively. The purpose of the branch
predictor is to improve the flow in the
instruction pipeline.
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24. Branch Prediction Techniques
 Static Branch Prediction
 Some branch instructions predicted as taken and
others as not taken
 End or program loop
 Beginning of program loop
 Hardware or compiler
 Dynamic Branch Prediction
 Bitmap for Lower bits of PC address
 Says whether or not branch taken last time
 If Instr is Branch, predict and update the table
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25.  Predict by Opcode
 Some instructions are more likely to result in a jump
than theirs
 Can get up to 75% success
 Taken/Not taken switch
 Based on previous history
 Good for loops
 Refined by two-level or correlation-based branch
history
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26. Branch Prediction Flowchart
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