>> Intel currently manufactures chips using a 14-nanometer process, and is preparing its move to 10nm later this year or early next. The number refers approximately to the smallest circuit dimensions etched on each chip, and smaller circuits mean faster chips and less power use. The new techniques could allow Intel to ensure the continuation of Moore\'s Law, which recently turned 50, until at least the 7nm process, which Kanter estimates will come into production in 2017 or 2018. Moore\'s Law predicts that transistor density will double approximately every two years, allowing chips to get progressively faster and cheaper. But with transistors reaching atomic scale, electricity leakage and power management become more challenging. Intel has introduced technologies such as strained silicon, high-k metal gate and FinFET -- in which transistors are built upward in a 3D fashion instead of laying flat -- to keep Moore\'s Law going. In the coming years, Kanter predicts it will combine silicon with materials such as strained germanium, or indium-gallium-arsenide, which part of a family III-V materials based on elements from the third and fifth columns of the periodic table. The III-V materials are being considered as eventual successors to silicon because they are better conductors of electrons. Initially, the materials are expected to be used alongside silicon. Intel is already using silicon alternatives like hafnium in its chips. Also likely for future chips is a new transistor and gate structure based on quantum-well FETs (QWFETs), which Intel has been researching for a little under a decade. Here, electrons are sandwiched between III-V materials and gates on each side, ensuring the electrons move in the right direction. The behavior of the charge becomes tightly controlled by the combination of the geometry and materials, and as a result transistors perform better. Kanter said that the new technologies are the best options available for cramming still more transistors onto chips. Other required technologies, such as EUV (extreme ultraviolet) lithography, are not yet available from tool makers. Intel has instead taken to techniques like triple-patterning to make sure it can create chips with fewer defects. It ran into trouble with its 14-nm process, which led to a delay in the shipment of chips for PC, mobile and servers. Solution >> Intel currently manufactures chips using a 14-nanometer process, and is preparing its move to 10nm later this year or early next. The number refers approximately to the smallest circuit dimensions etched on each chip, and smaller circuits mean faster chips and less power use. The new techniques could allow Intel to ensure the continuation of Moore\'s Law, which recently turned 50, until at least the 7nm process, which Kanter estimates will come into production in 2017 or 2018. Moore\'s Law predicts that transistor density will double approximately every two years, allowing chips to get progressively faster and cheaper.

1. >>
Intel currently manufactures chips using a 14-nanometer process, and is preparing its move to
10nm later this year or early next. The number refers approximately to the smallest circuit
dimensions etched on each chip, and smaller circuits mean faster chips and less power use.
The new techniques could allow Intel to ensure the continuation of Moore's Law, which recently
turned 50, until at least the 7nm process, which Kanter estimates will come into production in
2017 or 2018.
Moore's Law predicts that transistor density will double approximately every two years,
allowing chips to get progressively faster and cheaper. But with transistors reaching atomic
scale, electricity leakage and power management become more challenging.
Intel has introduced technologies such as strained silicon, high-k metal gate and FinFET -- in
which transistors are built upward in a 3D fashion instead of laying flat -- to keep Moore's Law
going.
In the coming years, Kanter predicts it will combine silicon with materials such as strained
germanium, or indium-gallium-arsenide, which part of a family III-V materials based on
elements from the third and fifth columns of the periodic table.
The III-V materials are being considered as eventual successors to silicon because they are better
conductors of electrons. Initially, the materials are expected to be used alongside silicon. Intel is
already using silicon alternatives like hafnium in its chips.
Also likely for future chips is a new transistor and gate structure based on quantum-well FETs
(QWFETs), which Intel has been researching for a little under a decade. Here, electrons are
sandwiched between III-V materials and gates on each side, ensuring the electrons move in the
right direction. The behavior of the charge becomes tightly controlled by the combination of the
geometry and materials, and as a result transistors perform better.
Kanter said that the new technologies are the best options available for cramming still more
transistors onto chips.
Other required technologies, such as EUV (extreme ultraviolet) lithography, are not yet available
from tool makers. Intel has instead taken to techniques like triple-patterning to make sure it can
create chips with fewer defects. It ran into trouble with its 14-nm process, which led to a delay in
the shipment of chips for PC, mobile and servers.
Solution
>>
Intel currently manufactures chips using a 14-nanometer process, and is preparing its move to

2. 10nm later this year or early next. The number refers approximately to the smallest circuit
dimensions etched on each chip, and smaller circuits mean faster chips and less power use.
The new techniques could allow Intel to ensure the continuation of Moore's Law, which recently
turned 50, until at least the 7nm process, which Kanter estimates will come into production in
2017 or 2018.
Moore's Law predicts that transistor density will double approximately every two years,
allowing chips to get progressively faster and cheaper. But with transistors reaching atomic
scale, electricity leakage and power management become more challenging.
Intel has introduced technologies such as strained silicon, high-k metal gate and FinFET -- in
which transistors are built upward in a 3D fashion instead of laying flat -- to keep Moore's Law
going.
In the coming years, Kanter predicts it will combine silicon with materials such as strained
germanium, or indium-gallium-arsenide, which part of a family III-V materials based on
elements from the third and fifth columns of the periodic table.
The III-V materials are being considered as eventual successors to silicon because they are better
conductors of electrons. Initially, the materials are expected to be used alongside silicon. Intel is
already using silicon alternatives like hafnium in its chips.
Also likely for future chips is a new transistor and gate structure based on quantum-well FETs
(QWFETs), which Intel has been researching for a little under a decade. Here, electrons are
sandwiched between III-V materials and gates on each side, ensuring the electrons move in the
right direction. The behavior of the charge becomes tightly controlled by the combination of the
geometry and materials, and as a result transistors perform better.
Kanter said that the new technologies are the best options available for cramming still more
transistors onto chips.
Other required technologies, such as EUV (extreme ultraviolet) lithography, are not yet available
from tool makers. Intel has instead taken to techniques like triple-patterning to make sure it can
create chips with fewer defects. It ran into trouble with its 14-nm process, which led to a delay in
the shipment of chips for PC, mobile and servers.