Project report

1. 1
Graphene Based Transistors for
Digital & Analog Application
-A Simulation Study
By
Vishal Anand (1204059)
Agam Kumar Gupta (1204056)
Abhishek Anand (1204055)
UNDER THE GUIDANCE
OF
Dr. M.W. Akram
DEPARTMENT OF
ELECTRONICS & COMMUNICATION
NATIONAL INSTITUTE OF TECHNOLOGY, PATNA
2012-2016

2. 2
The Undersigned Certify that Vishal Anand, Roll No. 1204059, Agam Kumar
Gupta, Roll No. 1204056 and Abhishek Anand, Roll No.1204055 are registered
students for the Bachelor’s Program in department of Electronics &
Communication engineering at NIT Patna have successfully completed their
project entitled “Graphene Based Transistors for Digital & Analog Application:
A Simulation Study” under our supervision and guidance.
During the Project period they showed keen interest and sincerity towards
accomplishment of the project. We wish them success in all their future
endeavors.
Date: 19|05|2016 Dr. M.W. Akram
Electronics & Comm. Engineering
NIT Patna
CERTIFICATE

3. 3
ACKNOWLEDGEMENT
First of all we would like to express our deep gratitude towards our advisor and guide
Dr. M.W. Akram who has always been a guiding force behind this project work. His
highly influential personality has provided us constant encouragement to tackle any difficult
task assigned. We are indebted to him for his invaluable advice and for propelling us further
in every aspect of our academic life. His depths of knowledge, crystal clear concepts have
made our academic journey a cake walk. We consider it our good fortune to have got an
opportunity to work with such a wonderful personality.
We express our gratitude to Dr. Gayadhar Pradhan, Head of Electronics & Communication
Engineering for their valuable guidance and support to carry out this work.
We are especially indebted to our parents for their love, sacrifice, and support. They are
our first teachers after we came to this world and have always been mile stones to lead us a
disciplined life.

4. 4
ABSTRACT
We have studied about Graphene in the form of Nano-ribbons. We have also
discussed about its application in designing of devices. We have dealt with
Graphene Nano-ribbons FETS & Graphene based transistors. We prefer Graphene
devices over CMOS and other technologies due to its atomic thickness, high
mobility at room temperature, high velocity at high electric field and large current
density.
Device modelling and simulation are required as they allow to predict the device
behavior, understand the physical mechanisms underlying the device operation and
test the impact of device design parameters on the device performance (device
optimization).
For this purpose we have used Nano TCAD ViDES which is an open source
simulation software. Forplotting of graph we have used ORIGIN software and for
extracting data from already published papers and thus comparing it with our data
we have used ‘Plot Digitizer’.
Nano TCAD ViDES has already designed models of different structures of
Graphene. Various parameters are already defined in its script file. If any other
parameter is desired then it can be added in the script file by writing the codefor it
in python.

5. 5

7. CHAPTER 1
Motivation
1.1 Moore’s Law
Moore's law is the observation that the number of transistors in a dense integrated
circuit doubles approximately every two years. The observation is named after Gordon E.
Moore, the co-founder of Intel and Fairchild Semiconductor, whose 1965 paper described
a doubling every year in the number of components per integrated circuit. The period is often
quoted as 18 months because of Intel executive David House, who predicted that chip
performance would double every 18 months (being a combination of the effect of more
transistors and the transistors being faster).[1]
Fig 1.1 Graph representing Moore’s Law and subsequent decrease in channel length

8. 1.2 Limitation
Every engineer is worried whether Moore's Law (that the density of transistors will double
every two years) can be extended forever. So far, merely scaling to smaller sizes has kept
Moore's Law in play, but now that we are approaching the atomic scale, many see the
handwriting on the wall: When you get down to one atom per memory cell, Moore's Law has
to end ?
Many other factors are involved besides size. Scaling is but one hurdle Moore's Law has to
clear. A few years ago, the semiconductor industry realized that energy-efficiency can be
improved quite a bit, but instead of traditional scaling one must rely on new, clever tricks,
including micro-architectural restructuring.
Thus Moore's Law is no longer just about making transistors smaller, but about continuing to
increase computational capacity in other ways that face new problems, some of which
engineers have never faced before. Multicore parallel processors is not the answer either,
because ultimately they face the same problems, according to Markov. The answer is
exploiting the limits to Moore's Law that are not so limiting.
Fig 1.2 Limitation of Moore’s Law

9. Chapter 2
Introduction
2.0 Beyond C-MOS
Following the limitations of Moore’s Law, we will have to find out a way out. As we have to
work on the Nano-level along with increased and optimized device performance we will have
to consider some other methods. Now the option left for us is to follow either of the two
methods given below:-
 New Device Structure
 New Channel Material
Fig 2.0 Flowchart describing process flow.
TWO
OPTIONS
NEW DEVICE
STRUCTURE
FinFET
NEW
CHANNEL
MATERIAL
GRAPHENE
NANO
RIBBON

10. 2.0.1 New Device Structure
Introduction of new device structure can help our devices to perform better. One of the latest
device structure is the FIN-FET. In this kind of Field Effect Transistor, the channel is
surrounded by the gate on all the three sides. The main characteristic of the FIN-FET is that it
has a conducting channel wrapped by a thin silicon "fin" from which it gains its name. The
thickness of the fin determines the effective channel length of the device.
In terms of its structure, it typically has a vertical fin on a substrate which runs between a larger
drain and source area. This protrudes vertically above the substrate as a fin. The gate orientation
is at right angles to the vertical fin. And to traverse from one side of the fin to the other it wraps
over the fin, enabling it to interface with three side of the fin or channel.
This form of gate structure provides improved electrical control over the channel conduction
and it helps reduce leakage current levels and overcomes some other short-channel effects.
Fig 2.0.1 FinFET Device Structure
2.0.2 New ChannelMaterial
We can introduce new materials in the channel of the device so as to increase the performance
of the device. One such material is GRAPHENE [2, 3, 4 ].
Fig 2.0.2 Graphene layer

11. Chapter 3
3.0 Introduction to Graphene
Graphene is an allotrope of carbon in the form of a two-dimensional, atomic-scale, hexagonal
lattice in which one atom forms each vertex [1, 5].It is the basic structural element of other
allotropes, including graphite, charcoal, carbon nanotubes and fullerenes. Scientists have
theorized about graphene for decades. It is quite likely that graphene was unknowingly
produced in small quantities for centuries through the use of pencils and other similar
applications of graphite, but it was first measurably produced and isolated in 2004.Research
was informed by existing theoretical descriptions of its composition, structure and properties.
High-quality graphene proved to be surprisingly easy to isolate, making more research
possible.
Graphene is a two –dimensional sheet of sp2 bonded carbon atoms arranged in a honeycomb
crystal structure with two carbon atoms in each unit cell.
Fig 3.0.1 Hybridisation of Carbon in Graphene

12. Fig 3.0.2 Graphene sheet
3.1 Fabricationof Graphene
Among the aforementioned applications, many require the fabrication of electronic devices,
such as transistors, photo detectors and sensors. This section briefly reviews the most
commonly employed forms of graphene device structures and their general fabrication
processes.
The most commonly used device structures are summarized in Figure 3.1. Back gated
devices, with silicon as a back gate and SiO2 as the gate dielectrics (Figure 3.1(a), are widely
used in graphene research. First graphene is transferred (e.g. by mechanical exfoliation) [6]
on to SiO2/highly conducting silicon substrates. The normally used thickness of SiO2 is ≈300
nm or 90 nm for easy identification of graphene under optical microscope. Then optical or
electron beam lithography is used to create patterns on graphene, followed by Ar or
O2 plasma etching to etch away the unnecessary parts (Figure 3.1(a). Another lithography step
is used to pattern the metal source/drain of the devices, which is done by evaporation or
sputtering [7-9]. In many cases thermal annealing is necessary to remove resistant residues
and improve the contacts. In such a device, the back gate is used to globally adjust the carrier
type and concentration (or equivalently, Fermi energy) in graphene. The mobility of the
device can be readily measured by field effects (with two metal electrodes) or Hall
measurements (with Hall bar structure as Figure 3.1(a)).
Fig 3.1 Various device structures of graphene. (a) Back gated, (b) top gated, (c) self-
aligned top gate and (d) suspended device.

13. 3.2 Electronic Properties
 Semi-metal or zero-gap semiconductor [10]
 Linear dispersion relation Optoelectronics
 Massless Dirac fermions, v ~ c/300 Intrinsic carrier mobility (suspended graphene in
vacuum 2,00,000 cm2 V-1s-1
 Carrier mobility of graphene on SiO2 at room-temperature 10,000-20,000 cm2 V-1s-1
 Maximum current density J > 108 A/cm
 Velocity saturation Vsat = 5 x 107 cm/s (10 x Si, 2 x GaAs)
Fig 3.2 Dispersion relation of graphene in fist Brillouin zone

14. 3.3 Other Properties
Another of Graphene’s stand-out properties is its inherent strength. Due to the strength of its
0.142 Nm-long carbon bonds, Graphene is the strongest material ever discovered. What
makes this particularly special is that Graphene also contains elastic properties, being able to
retain its initial size after strain. Graphene’s ability to absorb a rather large 2.3% of white
light is also a unique and interesting property, especially considering that it is only 1 atom
thick. This is due to its aforementioned electronic properties; the electrons acting like
massless charge carriers with very high mobility.
Mechanical properties
• Young’s modulus: ~1.10 Tpa (Si ~ 130 Gpa)
• Elastically stretchable by 20%
• Strongest material known
• Flexible
Thermal conductivity
• ∼5.000 W/m•K at room temperature
Diamond: ∼2000 W/m•K, 10 x higher than Cu, Al
Transparent (only 1 atom thin)
Transparent flexible conductive electrodes
High surface to volume ratio
Most important advantage of Graphene technology is that it is compatible with
standard silicon technology

15. Chapter 4
4.0 Introduction to Graphene Nano-Ribbon (GNR)
Graphene nanoribbons [11] (GNRs, also called Nano-graphene ribbons or Nano-graphite
ribbons), are strips of graphene with ultra-thin width (<50 nm). Graphene ribbons were
introduced as a theoretical model by Mitsutaka Fujita and coauthors to examine the edge and
nanoscale size effect in graphene.
4.1 Electronic Properties
The electronic states of GNRs largely depend on the edge structures (armchair or zigzag). In
zigzag edges each successive edge segment is at the opposite angle to the previous [10, 12].
In armchair edges, each pair of segments is a 120/-120 degree rotation of the prior pair.
Zigzag edges provide the edge localized state with non-bonding molecular orbitals near the
Fermi energy. They are expected to have large changes in optical and electronic properties
from quantization.
Calculations based on tight binding theory predict that zigzag GNRs are always metallic while
armchairs can be either metallic or semiconducting, depending on their width. Zigzag
nanoribbons are semiconducting and present spin polarized edges. Their gap opens thanks to
an unusual antiferromagnetic coupling between the magnetic moments at opposite edge
carbon atoms. This gap size is inversely proportional to the ribbon width and its behaviour
can be traced back to the spatial distribution properties of edge-state wave functions, and the
mostly local character of the exchange interaction that originates the spin polarization.
Therefore, the quantum confinement, inter-edge super exchange, and intra-edge direct
exchange interactions in zigzag GNR are important for its magnetism and band gap. The edge
magnetic moment and band gap of zigzag GNR are reversely proportional to the electron/hole
concentration and they can be controlled by alkaline atoms.
Their 2D structure, high electrical and thermal conductivity and low noise also make GNRs a
possible alternative to copper for integrated circuit interconnects. Research is exploring the
creation of quantum dots by changing the width of GNRs at select points along the ribbon,
creating quantum confinement.
Graphene nanoribbons possess semi conductive properties and may be a technological
alternative to silicon semiconductors capable of sustaining microprocessor clock speeds in the
vicinity of 1 THz field-effect transistors less than 10 nm wide have been created with GNR –
"GNRFETs" – with an Ion/Ioff ratio >106 at room temperature.

16. Chapter 5
5.0 Simulation Side
• We have used Nano-TCAD ViDES as our simulation software.
• The current version of Nano-TCAD ViDES is a python module, which integrates the
C and FORTRAN subroutines already developed in the past version of the Nano-
TCAD ViDES simulator, which is able to simulate Nano scale devices, through the
self-consistent solution of the Poisson and the Schrodinger equations, by means of the
Non-Equilibrium Green’s Function (NEGF) formalism.
5.1 Needfor Device Simulation
They allow to:
• predict the device behaviour
• understand the physical mechanisms underlying the device operation
• test the impact of device design parameters on the device performance (device
optimization)
Fig 5.1 Structure of top gated graphene field-effect transistor is used in our
simulations

17. 5.2BasicsofNano-TCAD Vides
Fig 5.2.0 Device Modelling Tool
The module developed so far has a set of predefined functions, which allow to compute
transport in:-
• Two-dimensional materials (2D materials like MoS2, WSe2 and metal di-
chalcogenides in generals)
• Silicene
• Graphene Nanoribbons
• Carbon Nanotubes
• Two-dimensional graphene FET
• Two-dimensional bilayer graphene FET

18. The user can anyway define his own device and material through the exploitation of the
Hamiltonian command and through script written in python.
5.3.0 Hamiltonian operator
Synopsys: Hamiltonian (n,Nc)
A class, which allow the definition of a general Hamiltonian within the semi-empirical tight-
binding model.
n- Number of atoms in the slice
Nc- Number of slices (Nc >= 4)
Some of the attributes of Hamiltonian class are as follows:-
• Nc : (int) the number of slices
• n : (int) the number of atoms within each slice
• x: (numpy array of length n*Nc) x coordinates of the atoms
• y: (numpy array of length n*Nc) y coordinates of the atoms
• z: (numpy array of length n*Nc) z coordinates of the atoms
• Phi: (numpy array of length n*Nc) potential of the atoms
• Eupper : (double) the upper energy limit for which the NEGF is computed in the
nanoribbon
• Elower : (double) the lower energy limit for which the NEGF is computed in the
nanoribbon
• chargeT : (function) function which computes the free charge and the transmission
coefficient in the energy interval specified by Eupper and Elower with an energy step
equal to dE in correspondence of each C atoms of the nanoribbon
Fig 5.3.1 Hamiltonian operator in use

19. 5.3.1 Non Equilibrium Green’s Formalism (NEGF)
The non-equilibrium Green’s function (NEGF) formalism [13-15] provides a sound
conceptual basis for the development of atomic-level quantum mechanical simulators that will
be needed for Nano scale devices of the future. The non-equilibrium Greens function (NEGF)
formalism provides a powerful conceptual and computational framework for treating quantum
transport in Nano devices. It goes beyond the Landauer approach for ballistic, non-interacting
electronics to include inelastic scattering and strong correlation effects at an atomistic level.
Fig 5.3.2 Flow chart of software

20. 5.3.2 Mathematics Involved
 Newton Rap son Method of Iteration
Fig 5.3.3 Newton Raphson
The idea of the method is as follows: one starts with an initial guess which is reasonably close
to the true root, then the function is approximated by its tangent line (which can be computed
using the tools of calculus), and one computes the x-intercept of this tangent line (which is
easily done with elementary algebra). This x-intercept will typically be a better approximation
to the function's root than the original guess, and the method can be iterated.
Suppose ƒ: [a, b] → R is a differentiable function defined on the interval [a, b] with values in
the real numbers R. The formula for converging on the root can be easily derived. Suppose
we have some current approximation xn. Then we can derive the formula for a better
approximation, xn+1 by referring to the diagram on the right. The equation of the tangent
line to the curve y = ƒ(x) at the point x=xn is
Where ƒ' denotes the derivative of the function ƒ.
The x-intercept of this line (the value of x such that y=0) is then used as the next
approximation to the root, xn+1. In other words, setting y to zero and x to xn+1 gives
Solving for xn+1 gives
We start the process off with some arbitrary initial value x0. (The closer to the zero, the better.
But, in the absence of any intuition about where the zero might lie, a "guess and check"
method might narrow the possibilities to a reasonably small interval by appealing to
the intermediate value theorem.) The method will usually converge, provided this initial guess
is close enough to the unknown zero, and that ƒ'(x0) ≠ 0. Furthermore, for a zero

21. of multiplicity 1, the convergence is at least quadratic (see rate of convergence) in a
neighbourhood of the zero, which intuitively means that the number of correct digits roughly
at least doubles in every step.
 Jacobi Method
In numerical linear algebra, the Jacobi method (or Jacobi iterative method) is an
algorithm for determining the solutions of a diagonally dominant system of linear
equations. Each diagonal element is solved for, and an approximate value is plugged
in. The process is then iterated until it converges. This algorithm is a stripped-down
version of the Jacobi transformation method of matrix diagonalization.
Let
be a square system of n linear equations, where:
Then A can be decomposed into a diagonal component D, and the remainder R:
The solution is then obtained iteratively via
Where is the kth approximation or iteration of and is the next
or k + 1 iteration of . The element-based formula is thus:
The computation of xi
(k+1) requires each element in x(k) except itself. Unlike the Gauss–Seidel
method, we can't overwrite xi
(k) with xi
(k+1), as that value will be needed by the rest of the
computation. The minimum amount of storage is two vectors of size n.

22. 5.4 Device Template
Fig 5.4.0 Device Structre of GNR
Fig 5.4.1 Input Desk of NanoTcad Vides

23. 5.5 Python Module
Above simulations are performed on Linux 64 bit OS with python support. New parameters
can be found out by writing a new script for it.
Fig 5.5.0 Python script file

24. Project Roadmap

25. Conclusion
A model for the graphene FET using NEGF written in GUI Nano TCAD ViDES has been
reported. The top-gated graphene FET has been simulated.Typical simulations is then
successfully performed for various parameters of the grapheme FET. The modeling results
agree with the experimental data. The model is not only able to accurately describe ID-VG,
ID-VD characteristics of the graphene FET, but also affects of channel materials, gate
materials, size of graphene FET, Doping,Channel width ,Channel length and Dielectric
material on the characteristics.
POSITIVES:
 Graphene bilayerMOSFETshave beeninvestigatedexperimentallyandbydevice simulation.
Althoughthe on–off ratiosreportedsofar(100 at room temperature and2,000 at low
temperature) are toosmall forlogicapplications,theymarkasignificantimprovement(of
abouta factor of 10) overMOSFETs inwhichthe channel ismade of large-areagapless
graphene.
 According to scaling theory, as noted previously, athin channel regionallowsshort-
channel effectstobe suppressedandthusmakesitfeasible toscale MOSFETs to veryshort
gate lengths.
 The two- dimensional nature of graphenemeans itoffersusthe thinnestpossible channel,
so graphene MOSFETsshouldbe more scalable thantheircompetitors.
 Highvelocityisobservedincase of GNRFET ,whichresultsinfastswitchingof the device
and itgivesbetterperformance comparedtosiliconbasedorGaAsdevice.

26. LIMITATION:
 CMOS logicrequiresbothn-channel andp-channel FETswithwell-controlledthreshold
voltages, andgraphene FETs withall these propertieshave notyetbeenreported.
 These deviceshadrelativelythickback-gate oxides,sovoltage swingsof several voltswere
neededforswitching,whichissignificantlymore thanthe swingsof 1V and lessneededto
switchSi CMOS device
 Nanoribbon graphene, whichdoeshave abandgapand resultsintransistorsthatcan be
switchedoff, has serious fabrication issues because of the small widthsrequiredand
the presence of edge disorder
This discussion of the problems of graphene MOSFETs should not lead to the conclusion that
graphene is not a promising material for transistors. Rather, we have chosen a more critical
view to avoid a situation that has been seen in the past, in which a new device or material
concept has been prematurely declared capable of replacing the status quo.
Also, I agree with David Ferry, a veteran of semiconductor device research, when he says
that97 “many such saviours have come and gone, yet the reliable silicon CMOS continues to
be scaled and to reach even higher performance levels”.
However, the latest ITRS road- map strongly recommends intensified research into
graphene and even contains a research and development schedule for car- bon-based
nanoelectronics2. The race is still open and the pros- pects for graphene devices are at least
as promising as those for alternative concepts.

27. References:-
[1] A.C.Ferrari,F.Bonaccorso,V.Fal'ko,K.S.Novoselov,S.Roche,P.Boggild, S.Borini, F.H.L.
Koppens, V. Palermo, N. Pugno, J.A. Garrido, R. Sordan, A.Bianco, L.Ballerini, M.Prato, E.
Lidorikis, J. Kivioja, C. Marinelli, T. Ryhanen, A. Morpurgo, J.N. Coleman, V. Nicolosi, L.
Colombo, A. Fert,M. Garcia- Hernandez, A. Bachtold, G.F. Schneider, F.Guinea, C.Dekker,
M.Barbone, Z. Sun, C.Galiotis, A.N.Grigorenko, G.Konstantatos, A.Kis,M.Katsnelson, L.
Vandersypen, A.Loiseau, V.Morandi, D.Neumaier, E.Treossi, V.Pellegrini, M. Polini,
A.Tredicucci,G.M.Williams,B.HeeHong,J.-H.Ahn, J.MinKim, H. Zirath, B.J.vanWees,
H.vander Zant, L. Occhipinti, A. DiMatteo, I.
A.Kinloch,T.Seyller,E.Quesnel,X.Feng,K.Teo,N.Rupesinghe,P.Hakonen, S.R.T.Neil,
Q.Tannock, T.Lofwander, J.Kinaret, Science and technology roadmap for graphene, related
two-dimensional crystals, and hybrid systems, Nanoscale7(2015)4598–4810,
http://dx.doi.org/10.1039/ C4NR01600A.
[2] Peierls, R. 1935. Quelques properties typiques des corpes solides. Annales d’ Institut
Henri Poincare 5: 177.
[3] Landau, L. 1937. Zur Theorei der phasenumwandlugen II. Physikalische Zeitschrift
Sowjetunion 11: 26.
[4] Mermin, N. D. 1968. Crystalline order in two dimensions. Physical Review 176: 250.
[5] A.Geim, Graphene update, Bulletin of the American Physical Society 55(2). URL
〈http://meetings.aps.org/link/BAPS.2010.MAR.J21.4〉.
[6] M.C. Lemme, “Current Status of Graphene Transistors,” Solid State Phenomena, vol. 158,
2010, pp. 499-509
[7] A. Obraztsov, E. Obraztsova, A. Tyurnina, and A. Zolotukhin, “Chemical Vapor
Deposition of thin graphite films of nanometer thickness,” Carbon,vol. 45, Sep. 2007, pp.
2017-2021.
[8] A. Reina, X. Jia, J. Ho, D. Nezich, H. Son, V. Bulovic, M.S. Dresselhaus, and J. Kong,
“Large area, few-layer graphene films on arbitrary substrates by Chemical Vapor
Deposition.” Nano letters, vol. 9, Jan. 2009, pp. 30-5.
[9] J. Coraux, A.T. NıDiaye, C. Busse, and T. Michely, “Structural Coherency of Graphene
On Ir (111).,” Nano letters, vol. 8, Feb. 2008, pp. 565-70.
[10] Kan, E; Xiang, H.; Yang, J. & Hou, J. (2007a). Electronic structures of atomic Ti chains
on graphene Nano ribbons: A first-principles study. The Journal of Chemical Physics,
Vol.127, No. 16, 164706, ISSN: 0021-9606.
[11] K.S. Novoselov, a K. Geim, S.V. Morozov, D. Jiang, Y. Zhang, S.V. Dubonos, I.V.
Grigorieva, and a Firsov, “Electric field effect in atomically thin carbon films.” Science
(New York, N.Y.), vol. 306, Oct. 2004, pp. 666-9.
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metal under electric field ? Applied Physics Letters, Vol. 91, No. 24, 243116, ISSN: 0003-
6951

28. [13] G. H. Wannier, “The structure of electronic excitation levels in insulating crystals,”
Phys. Rev., vol. 52, pp. 191–197, Aug. 1937.
[14] W. Kohn, “Analytic properties of Bloch waves and Wannier functions,” Phys. Rev., vol.
115, pp. 809–821, Aug. 1959.
[15] J. D. Cloizeaux, “Orthogonal orbitals and generalized Wannier functions, “Phys. Rev.,
vol. 129, pp. 554–566, Jan. 1963.
[16] Youngki Yoon1,a
, Gianluca Fiori2,b
, Seokmin Hong1
, Giuseppe Iannaccone2
, and
Jing Guo “Performance comparision of Graphene Nanoribbon FETs with Schottky
contact and doped reservior”

29. Chapter 6
GNR FET Output Model:
Fig 6.1. showing the GUI (Graphical User Interface) of Nano TCAD ViDES
First of all we needed to insure that the results that we are getting from the
software is consistent or not. To check this we did the calibration with the help
of the data obtained from the software with the results that are already obtained
using sophisticated device and have been published. To obtain the results we
used Plot Digitizer for extracting data from the graphs of papers and then
compared it with the results that we found from Nano-TCAD ViDES.

30. Calibration Data :
Fig 6.2. Shows Output characteristics at Vgs= 0.6 v
Fig 6.3 .shows Turn-on characteristics at Vds=0.

31. Chapter 7
Study by Variation of Different Parameters:
1. InputCharacteristics.
Fig 7.1: Input Characteristics.
Parameters:-
W=1.5 nm , L=14nm and Both gate sweep.
Conclusion:-
As Vds is increased, current increases in the channel as it is directly proportional
to Vds, since now the drain voltage is more positive and electrons are attracted
towards it.

32. 2. Output Characteristics.
Fig 7.2: Output Characteristics.
Parameters:-
W=1.5 nm, L=14nm (Both gate sweep)
Conclusion:
At particular value of Vds as different Vgs are applied, current increases to a
large extent. When there is no gate voltage minimal current flows through the
channel, as the gate voltage is increased the amount of carriers in the channel
increases at the same value of Vds.

33. 3. Width Variation of the channel.
Fig 7.3: Width Variation of the channel.
Parameters:-
Vg1=1.0V=Vg2
L=14nm
Conclusion:-
• The width (W) of GNR is inversely proportional to its bandgap (eV).
• Therefore as W increases bandgap decreases and the device shows
metallic characteristics as the device enters into saturation at lower value
of Vds.

34. 4. Channel Length Variation
Fig 7.4 Channel Length Variation
Parameters:-
W=1.5nm
Vg1=Vg2=1.0V
Conclusion:-
• Length (L) is inversely proportional to the drain current(Ids).
• Therefore as the length is increased, the drain current starts to decrease.

35. 5. Variation of thickness of oxide layer on the gate.
Fig 7.5 Variation of thickness of oxide layer on the gate.
Parameters:-
W=1.5nm
Vg1=Vg2=1.0
Both gate sweep
Conclusion:-
• Capacitance is inversely prop. to oxide thickness.
• Ids is directly prop. to the capacitance.
• Therefore as the oxide thickness is increased, the capacitance decreases
and the over-all current decreases.

36. 6. Variation in the doping concentration
Fig 7.6 Variation in the doping concentration
Parameters:-
W=1.5nm
Vg1=1.0=Vg2 (both gate sweep)
L=14nm
Conclusion:-
As the doping increases while keeping the channel length same, the increased
no. of carriers result in the increase of particle-to-particle collision and hence the
mobility decreases and the resultant value of current is less.

37. 7. Using Different Dielectrics.
Fig 7.7 Using Different Dielectrics.
Parameters:-
W=1.5nm
L=14nm
Vg1=Vg2=1.0 (both gates sweep)
Conclusion:-
• Capacitance of the device is directly proportional to the relative di-electric
constant.
• As the di-electric constant increases, capacitance increases and hence the
Ids value increases.

38. Chapter 8
Analog & Digital Parameters Calculation for GNRFETs
In this segment we calculated some analog and digital parameters from the
curves obtained after simulating GNRFET using Nano-TCAD Vides. We have
considered four kinds of graphs:
(1) Id vs Vgs for differentVds
(2) Id vs Vgs for differentGNRwidth
(3) Id vs Vds for different Vgs
(4) Id vs Vds for different GNR width.
Digital Parameters:
 ION/IOFF ratio
 Subthreshold Swing (SS)
 DIBL (mV/V)
Analog Parameters:
 Trans-conductance(gm)
 Drain Resistance (rd)
 Amplification factor (µ)

39. Digital Parameters
 ION/IOFF ratio: - It is the figure of merit for having high performance (more ION) and
low leakage power (less IOFF) for the CMOS transistors. Typically more gate control
leads to more ION/IOFF ratio.
 Subthreshold Swing (SS): - The subthreshold swing is defined as the gate voltage
required to change the drain current by one order of magnitude, 1 decade. In the
MOSFET, the subthreshold swing is limited to (kT/q) ln10 or 60 mV/dec at room
temperature.
SS= ∆Vgs / ∆ (log10 Id)
 DIBL (mV/V): - Drain-induced barrier lowering or DIBL is a Shrt channel effect
in MOSFETs referring originally to a reduction of threshold voltage of the transistor at
higher drain voltages.
where,
is the threshold voltage measured at a supply voltage (the high drain voltage),
is the threshold voltage measured at a very low drain voltage, typically 0.05 V or 0.1v
is the supply voltage (the high drain voltage)
is the low drain voltage (for a linear part of device I-V characteristics).
Note:
The minus in the front of the formula ensures a positive DIBL value. This is because the high
drain threshold voltage, , is always smaller than the low drain threshold voltage, .
Typical units of DIBL are mV/V.

40. Analog Parameters
 Trans-conductance (gm): - It is very often denoted as a conductance, gm, with a
subscript, m, for mutual. Trans-conductance is defined as follows:
 Drain Resistance (rd): - It is given by rd = ∆ Vds / ∆ Id Ω
 Amplification factor (µ): - It is given by gm * rd
Fig 8.1 Different regions in Id vs Vgs

41. Digital Parameters Calculation
(1)For different values of Vds
Fig 8.2 Id vs Vgs at Vds=0.05V
ION/IOFF ratio= (1*10^-6) / (1*10^-10) =1*10^4
SS= ∆Vgs / ∆ (log10 Id) =60 mV/dec
Fig 8.3 Id vs Vgs at Vds=0.6V
ION/IOFF ratio= (6.5*10^-6) / (2*10^-8) =325

42. SS= ∆Vgs / ∆ (log10 Id) = 210 mV/dec
Fig 8.4 Id vs Vgs curve at Vds=0.8V
ION/IOFF ratio= (6.5*10^-6) / (2.8*10^-8) =232
SS= ∆Vgs / ∆ (log10 Id) = 190 mV/dec
(2)For different GNR width
Fig 8.5 Id vs Vgs curve for W=1.5nm
ION/IOFF ratio= (9*10^-6) / (7*10^-7) =13
SS= ∆Vgs / ∆ (log10 Id) =175 mV/dec

43. Fig 8.6 Id vs Vgs curve for W=2nm
ION/IOFF ratio= (6.5*10^-6) / (3.8*10^-7) =17
SS= ∆Vgs / ∆ (log10 Id) = (0.4-0.3) / (3*10^-6-8*10^-7) = 450
Fig 8.7 Id vs Vgs curve for DIBL calculation
Vth
DD (by red curve) = 0.18V
Vth
LOW (by black curve) = 0.3V
VDD = 1V
VD
Low = 0.05V
DIBL= - (0.18- 0.3) / (1-0.05) = 126 mV/V

44. Analog Parameters:
Obtained by changing GNR width
Fig 8.8 Id vs Vds for W=1.5nm
gm = ∆ Id / ∆ Vgs = (4*10^-6 – 2.2*10^-6)/(0.4-0.3) = 18 * 10^-6 Ω-1
rd = ∆ Vds / ∆ Id = (0.7-0.5) / (4.8*10^-6 – 3.8*10^-6) = 200 *10^3 Ω
µ = gm * rd = (18 * 10^-6 ) * (200 *10^3) = 3.6
Fig 8.9 Id vs Vds for W=2nm
gm = ∆ Id / ∆ Vgs = (3*10^-6 – 0.8*10^-6)/(0.4-0.3) = 22 * 10^-6 Ω-1
rd = ∆ Vds / ∆ Id = (0.3-0.1) / (2.5*10^-6 – 1.55*10^-6) = 210 *10^3 Ω
µ = gm * rd = (22 * 10^-6 ) * (210 *10^3) = 4.62

45. DIGITAL PARAMETERS
(1) For different Vds
Table 8.1
Vds (volts) Ion/Ioff ratio SS(mV/dec)
0.05 10000 60
0.6 325 210
0.8 232 190
(2) For different GNR width
Table 8.2
GNR Width(nm) Ion/Ioff ratio SS(mV/dec)
1.5 13 175
2.0 17 450
ANALOG PARAMETERS
For different GNR width
Table 8.3
GNR Width(nm) gm (Ω-1
) (*10-6
) rd (Ω) (*103
) µ
1.5 18 200 3.6
2.0 22 210 4.62

46. LIST OF FIGURES
Figure Number Page Number
1.1 Graph Representing Moore’s Law 04
1.2 Limitations of Moore’s Law 05
2.0 Flow chart of process flow 06
2.0.1 FinFET Device structure 07
2.0.2 Graphene layer 07
3.0.1 Hybridisation Of carbonin Graphene 08
3.0.2 Graphene Sheet 09
3.1 Various device structure of graphene 09
3.2 Dispersion relation of Graphene 10
5.1 Structure of top gated GFET 13
5.2.0 Device Modelling Tool 14
5.3.1 Hamiltonian Operator 15
5.3.2 Flow chart of software 16
5.3.3 Newton Raphson 17
5.4.0 Device structure of GNR FET 19
5.4.1 Input desk of Nano TCAD ViDES 19
5.5.0 Python Script File 20
6.1 GUI Of Nano TCAD ViDES 21
6.2 Output Characteristics 22
6.3 Turn On Characteristics 22
7.1 Input Characteristics (Different Vds) 23
7.2 Id vs Vds For different Vgs 24
7.3 Id vs Vds For different GNR Width 25
7.4 Id vs Vds For different GNR Length 26
7.5 Id vs Vds For diff. oxide thickness 27
7.6 Id vs Vds For diff. Doping 28
7.7 Id vs Vds For diff Dielectrics 29

47. 8.1 Different regions in Id vs Vgs 32
8.2 Id vs Vgs at Vds 0.05 V 33
8.3 Id vs Vgs at Vds 0.6 V 33
8.4 Id vs Vgs at Vds 0.8 V 34
8.5 Id vs Vgs For w=1.5nm 34
8.6 Id vs Vgs For w=2 nm 35
8.7 DIBL calculation 35
8.8 Id vs Vds for w=1.5 nm 36
8.9 Id vs Vds For w=2 nm 36

48. CONTENT
Chapter Number Page Number
Acknowledgement 01
1. Motivation 04
2. Introduction 06
3. Introduction to Graphene 08
4. Introduction to GNR 12
5. Simulation Side 13
6. GNR FET GUI In Nano TCAD 21
7. Variation Of Parameters 23
8. Analog and Digital Parameter calculation 30