1. Bhavana B M 1
BHAVANA B M
Address: #461/1, 8th
B Main, Jayanagar 4th
Block, Bengaluru 560011
Email: bhavana.bm14@gmail.com
Mobile Number: 8904480825
PROFILE:
I am a responsible and hard-working individual motivated to achieve my best. I have other qualities
to bring up the work place such as good team work, organisational skills, efficiency and I am very
meticulous, I take pride in all the work I do. The feat of engineering in today’s world inspires me to
also make such valuable contributions.
KEY ACHIVEMENTS:
 Currently pursuing internship at Graphene Semiconductors.
 Published a paper entitled ‘Design of SPI flash controller for Spartan6 FPGA’ in International
Journal of Innovations in Engineering and Technology (IJIET), volume 5 issue 1- February
2015.
 Selected for a highly competitive Higher Education Program (HEP) SystemVerilog Training
conducted by Mentor Graphics. (3% acceptance rate).
 Secured 865th
rank in the Common Entrance Test (CET).
 Volunteered International Conference on Transformations in Engineering Education (ICTIEE)
held in BMS College of engineering, January 2015.
EDUCATION:
Education : Bachelor of Engineering in Electronic and Communication
College : BMS COLLEGE OF ENGINEERING, Bengaluru.
Completion date : 2016
CGPA (7th
semester) : 9.6
Education : PUC
College : RV PU College, Bengaluru.
Completed : 2012
Percentage : 94.33%
Education : SSLC
College : Carmel Convent School, Bengaluru.
Completed : 2010
Percentage : 96.16%
CORE SKILLS:
 Programming Language/ : C, C++, Linux, MS Windows
Operating Systems
 Hardware Description Languages : UVM, SystemVerilog, Verilog, VHDL
 EDA tools : Mentor Questasim, Cadence NCsim & Incisive, Xilinx ISE.
 Others Tools : Keil IDE, MBED compiler, vi editor, Makefiles
 Well-developed Presentation, analytical and numerical ability.

2. Bhavana B M 2
ACADEMIC EXPERIENCE:
Project : Implementation of Low power interface for a Verification Intellectual
Property of AXI4 protocol
Tool Used : Cadence Incisive
Language Used : UVM
Date : January –May 2016
Synopsis:
The AXI master VIP including the sequence_item, sequences, sequencer and driver was designed
using UVM. AXI slave was designed in Verilog and five channels of the AXI protocol for basic read and
write transactions were implemented. The power controller consisting of APB master and slave was
designed. By using the concept of RAL model and writing into a register of APB slave, the entry and
exit of the AXI slave into the low power mode was controlled. Simulation was performed using
Cadence Incisive.
Role & Responsibilities:
 Analyzed the specification of AMBA AXI and APB protocols
 Designed AXI master VIP, AXI slave and power controller
 Simulated using Cadence Incisive.
 Prepared the project report and made a presentation of the same.
Project : Design of DLX processor
Tool Used : EDA playground, Xilinx ISE, Cadence RTL compiler
Language Used : Verilog
Date : August –December 2015
Synopsis:
DLX processor with five-stage-pipeline containing six modules was designed. Each module was tested
for it’s functionality and all the modules were integrated into a top module. Simulation was
performed using EDAplayground tool. Synthesis was done using Xilinx and Cadence RTL Compiler. It
was found that the power consumed by the FPGA optimised design is 29 mW whereas the power
consumed by the ASIC optimised design is 10 mW. The operating frequency of the processor is
666.66 MHz.
Role & Responsibilities:
 Analyzed the specification of DLX processor
 Designed the modules using Verilog and verified for its functionality.
 Synthesized using Cadence RTL compiler
 Prepared the project report and made a presentation of the same.
Project : Verification of LC3 microcontroller
Tool Used : Mentor Graphics QuestSim for functional coverage.
Language Used : SystemVerilog
Company : Mentor Graphics.
Date : June – July 2015
Synopsis:
Included verification of the LC3 microcontroller modules - Fetch, Decode, Execute, Writeback,
controller and top module. The testbench components included generator, driver, receiver, monitor

3. Bhavana B M 3
and scoreboard. The concepts used in testbenches were Object oriented classes; constrained
randomization techniques; inter-process synchronization mechanisms like assertions and mailboxes.
20 functional bugs were reported for this design. Then 100% functional coverage was achieved for
the same design using the Questa functional coverage tool.
Role & Responsibilities:
 Analyzed the specification of LC3 microcontroller
 Analyzed and formulated a detailed verification plan.
 Developed a testbench and test cases using Hardware Verification Language (HVL)
SystemVerilog.
 Prepared the project report that documented the bugs found and made a presentation of
the same.
Project : Bluetooth Controlled Motor
Tool Used : MBED Compiler
Microprocessor : Cortex M0
Date : January – May 2015
Synopsis:
In this project, motor of a projector screen was controlled by sending the commands through
Bluetooth. An application called Bluetooth terminal was used to send signals through Bluetooth of
the phone which were received by HC-05 module. The response from HC-05 was used by the
microprocessor to control the rotation upwards or downwards.
Role & Responsibilities:
 Analyzed the architecture of cortex M0 microprocessor and HC-05 Bluetooth module
 Developed a circuit to meet the requirements.
 Developed a C program using the MBED compiler to control the microprocessor
 Prepared the project report that documented the results.
Project : Implementation of Serial Peripheral Interface (SPI) protocol.
Tool Used : Xilinx
Language Used : VHDL (VHSIC Hardware Description Language)
Date : August – December 2014
Synopsis:
In this project, basic commands for a SPI flash controller with single master and single slave
configuration operating in full duplex mode was designed. SPI protocol was demonstrated by using
SPI flash memory present on Spartan6 board. SPI flash controller program was written in VHDL and
was used to write into or read from the flash memory. The contents of the flash were then displayed
using LEDs.
Role & Responsibilities:
 Studied the basic functionality of SPI protocol.
 Developed the code using VHDL.
 Prepared the project report that documented the results seen on the Spartan 6 board and
made a presentation of the same.

4. Bhavana B M 4
Project : Propeller display
Tool Used : KEIL Professional Developer’s Kit
Microcontroller : 8051
Date : January – may 2014
Synopsis:
The text message BMSCE was displayed on a cost effective, area effective, circular LED display using
the principle of persistence of vision and space multiplexing. It was done by pre programming the
8051 microcontroller.
Role & Responsibilities:
 Analyzed the architecture of 8051 microcontroller.
 Developed a circuit diagram and the hardware assembly.
 Developed low level design (coding) using ‘C’ language.
 Prepared the project report that documented the results and made a presentation for the
same.
HOBBIES
 Drawing and painting.
 Calligraphy
 Music
REFERENCES: Upon request.