This document discusses hardware simulation of a QPSK modulator. It begins by introducing QPSK modulation and its applications in wireless communication systems due to its bandwidth efficiency and noise immunity. It then discusses a proposed hardware simulation of a QPSK modulator using Altera Quartus II software to reduce power consumption by eliminating unnecessary blocks. The proposed design stores phase-shifted carrier signals in a ROM rather than generating them, requiring fewer blocks. It is summarized that the proposed design aims to improve speed, area and power over conventional designs.