Dsp U Lec02 Data Converters

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Data Converters

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Dsp U Lec02 Data Converters

  1. 1. EC533: Digital Signal Processing Lecture 2 : Data Converters
  2. 2. 2.1 – Sample & Hold (S&H) Circuit
  3. 3. 2.1 – Sample & Hold (S&H) Circuit - continued Control Signal Rate of change of the output voltage when the control signal is in  the hold state ‐ due to leakage current.
  4. 4. 2.1 – Sample & Hold (S&H) Circuit - continued Ideally =0 & it should be too small. needed for the capacitance to achieve 0.993 Vi ≈ 0.7 % error.
  5. 5. 2.2 – Analogue-to-Digital (ADC) DC level n bits O/P I/P Quantizer Encoder Full Scale ADC After Sampling; the amplitude of the analogue samples is quantized & encoded using either uniform or non-uniform quantization & encoding depending on the application
  6. 6. 2.3 – Quantization • The quantizing operation approximates each sample value to the nearest level in a finite set of discrete levels/values, known as quantization levels. • This approximation introduces quantization error. Therefore, once quantized, the instantaneous values of the signals are lost, and can never be reconstructed exactly. Continuous signal values Discrete signal values at discrete times at discrete times Quantizer
  7. 7. 2.3 – Quantization (cont.) • Quantization principle is based on that any human sense (ear & eye) can only detect finite intensity differences. as an ultimate receiver There are 2 types of quantization: 1. Uniform quantization: biomedicine, audio systems. 2. Non­uniform quantization: communication systems for the need to compress signals.
  8. 8. 2.3.1 – Uniform Quantization & Encoding • The full scale range of the I/P signal is divided into 2n values; (n is the number of ADC bits). • Each analogue sample is assigned to one of the 2n values by truncation. • The difference between two adjacent values is called ‘Quantum’ or step size (a) Vmax 111 3.5 a 110 e 2.5 a n = 8 levels Signal level 1.5 a 0.5 a 0 -0.5 a 010 -1.5 a VFSR 001 a -2.5 a 000 -3.5 a -Vmax Unipolar (+Vm or ‐ Vm) polar (±Vm) FSR: Vmax - Vmin (swing). Mid‐tread Quantizer. L: number of quantization levels L= 2n – 1 L= 2n Mid‐rise Quantizer. n increases for audio applications as the ear is more sensitive than the eye.
  9. 9. 2.3.1 – Uniform Quantization & Encoding - Continued Quantization Transfer Characteristics Mid‐ tread a=Q Truncation leads to quantization noise • Quantization noise is random & follows a zero- mean uniform distribution (pdf). a/2 0 - a/2 Quantization Noise
  10. 10. 2.3.1 – Uniform Quantization & Encoding - Continued
  11. 11. 2.3.1 – Uniform Quantization & Encoding - Continued rms Not detected by ADC
  12. 12. 2.4 – Digital-to-Analogue Converter (DAC) • What is a digital to analog converter (DAC)? – Converts digital input signal to an analog output  signal Bn-1 B0 1 0 0 0 1 1 1 Va 0 1 0 1 0 0 0 0 0 1 1 0 1 1 DAC 1 1 1 1 1 0 1 Circuit Symbol B0 LSB B1 B2 n: word‐length MSB
  13. 13. 2.4 – Digital-to-Analogue Converter (DAC)…Cont. • D/A conversion can be achieved using a number of different methods such as: – The Weighted-Resistor DAC – The Ladder Network (The R-2R Ladder DAC) – The Switched Current-Source DAC – The Switched-Capacitor DACs
  14. 14. 2.4.1 – Weighted Resistor DAC Rf = R ∑I i R 2R 4R 8R Vo Most  • summing amplifier Significant  Bit Least  Significant Bit VREF Large n  very large R
  15. 15. 2.4.1 – Weighted Resistor DAC - continued
  16. 16. 2.4.1 – Weighted Resistor DAC - continued Advantage – Easy principle (low bit DACs) Disadvantages – Requirement of several  different precise input  resistor values: one unique  value per binary input bit.  (High bit DACs) – Larger resistors ~ more error. – Precise large resistors – expensive. VREF
  17. 17. 2.4.2 – R-2R Ladder Type DAC R-2R Ladder Network
  18. 18. 2.4.2 – R-2R Ladder Type DAC (Cont.) D 0 × 2 0 + D1 × 21 + D 2 × 2 2 + D 3 × 2 3 Vo = 4 Vref 2 Example: Circuit with 0110 input
  19. 19. 2.4.2 – R-2R Ladder Type DAC - continued VREF MSB LSB
  20. 20. 2.4.2 – R-2R Ladder Type DAC - continued • The less significant the bit, the more resistors the signal must pass through before reaching the op‐amp • The current is divided by a factor of 2 at each node LSB MSB
  21. 21. 2.4.2 – R-2R Ladder Type DAC - continued Rf ⎛ B2 B1 B0 ⎞ VOUT = VREF⎜ + + ⎟ R ⎝2 4 8⎠ Rf
  22. 22. 2.4.2 – R-2R Ladder Type DAC - continued • Question:   – Input = (101)2 – VREF = 10 V – R = 2 kΩ – Rf = 2R R R R 2R R 2R 2R 2R I0 I0 Op-Amp input VREF VREF “Ground” B0 B2
  23. 23. 2.4.2 – R-2R Ladder Type DAC - continued • Only two resistor values‐ R and 2R • Does not need the kind of precision as Binary  weighted DACs • Easy to manufacture • More popular • Less errors
  24. 24. 2.5– DAC Resolution • Resolution: is the amount of variance in  output voltage for every change of the LSB in  the digital input. • How closely can we approximate the desired  output signal(Higher Res. = finer detail=smaller  Voltage divisions) • A common DAC has a 8 ‐ 12 bit Resolution VRef Resolution = VLSB = 2n
  25. 25. 2.5– DAC Resolution (Cont.) • Voltage  Vref resolution:  2n Voltage step example : for 10 bit resolution. So n=10 if Vref = 10V voltage step : 10V/1024 = 10mV
  26. 26. 2.5– DAC Resolution (Cont.) Poor Resolution(1 bit) Better Resolution(3 bit) Vout Vout Desired Analog Desired Analog signal signal 111 110 110 2 Volt. Levels 1 8 Volt. Levels 101 101 100 100 011 011 010 010 001 001 0 0 000 000 Digital Input Approximate Digital Input Approximate output output

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