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1. Top School in Noida
By:
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2. Analogue to Digital Conversion
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3. Digital Signal Processing
 A digital signal is an approximation of an analog
one
 Levels of signal are sampled and converted to a
discrete bit pattern.
 Resistor networks can be used to convert digital
signals into analogue voltages
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4. Step (discrete) approximation
more samples give greater accuracy
time
level
sample
“stair-step”
approximation of
original signal
hold time for sample
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5. This Lecture
 Methods of analogue to digital conversion
 flash
 counter ramp
 successive approximation
 Sample interval and aliasing problems
 Sample and hold circuits
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6. The Comparator
 Most A-D converters use a comparator as part of the
conversion process
 A comparator compares 2 signals A and B
 if A > B the comparator output is in one logic state (0, say)
 if B > A then it is in the opposite state (1, say)
 A comparator can be built using an op amp with no
feedback
+ analogue
-
input
reference
voltage
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7. Flash Converter
 Uses a reference and a comparator for each of
the discrete levels represented in the digital
output
 Number of comparators = number of
quantisation levels
 Not practical for more than 10 bit converters
 generally fast but expensive
+ G
+ F
+ E
+ D
+ C
-
3V
-
4V
-
5V
-
6V
-
7V
+ B
+ A
-
1V
-
2V
encoder
input signal
digital
output
Converter
input
Comparator Outputs Encoder Output
range (V) A B C D E F G
< 1 0 0 0 0 0 0 0 000
>1-2 1 0 0 0 0 0 0 001
>2-3 1 1 0 0 0 0 0 010
>3-4 1 1 1 0 0 0 0 011
>4-5 1 1 1 1 0 0 0 100
>5-6 1 1 1 1 1 0 0 101
>6-7 1 1 1 1 1 1 0 110
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>7 1 1 1 1 1 1 1 111

8. Counter-ramp Converter
 Comprises a D-A converter, a single comparator, a counter, a clock
and control logic
 When a conversion is required
 A signal (conversion request) is sent to the converter and the counter is
reset to zero
 a clock signal increments the counter until the reference voltage
generated by the D-A converter is greater than
the analogue input
 At this point in time the output of
the comparator goes to a
logic 1, which notifies the
control logic the
conversion has finished
 The value of the counter
is output as the digital
value
-
+
D-A
Converter
comparitor
Counter clock and
control logic
analogue input
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9. Counter-ramp Converter
 The time between the start and
end of the conversion is known
as the conversion time
 A drawback of the counter-ramp
converter is the length of time
required to convert large
voltages
 We must assume the worst case
when calculating conversion
times
0 1 2 3 4 5 6 6 6 6 6 6
conversion
request
comparitor
output
d.c input voltage
D-A converter
output
counter output
clock
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10. Successive Approximation Converter
 Counter replaced by a register
 Contents of register decided by clock and control logic
 When a conversion is required:
 contents of register cleared
 Vd = 0
 MSB set to a 1
 if Vc = 0 then Vd < Vin
=> leave MSB set
 if Vc =1 then Vd > Vin
=> clear MSB
 Repeat previous step for other bits
in MSB to LSB order
+
-
D-A
Converter
comparitor
clock and
control logic
analogue input
4-bit reg
b3 b2 b1 b0
Vin
Vd
Vc
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11. The successive approximation A-D
converter
 Example:
 A 4-bit successive approximation A-D converter has a
full-scale input of +15V. Show how the A-D converter
would convert the analogue voltages 10.9V and 3.1V
into their digital equivalents
 Total conversion time = n+1 cycles where n = the
number of bits in the code word
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12. ADC Conversion Error
 Assume D-A converter output
has stepped up to V1.
 Because Vi > V1, the output
has stayed at a logic 0.
 On the next clock pulse the D-A
output rises to V2.
 V2 > Vi, comparator output
becomes logic 1 and
conversion is completed.
 Maximum possible error = q.
V2
V1
VI

13. Quantisation
 Output from an A-D converter can
only be one of a limited number of
possible codes
 Hence quantisation errors will arise.
 Possible to reduce this error to half by
adding q/2 to the output of the D-A
converter
 Equivalent of “rounding” decimal
numbers.
111
110
101
100
011
010
001
000
7V
6V
5V
4V
3V
2V
1V
0V
111
110
101
100
011
010
001
000
7V
6V
5V
4V
3V
2V
1V
0V

14. Quantisation
 Quantisation errors can be reduced by increasing
the number of bits
 Common for A-D converters to have 16 bit or
better resolution
 However the accuracy of the reference voltage
must be of the same precision
 Example:
 Consider a A-D converter where Vref is only accurate to
within 1%

15. Summary

Device Comment Conversion time
Best Average Worst
Flash fast and expensive 1 1 1
Counter ramp simple but slow 1 2n/2 2n
Sucessive approx widely used n+1 n+1 n+1
 One way to reduce quantisation errors is to use a larger number
of bits in the codeword
 absolute accuracy of conversion may not be as good as the
resolution if the error tolerance for reference voltages gets too
large
 A multiplexer enables one A-D converter to be switched between
several signal inputs

16. Multiplexers
 The A-D converters described above have all been single-input
devices
 It is often necessary to convert several analogue signals to binary
code words
 Integrated circuit multiplexers are available which can select one of
its analogue inputs at a time and present it to a single A-D
converter
switch decoding
logic
1
2
3
4
Analogue
inputs
digital
control
lines
Selected
analogue
output

17. Conversion of a.c. signals
 The A-D converters that we have looked at present no special
problems with d.c.
 What about a.c. signals?
 Example consider reading room temperature and plotting
against time
 Not possible to sample at every instant in time
 rate at which we take samples is known as the sampling rate
 sampling too fast can be
inefficient
A3
A2
A1
temp
time

18. Conversion of a.c. signals
 Sampling too slowly can cause information to be lost
t1 t2
A2
A1
temp
time

19. Sample Time vs Frequency
 Consider what happens when the signal
frequency is higher than the sampling
frequency.
time
voltage
sample frequency is number of samples / second

20. Conversion of a.c. signals
 Effects of under-sampling
 possible to interpolate high
frequency components as
low frequency ones
 these errors are said to be
caused by aliasing
 important to preceed A-D
converter with a low pass
filter to remove high
frequencies
 known as an anti-aliasing
filter
time
voltage
Sample frequency must be at least twice
the highest signal frequency (2f is also
called the Nyquist Frequency).

21. Example
What is the maximum frequency of input signal
that can be converted by an A-D convertor with a
conversion time of 0.25 mS?
samples per second = 1000 / 0.25 = 40,000
Maximum frequency in input signal has to be
half this or 20kHz.

22. Sample-and-hold devices
 Sampling rule tells us at what rate to make conversions, but there
is still another problem associated with changing signals
time
voltage
t1 t2

23. Sample-and-hold devices

time
voltage
t1 t2
To remove the problem a sample and hold device which
samples the input and holds this value until the end of the
conversion is often used
switch
storage
capacitor

24. Sample-and-hold devices
A number of problems exist with the previous sample
and hold circuit
 load placed on the input of the circuit by charging the
capacitor during the sample phase
 current flowing from the capacitor used in the conversion will
reduce the voltage stored on the capacitor
-
+
-
+
sample/hold
control line
C

25. What you should be able to do
 Explain the operation of binary weighted resistor and R-
2R ladder networks. Recall their general layout.
 Calculate the output voltage given an input 4-bit value.
 Explain quantisation with reference to D-A conversion.
 Explain the operation of flash, counter ramp and
successive approximation A-D convertors. Recall their
general layout.
 Recall their conversion time relative to number of bits
required.
 Explain quantization with reference to A-D conversion.
 Explain the aliasing problem and the relationship
between sample rate and input signal frequency.