1. FPGA High Speed IO Trends and
Signal Integrity Challenges
John Wei
Member of Technical Staff
High Speed Technology Specialist
© 2010 Altera Corporation—Public

2. Agenda
 High Speed IO Trends
 Signal Integrity Terms
 Signal Integrity Challenge
 Minimize Jitter Generation
 Improve Jitter Tolerance
 Transceiver Equalization
q
 On-Die Instrument
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3. High Speed IO Trends
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4. HSIO Link Architecture Advancement Path
1 Gbps
Asynchronized
A h i d
Tx Rx
Coded data
te
Data rat
~0.8 Gbps Gigabit Ethernet
source synchronized CEI/OIF
~0.1 Gbps
global clock Strobe PCI Express
Tx Rx 40G/100G Ethernet
Tx Rx Data
Data
Clock
Time
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5. Traditional Parallel Bus
 PCI, PCI-X, Telecombus, SPI-3, XGMII…
 Single-ended bus
Single ended
 Low speed, usually less than 150Mbps/pin
 High pin count
 Short distance
 Simultaneous Switching Noise (SSN)
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6. High-Speed Source-Synchronous
 SFI-4, SPI-4, RapidIO (Parallel)…
 Parallel LVDS bus
 Data rate up to 1.6Gbps
 Source-Synchronous clock required to sample data
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7. High-Speed Source-Synchronous
 Skew is an issue
 Bit Period Is Short, 0.6 ns at 1.6 Gbps
 Sk
Skew I Large Percentage of the Period
Is L P t f th P i d
 Skew Makes It Difficult to Sample in Middle of Bit Period
 Sources of Skew
 Trace Length Variations
 Capacitive & Inductive Loading
 Transmitter Channel-to-Channel Skew
Clk’
D0
D0’
D1’
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8. High-Speed SSIO Consideration
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9. Serialization
 Transceiver introduced
 S i li
Serializer
 Clock and Data Recovery
 Deserializer
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10. Transceiver Functionality
High-Speed Data High-Speed Data SERDES Slower-Speed Data
b2
b3
CDR
High-Speed
b0
Clock
b1
Slower-Speed Clock
/
Receiver
Transmitter
T itt SERDES Slower-Speed Data
b0
High-Speed Data
b1
b2
b3
PLL
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11. Serialization
 Serialization solves most of parallel bus
problems
 CDR based
 Skew is not a problem any more
 Faster data rate, shorter bit rate
 Simple Timing Calculation Not Sufficient to Determine System
Reliability
R li bilit
 Must Examine Uncertainty in Digital Data Communications
 Signal Integrity is the key
g g y y
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12. Signal Integrity Terms
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13. Key Measurement Components for Serial I/O
Signal Integrity
 Bit error rate performance (
p (BER)
)
 Measures number of errors over the total number of bits transferred from
transmitter (Tx) to receiver (Rx)
 Eye diagram
 Shows the data valid window with timing and voltage margins
 Jitter
 Reduces data valid window
 Increases with more transceiver, FPGA core and regular I/O switching
Good Signal Integrity is the Key to Reliable
High-Speed Solutions
High Speed Sol tions
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14. What’s an Eye Diagram
Waveform Represents a Logical ‘1’
Waveform Represents a Logical ‘0’
0
Ideal Eye Diagram with No Noise
Eye Diagram with Voltage Noise
Eye Diagram with Timing Noise
Eye Diagram with Voltage & Timing Noise
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15. Definitions of Jitter
 Time Difference Between
 When a Pre Defined Event Should Occur &
Pre-Defined
 When It Actually Occurs
 Event Could Be:
 Clock Rising & Falling Edges
 O ti
Optimum Sampling I t t of Signal
S li Instant f Si l
 Differential Zero Crossing of Electrical Signal
 Threshold Power Crossing of Optical Receiver
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16. Jitter Pictorial Representation
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17. Jitter Generation
 Used to define a transmitter
 The amount of period variation (jitter)
(j )
due to the driver
 Total jitter (TJ) consists of a bounded
portion (DJ) and an unbounded
portion (RJ)
 TJ = DJ + RJ
  is a function of bit error
rate (BER)
 BER defined by spec
 i.e. BER of 1E-12 = 1E12 bits without an
error
  = +/-7 = 14
+/- 3 = 99% error-free = 1E-2 BER
 TJ = DJ + 14*RJ
14 RJ
+/- 7 = 1e-12 BER
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18. Jitter Tolerance
 Used to define a CDR
 Definition: Amount of jitter the receiver can handle without
registering a bit error
 Specification defines the frequency range of jitter
Altera Stratix® II GX
j
jitter tolerance over
PVT @ 6.25 Gbps
Jitter Tolerance
Mask
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19. S-Parameters
 Used to define a channel S22
S12
S21
S11
 Single ended
 Energy in vs. energy out Port 1 Port 2
 S11, S21, S12, S22
 Differential
 4 parameters for each conversion
Port 1 Port 4
 Differential  differential (SDD)
 Differential  common mode (SDC) Port 3 Port 2
 Common mode  differential (SCD)
 Common mode  common mode (SCC) Diff Port 1
Co o ode co o ode Diff Port 2
 SDD21 = Differential insertion
loss
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20. S-Parameters
 As Data Rate (Frequency) Increase, we see
higher insertion loss (attenuation )
SDD21 Curve for XAUI
Backplane vs. Frequency
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21. Signal Integrity Challenge
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22. Serial Protocols Get Faster
FC16
OC192 10GE CEI-10G
10
FC8 PCIe 3.0
Interlaken 6G
Data rat (Gbps) in log scale
CEI-6G
XAUI FC4 PCIe 2.0
SRIO 3.125 SATA 2.0
PCIe 1.0 3.072G
SRIO 2.5
25
OC48 2.4576G 3G SDI
FC2 1.536G GPON
GigE 1.2288G
1 FC1 SATA 1.0
SRIO 1.25
In 2002, serial protocols entered
te
OBSAI 768M mainstream
OC12 CPRI 614M
HD-SDI
SDI
OC3
0.1
1985 1990 1995 2000 2005 2010
Protocol standard completion d t
P t l t d d l ti date
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23. Move to 28 Gbps
 For the highest data rate and bandwidth
applications
 100 Gigabit Ethernet
 Optical interface is moving to 4x25G and 4X28G
 Size and cost reduced optical module
 Power efficiency (per Gbps)
 200mW / channel
Standards: 100 GbE, OTU-4 100G CFP Optical Module
 Electrical specs: CEI-28G
CEI 28G
10 @ 11.3 Gbps 4 @ 28 Gbps
28 Gbps Enables Greater System Integration and Lower System Cost
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24. Signal Integrity Challenge
 Electrical signal from point A needs to be delivered to point B
 Point A: TX - transmitter, we refer to signal @ near-end
g
 Point B: RX - receiver, we refer to signal @ far-end:
 either inside device (RX output) or right before RX pins
 Via Interconnect: Link (IO card+back-plane+IO card)
Vi I t t Li k d b k l IO d)
receive device
transmit device RX output
A far-end eye B
near-end eye
TX RX
I/O card
connector
backplane
p
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25. Why the Challenge?
 Inside interconnect:
Incident  Attenuation + Reflection + Radiation + Coupling  Transmitted
A B
TX RX
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26. Degradation is Proportional to Data Rate
0 dB is 100%
-5 dB is 56%
-10 dB is 32%
10
Collection of customer backplane
transfer functions
-40 dB is 1%
3.125 Gbps
6.25 Gbps
8.5 Gbps
-60 dB is 0.1%
10 Gbps
p
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27. Examples: 800mV FR4 6.375 Gbps
2-inch trace 10-inch trace 52-inch trace
CLOC PATTERN
CK
BS
PRB N
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28. Minimize Jitter Generation
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29. Power Supply Optimization
VccT VccL VccH
 Precision and dedicated voltage
supplies are provided for timing-
Tx path
TX
critical PLL components
serializer
 Voltage noise to timing jitter
Gnd
Gnd Gnd Gnd conversion is minimized
Tx VccH  < -55 dB reduction in power supply
Clock path
PLLs rejection ratio (PSRR)
Gnd Linear
Gnd
regulator  Separated and isolated power
Band gap
supply
VCOs  No power supply coupling
Charge pumps
Protected analog  Prevent uncorrelated noise pick-up
Gnd
 On-package decoupling (OPDs)
used appropriatel
sed appropriately
 To keep the transceiver immune from the
PLL external power supply noise
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30. Ring Oscillator (RO)
 Most widely used oscillator architecture for CMOS ICs
 Wide frequency tuning range: from 10-100 MHz to 1-10 GHz
y g g
 Because of the high gain:
 Sensitive to power supply and substrate noises
 Requires a high p
q g power supply rejections ratio
pp y j
 Offers good substrate isolation
 A 3-GHz CMOS VCRO (65 nm) achieves:
 A phase noise of -91 dBc/Hz at 1 MHz
91
 An RMS jitter (1-80 MHz) at 1.1 ps
 A 6-GHz VCRO in the same process achieves:
 A phase noise of -86 dBc/Hz at 1 MHz
 An RMS jitter (1-80 MHz) at 1.24 ps
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31. LC Oscillator (LCO)
 Existed in RF applications for a long time, only recently becoming
more common in mixed-signal IC design
 One reason: with shrinking technology inductors are becoming small enough to be
technology,
integrated on the die (still bigger than a ring oscillator, however)
 Superior phase noise performance because of its highly selective and
high quality
high-quality LC tank
 Limited frequency-tuning range: typically ~ 20%
 A 6-GHz LC in the same process has a phase noise of -110 dBc/Hz at
1 MHz and an RMS jitter (1-80 MHz) of only 100 fs
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32. Programmable LC PLL
 LC PLL frequency tuning range extension
LC
div/2
Diff Ref - VCO0
Output
Clock Input PFD CP / LF /L
LC
VCO1 div/2
/M
Data Rate
0.6 (Gbps)
3.25 12.5
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33. Jitter and Eye Performance for RO and LC
LC at 6.5 Gbps RO at 6.5 Gbps
RJ =605 fs
605 RJ =1.228 ps
1.228
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34. Improve Jitter Tolerance
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35. Hybrid Clock and Data Recovery (CDR)
 CDR has lock to clock and lock to data modes
lock-to-clock lock-to-data
 CDR is first locked to the reference clock, then switched to lock the data, providing fast
locking time
 No unlocked or out-of-lock problems when the received data has excessive jitter
 Reference clock jitter does not affect CDR jitter performance
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36. Phase Interpolator CDR
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37. Jitter Tolerance Comparison
<-40 dB/decade
tude
Magnit
-20 dB/decade
PLL/hybrid CR
PI CR
fPl fPLL Frequency
 Receivers have a hybrid phase-locked loop (PLL)-based CDR technology that
has the best jitter generation and jitter tolerance performance
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38. Transceiver Equalization
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39. Electrical Channel Characteristics
0 dB
-20 dB
20
-40 dB
$$
-60 dB
$
-80 dB
80
0 GHz 5 GHz 10 GHz 15 GHz
Tx/Rx Tx/Rx
Channel
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40. Physics for Electrical Channel Loss
Electrical loss function
0 2 4 6 8 10 12
0
-5
-10 Skin
15
-15
Loss (dB)
-20
-25 Dielectric
30
-30
-35
Skin + dielectric
-40
-45
-50
Frequency (GHz)
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41. Mechanisms for Equalization
0dB 0dB 0dB
f f f
Channel + Equalizer = Flat overall response
Tx equalizer: Rx equalizer:
pre-emphasis, linear (CTLE or FFE)
de-emphasis or adaptive (DFE)
Make the lossy channel a non-lossy channel
M k th l h l l h l
so the overall “effective channel” is an
“all-pass” function or has a flat response
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42. Tx Pre-emphasis
Channel/
medium
Tx EQ Rx
 Work up to 28Gbps in 28-nm CMOS process node
 Simple,
Simple easy to implement relatively less power
implement,
 Good control and testing
 Not suitable for fine-tuning adaptive/dynamic equalization
 Can
C amplify the noise
lif th i
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43. Pre-emphasis Opens Eye on 40” PCB @ 6 Gbps
3” PCB trace (FR-4 material)
40” PCB trace (FR-4 material)
Increasing pre-emphasis levels
Equivalent to driving a backplane @ 6g
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44. 6.25-Gbps Signal Degrades Over 40” of PCB
3 ones, 5 zeroes 1 3 4
Short trace (5”)
no pre emphasis
pre-emphasis
2
1
Short trace (5”)
4
Long trace (40”) 3
no pre-emphasis
2
Not DC balanced
Long trace ( )
g (40”)
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45. 6.25-Gbps Signal Improves With Pre-emphasis
3 ones, 5 zeroes 3 4
1
Short trace (5”)
with pre-emphasis
pre emphasis
2
1 Short trace (5”)
3 4
Long trace (40”)
with pre-emphasis 2
DC balanced
Long trace ( )
g (40”)
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46. Rx Equalization
Rx
Channel/medium
Eq. Data
Tx sample
l

 Well suited for fine-tuning adaptive/dynamic equalization
 Finite impulse response (FIR), infinite impulse response (IIR) and
(FIR) (IIR),
analog filters (such as FFE, DFE, and CTLE) are possible
 Lack of observability and relatively higher power consumption
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47. Continuous Time Linear Equalizer (CTLE)
 Continuous time, non-sampled
 Easy to implement, low p
y p power consumption
p
 Many equalizer stages can be added to increase the order and
the maximum boost in a given frequency interval
Equalizer Parasitic
pole pole
Gain
Equalizer
E li
zero
Frequency
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48. Four-Tap Linear Equalizer (CTLE)
32
30
28
26
24
22
High-frequency
DC gain 20
18
g
gain adjustment
j
adjustment
dj t t
16
14
dB(S(2,1))
12
10
[0dB-20dB]
[0dB-12dB] 8
6
4
2
0
-2
-4
-6
-8
1E7 1E8 1E9 6E9
Slope adjustment
freq,
freq Hz
[20dB-80dB]
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49. Equalizer Transfer Function
combined frequency response High
Medium
Low
Bypass EQ
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50. Equalization Simulation Example
 Optimize equalizer settings
 Simulate channel with transceiver
Receive Eye,
Channel Model No Equalizer
q
Receive Eye
With Equalizer
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51. CTLE Bandwidth
 Programmable bandwidth
CTLE to support 12.5G
p
backplane Gain
 20dB high-frequency gain
0 db
Freq
q
3.25 GHz
(6.5 Gbps)
6.25 GHz
(12.5 Gbps)
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52. Adaptive Equalization Example
RL1 RL2
OUTN OUTP
INP INN
M1 M2
RS
VEQ[1:4]
CV1 CV2
M3 M4
VVAR
RRGEN_BW[1:0]
VEQ1 VEQ2 VEQ3 VEQ4 VRGEN
RXin EQ EQ EQ EQ EQ_OUT RGEN_OUT
stage
1
stage
2
stage
3
stage
4
RGEN
Plug-and-play solution
VVAR
LPF[1:0] LPF HPF LPF HPF
HPF[1:0]
RGEN_C
G CTRL
Controls Adaptive (plug d l )
Ad ti ( l and play)
ADCE Rect Rect Rect Rect
changes over time,
(adaptive dispersion enabling link monitoring
compensation engine) State Machine
UP_DNN_LF
D2As
D2As
UP_DNN_HF
Adaptive
Engine
HF_OFFSET[2:0]
LF_OFFSET[2:0]
D2A controls
Sta Machine
CLK
controls
ate
D
Flexible PLD interface enables link monitoring usage
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.
52

53. 5-Tap Decision Feedback Equalizer
From Linear _ To CDR
Equalizer
Z-1
 C1
Z-1
1
C2
Z-1
C3
Z-1
 Work up to 12.5Gbps C4
 Improves signal-to-noise ratio (SNR)
p g ( ) Z-1
C5
 With CTLE, addresses
pre-cursor and post-cursor ISI
 Mitigates the effects of crosstalk
 Automatically adapts to PVT conditions
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.
53

54. On Die
On-Die Instrument
© 2010 Altera Corporation—Public

55. Why On-Die Instrument?
 On-Die Instrument can test/verify critical IC blocks
within the Rx that are not possible from an
external instrument
 CTLE gain and DFE coefficients
 Data and clock signal properties/jitter before the
sampler
 System debugging
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.
55

56. On-Die Instrument
 View receiver signal margin up to 12.5 Gbps
 Complete vertical and horizontal reconstruction of eye opening
 Uninterrupted datapath for live debug capability
EyeQ
Pre-
Emphasis EQ CDR
Lossy Medium
Tx Rx
Minimize Board Bring Up / Debug Time With
Dynamic Reconfiguration and E Q
D i R fi ti d EyeQ
© 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
56

57. On-Die Instrument Circuit
EQ: Equalizer
Q q
PD: Phase Detector
CP: Charge Pump
VCO: Voltage Controlled Oscillator
RX PI: Phase Interpolator
Sampler A
S l o
OUT
Multi - Recovered
Deserializer
plexer Data
RX
Input EQ PD 1
CDR  64 vertical threshold le els
ertical levels
CP VCO  32 horizontal phase-
interpolator steps
EYE  3ps / steps (@ 10 Gbps)
o  User-selectable threshold /
Multi - Recovered
Logic
PI
Clock PI setting
plexer
1
VREF_G
EN
BIT BitErr
Checker
Sampler B
New in SV
© 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
57

58. Altera’s 28 nm Transceivers are Working!
Die Layout
e ayou
12.5 Gbps
Eye Diagram
© 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
58

59. Summary
 Advanced oscillator and hybrid CDR enables 28Gbps at
the 28-nm CMOS process node in FPGAs
 Comprehensive equalizations for 12.5Gbps backplane
 On-Die instrument for system debug
y g
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.
59