Developments of the SoC for High-Multi-Level QAM 1 Gbps Class Wireless System               and its Evaluation with RF Har...
internal PLL. Figure 1 describes the SoC block diagram,                  signal as the unwanted noise. In particular, this...
Furthermore, by adopting InP type MMIC for LNA to                                                                         ...
design target was unachieved” was in a situation.                                                                       sy...
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  1. 1. Developments of the SoC for High-Multi-Level QAM 1 Gbps Class Wireless System and its Evaluation with RF Hardware of 38 GHz Band FWA Toru Taniguchi1, Kazuya Kojima1, Akira Matsuzawa2, Kouji Matsunaga3, Yasutake Hirachi4 1 Laboratory, Research & Development Center, Japan Radio Co., Ltd., Tokyo, Japan 2 Department of Physical Electronics, Tokyo Institute of Technology, Tokyo, Japan 3 System IP Core Research Labs, NEC Corporation, Tokyo, Japan 4 AMMSYS Inc, Tokyo, Japan Abstract — Since 2008, we have been developing the [3] under incorporating in the 38 GHz band FWA system. integrated SoC, which incorporates from the ultra high This time, we equipped the SoC with ultrafast high- speed multi-level QAM modem to the gigabit Ethernet resolution ADC/DAC so that it can support the interface, in a bid to adapt to the millimeter wave broadband wireless system. In 2009, we developed the SoC that multileveled 64QAM, which will likely enable the 1 functions on its maximum modulation clock 200 MHz, single- Gbps-class system as our initial objective. carrier 16QAM, and TDD, and managed to conduct field evaluation tests as a state of actual operation of 38 GHz band II. IMPROVED SOC P-P FWA system. This time, we have increased the resolution of ADC/DAC incorporated in the SoC, and made design Our research project has aims that actually enable the improvements to suppress the internal clock jitter, and high-density transmission by multilevel I/Q modulation finally managed to develop a prototype SoC for the wireless technology in millimeter wave range. As in these step by system, which enables 64QAM operations (on architecture of step processes, we would actualize an easy constructing of the modem, maximum multi-level is 256QAM) and also actualized an effective throughput of 1 Gbps. the effective 1 Gbps-class radio system with a stable link quality by developing the SoC. Hence we upgraded this Index Terms — Broadband, Wireless, Millimeter wave, first-generation SoC as above and we would like to report Multi level QAM, I/Q modulation, SoC, single carrier, TDD for new SoC which has a potential to operate 256QAM in this time. We changed its performance by increasing the I. INTRODUCTION resolution of ADC/DAC architecture from 8 bits / 10 bits to 10 bits / 12 bits with suppressing the clock jitter on Since applications on the IP network have rapidly improved and their data volumes are still growing, there Table 1. The major functional characteristics of the SoC. are compelling needs for the large-capacity connecting- Process CMOS 90 nm technology devices for constructing their network. At the same time, Circuit size 40 million transistors styles of connection demands themselves are getting Supply voltage I/O voltage 3.3 V, Core voltage 1.2 V Power 2.5 W (typ.) shifted from the conventional desktop PC to the mobile Chip size 5 mm × 10 mm style in order to connect anywhere user on infallibility. ADCs 10 bit / 400 Msps (ENOB=8 bits) Hence, the number of base stations is increasing and DACs 12 bit / 800 Msps corresponding backhaul requirements tend to include not PLL Jitter ±50 psec peak or less only fixed fiber-devices but also more flexible wireless Communication scheme Single carrier TDD Modulation scheme QPSK, 16QAM, 64QAM devices. In this background, it seems desirable to come FEC (255, 239) Reed Solomon true the wireless system of millimeter wave which is Radio symbol frequency 200 MHz (max.) relatively easy to get the wide band spectrum, it is Band limited filter Root raised cosine filter (alpha=0.5) compact, it has large capacity, and its setting is so easy. GE-MAC Conformance to IEEE 802.3 and IEEE 802.1Q Therefore, we are developing the SoC which was Effective throughput 970 Mbps (max.) combined the all core circuits such as ultrafast multi-level QAM modem, linear frequency equalizer, MAC, error Flash Temperature SDRAM EEPROM SDRAM Synthesizer correction, interface and CPU for the wireless system, Memory Sensor then we would realize the 1 Gbps-class simple single- carrier TDD radio system such as very compact and large CPU Core and Peripheral Circuits capacity by integrating this SoC into a small-size Gigabit Et hernet I/Q Quadrature Modulator and hardware which is most characterizing of the millimeter D/A Converter Demodulator Transceiver Gigabit 12bit/800Msps R adio QAM Ethernet Framer MAC Modem wave device. In addition, before the end of 2009, we MAC A/D Converter 10bit/400Msps developed in advance the SoC [1] that supports 16QAM Network Interface Block QAM Modem Block D/A and A/D Converters on system clock 200 MHz, and managed to conduct Baseband Processing SoC performance evaluation for a 600 Mbps-class system [2] Figure 1. Block diagram of the SoC.978-1-4244-8971-8/10$26.00 c 2010 IEEE
  2. 2. internal PLL. Figure 1 describes the SoC block diagram, signal as the unwanted noise. In particular, thisand Table 1 indicates major functional characteristics of phenomenon seems to be almost same as affecting the linkthe SoC. As we can see in Table 1, the new SoC should quality with adding so-called background noise bymake suppressing the jitter as making its peak upper limit decreasing of DAC’s or ADC’s resolution. In±50 psec as 1/100 of the symbol speed, thereby the SoC consideration for the above, it was decided on the jitterwill be able to get to effective operation on the high-level specifications of this SoC to control a background noise ofof ADC/DAC resolution, as features to upgrade. For C/N = 36 dB to become the fixed degradation conversionexample, Figure 2 shows the situation of influence process (BER=1e-6) 0.5 dB equivalency by 64QAM system of α =of sample timing jitter in ADC of receiver side. That is, 0.5 and also the fixed degradation conversion 2.5 dBwhen a jitter ingredient is performed addition of by equivalency by 256QAM as the acceptable upper limit.internal clock of SoC, the reception baseband signal onADC is sampled by the timing, which has the error of the III. IMPROVEMENT TO ANALOG CIRCUIT AROUND SOCjitter. However, the data which an ADC stored once with We mainly upgrade SoC’s functions themselves tothe amplitude direction error are processed as sampled by support at least 64QAM, but the radio system gaina correct timing, because these data are handled only as a increase on analog area around the SoC is also necessary.simple chronological ordered series-data by the following Table 2 describes specification of the 64QAM radiorecovery circuit. On the other hand, the timing fluctuation system, and Figure 4 describes an example of link budgetof clock jitter in DAC of transmission side is reflected as a design of this system for the rainfall model of Tokyo,horizontal vibration of the baseband transmission Japan We are aiming to achieve a non-operating ratio ofwaveform like Figure 3, and as a result, it is reflected as a 1E-4 (50 minutes per year) or less, on the 1 km link. Tophase error at the decision timing in the demodulation satisfy this target specification with the 64QAM system, 6system. However, after all, it can consider that it equal the dB of the system gain increasing is necessary compared toarriving signal added with the amplitude error at the 16QAM preceding system. These circumstances aredemodulator circuits, if it sampled by the ADC, which has synonymous with situations that the required C/N forno jitter as ideal. Therefore, when the row of arriving data 64QAM system becomes 27 dB whereas required C/N forto demodulator would be observed, it will be able to 16QAM system was 20.5 dB. Our new system assignshandle as the simple sum of both amplitude error necessary additional system gain of 6 dB, such asgenerated by the each influence of the sampling timing transmission output has been increased by 3 dB, andfluctuation at DAC and ADC. By the way, demodulator receiver’s NF has been reduced by 3 dB.should process with the quantized data row, as a result the Improving PA is necessary for securing the system gainstep function like amplitude error is mixed into receiver of the transmitting side, but of course, at least 3 dB of djn djn+1 djn+2 djn+3 djn+4 djn+5 djn+6 back-off from 1 dB compression level is necessary. In case of our target, that maximum output level is 27 dBm at QPSK-operation to the long span. That is to say, under considering a loss of 2 dB for antenna connection and due to the spurious suppression waveguide filter, we have to select an A-class amp whose 1 dB comp level is 32 dBm. When we want to enable this grade PA by usual GaAS MMIC, normally we choose 6-parallel structure by 27 dBm class MMIC to avoid heat concentration with nT (n+1)T (n+2)T (n+3)T (n+4)T (n+5)T (n+6)T consideration of connection loss between each MMIC. Figure 2. The influence process of sample timing jitter in ADC. Hence, we must allow estimated 20 W of power djn djn+1 djn+2 djn+3 djn+4 djn+5 djn+6 consumption for PA. Therefore, our new system adopted GaN MMIC that has higher Tjmax and can withstand heat concentration, and deployed all the necessary parallel connections as 4-parallel by improving the connection loss within MMIC chip , and we would reduce the PA power consumption to 15 W. Figure 5 shows, the chip face of GaN MMIC that was designed for our 38 GHz band FWA as above. At the same time, as for improving receiver’s NF, we made gain approximately 1.5 dB by nT (n+1)T (n+2)T (n+3)T (n+4)T (n+5)T (n+6)T reviewing system gain assignments on receiver circuit Figure 3. The influence process of sample timing jitter in DAC. blocks, improving antenna’s return loss, and shortening the connection length of each device, and so on.
  3. 3. Furthermore, by adopting InP type MMIC for LNA to IV. PERFORMANCE OF IMPROVED SOCreduce LNA’s NF by about 1.5 dB, we managed to total Figure 6 describes BER vs. C/N characteristics onNF = 5 dB or less. Figure 5 is InP MMIC’s chip face baseband-interconnection of the new SoC which is givenwhich was estimated for NF = 2.5 dB with 20 dB gain. upgraded 256QAM modem architecture and high- resolution ADC/DAC. An added noise that was set by the Table 2. The major specification of the 38 GHz 64QAM system. C/N parameter is generated by the pseudo-noise simulator Radio frequency 38.270 / 39.270 GHz (Center frequency) of the SoC of the transmitting side. As the figure shows, Frequency stability 5 ppm or less the BER curve of 64QAM goes down smoothly to the Duplex TDD (Time Division Duplex), vicinity of 1e-6 of BER, which indicates a good condition. frame period 0.5 msec However, from the vicinity of 1e-14 of BER, the BER Tx power +27.0 dBm (QPSK), +24.4 dBm (16QAM), curve goes to saturation as adding quantization noise by +23.3 dBm (64QAM) the minimum resolution limitation appears in the Tx power stability -3.0 to +1.7 dB (±50 %) background. Thus, this BER curve has about 1 dB of Maximum Rx input -30 dBm deviation from the theoretical value at the vicinity of 1e-6 Passband bandwidth 260 MHz or less of BER even though the curve seems smooth. It is NF (Noise figure) 5 dB max. Network interface 10/100/1000 BASE-T (full/half/auto) estimated these degradation occur by the insufficient Antenna waveguide slot array (32 dBi) situation of “sampling jitter suppressing” which is Optional function Adaptive transmission power control, described in SoC improvements. In fact, we measured Adaptive modulation method switch, ±240 psec peak of clock jitter generated within the SoC, QoS control, which is almost five-fold of the designed value. At re- Adaptive data bandwidth shaping, Remote system monitoring calculation under the situation that induced the affect to both side of DAC/ADC for consideration, this effect indicates that we can only secure approximately 31 dB of 1.0E-03 equivalent background C/N in DAC/ADC, compared to 200 min. / 1 year the design estimation value of 36 dB. As we can see the simultaneously plotted in Figure 6, what the re-calculated Non-operating ratio par 1 year 1.0E-04 20 min. / 1 year BER curve as include the background C/N effects are well equal to the measured BER. This means our new 1.0E-05 prototype SoC has not satisfied the objective of 2 min. / 1 year suppressing the internal clock jitter. However, in terms of 1.0E-06 matching of measured BER as indication in Figure 6, most QPSK dominant factor of fixed degradation affecting the link 16QAM 64QAM quality is the sampling jitter on DAC/ADC. On the other 1.0E-07 hand it is actual fact that it was able to come true about 100 1000 10000 Maximum service distance [m] “the stable function of 64QAM” from this thing in this version SoC. That is, at the side of SoC trial work, “partial Radio frequency: 38 GHz Antenna gain: 32 dBi Noise figure: 5dB Equivalent noise bandwidth: 200 MHz Tx level: +27.0dBm(QPSK), +24.4dBm(16QAM),+23.3dBm(64QAM) 1.E-02 Required Rx level: -73 dBm(QPSK), -64 dBm(16QAM),-57dBm(64QAM) background: C/N = 31dB Distribution of accumulated rainfall: 1.66 mm/min. 1.E-03 1.E-04 Figure 4. Calculation of link budget for the 38 GHz 64QAM system. 1.E-05 measured QPSK BER on BB-pair 1.E-06 measured 16QAM BER on BB-pair BER 1.E-07 measured 64QAM BER on BB-pair measured 256QAM BER 1.E-08 on BB-pair theoretical BER 3.1mm 1.44mm 1.E-09 calculated BER 1.E-10 with Background 1.E-11 3.8mm 1.64mm 1.E-12Figure 5. The chip surface photograph of GaN PA MMIC (left side) 5 10 15 20 25 30 35 40 45 and InP LNA MMIC (right side). C/N [dB] Figure 6. BER vs. C/N characteristics on the BB-interconnection.
  4. 4. design target was unachieved” was in a situation. symptom. However, by activating FEC built in the SoC, itHowever, as a result, transmission rate increase task target can considerably expect that the saturated remaining BERabout “effective transmission rate of 1 Gbps” at this time will be corrected, so that in fact, we can observe an almostbecame the form called the accomplishment. error-free state during a short period. Figure 8 describes the effective throughput in the link situation using this V. EVALUATION OF RADIO SYSTEM EQUIPPED FEC. We could verify 1 Gbps, as our first objective, at the WITH NEW SOC ends of the Ether interface of the direct RF connection test system. That means degradation factors causing saturated We verified that the 64QAM transmission performance remaining BER are well randomized, since FEC functionsof new SoC described in Figure 6 reappears on the well for the residual BER as effectively. Therefore, itexisting RF hardware of the 600 Mbps class 38 GHz radio show we will be able to get the transmission performancesystem. Figure 7 indicates the result with a BER curve described same level to Figure 6, when we will adapt thecorresponding to the receiving level. Note that we have new SoC in the improved RF hardware for 64QAMnot completed upgrading the hardware side to introduce transmission in future.64QAM as described in the previous section, and that thisevaluation is provisional since we used existing hardware VI. SUMMARYfor the current evaluation to debug new SoC’s functions.Figure 7 shows saturation in the vicinity of 1e-7 of BER at For the purpose of enabling the 1 Gbps-order, superhigher reception level, which clearly indicates the effects wideband millimeter wave transmission system, which isof degradation of amplitude distortion on HPA or same so compact and low cost for easy dissemination, we are developing about all-in-one SoC produced using the 90 n 1.E-02 theoretical BER: NF=4.5dB CMOS technology. This time, we managed to develop a measured QPSK BER new SoC that enables the 1 Gbps effective transmission 1.E-03 rate at 64QAM, and to reach the phase that we can on RF-ports pair measured 16QAM BER 1.E-04 on RF-ports pair measured 64QAM BER practically evaluate it. Also, we verified the link on RF-ports pair performance under RF-interconnection, by end to end 1.E-05 Ether-interface evaluation, by using the existing 38 GHz BER 1.E-06 band 600 Mbps class FWA system. We will continue to 1.E-07 upgrade RF hardware to introduce 64QAM according to the initial plan, and would conduct operation 1.E-08 demonstration assessments in actual fields. 1.E-09 1.E-10 ACKNOWLEDGEMENT -80 -75 -70 -65 -60 -55 -50 -45 -40 Receiving Level [dBm] We reported the SoC that will be the core to enable the next generation super wideband radio system. We wish toFigure 7. BER vs. Receiving level on the RF-interconnection state. thank all those who helped us conduct this research: Professor Makoto Ando, Tokyo Institute of Technology, Dr. Kenkichi Hirade, Japan Radio Co., Ltd. 1000 900 REFERENCES 800 [1] K. Kojima, Y. Toriyama, T. Taniguchi, M. Miyahara, and 700 A. Matsuzawa, “Development of Baseband Processing SoC with Ultrahigh-Speed QAM Modem and Broadband Radio Throughput [Mbps] 600 System for Demonstration Experiment Thereof, ” IEEE 500 ICECS 2009, Tunisia, pp. 687-690, Dec. 2009. 400 [2] Y. Toriyama, K. Kojima, T. Taniguchi, M. Zhang, and J. 300 Hirokawa, “Multi-level QAM single-carrier high-efficiency QPSK Throughput broadband wireless system for millimeter-wave 200 16QAM Throughput applications, ” IEEE RWS 2010, New Orleans, pp. 677-680, 100 64QAM Throughput Jan. 2010. 0 [3] S. Nagamine, F. Ozawa, T. Shirosaki, T. Taniguchi, and K. -80 -75 -70 -65 -60 -55 -50 -45 -40 Okada, “Multifunctional frequency converter MMIC for Receiving Level [dBm] 38GHz band 600Mbps multi-level QAM wireless system, ” Figure 8. Effective throughput on the RF-interconnection state IEEE RFIT 2009, Singapore, pp. 229-232, Dec. 2009. in a case functionalizing FEC.