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ADS Workshop on PCI Express(r)

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Colin Warwick
Colin Warwick

At multigigabit per second data rates and with channel flight times longer than a bit period, signal integrity is a major concern. Under these conditions, high-speed analog effects, previously only seen in high frequency RF and microwave engineering, can impair the signal quality and degrade the bit error rate of the link. This hands-on workshop will show you how use Advanced Design System (ADS) to dramatically reduced product design cycles by resolving these issues early in the design cycle. Using PCI Express serial link as an example, we’ll illustrate how you can: Analyze complete serial links by co-simulating individual components, each at its most appropriate level of abstraction: link-, circuit- or physical-level. Import S-parameter backplane and interconnect models accurately into transient (SPICE) simulations. Perform jitter diagnosis with the proven EZJIT Plus algorithm used in Agilent instruments.

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ADS Workshop on PCI Express® PCI EXPRESS is a registered trademark of the PCI –SIG FTE 2008 AE22 Lab: PCI- ExpressGroup/Presentation Title Page 1 2008-May-05MonthRestricted Agilent ##, 200X
Agenda • Brief introduction to key specifications • Create and analyze PCI Express channel PCI Express Workshop – Version 1 2
PCI Express Physical Channel Point to Point serial link communication PCI Gen1 – 2.5 GT/s/lane (Giga transfer per second) PCI Gen2 – 5.0 GT/s/lane Each lane is AC coupled Transmit PCI Express Connector Device A Device B Receive • AC coupling capacitor lane • Min value – 75 nF • Max value – 200 nF • Preferred value 100 nF • Size 0402 provide best performance 0603 is fair • Should be symmetrically placed with in a diff pair PCI Express Workshop – Version 1 3
Transmit Signal Specifications Differential Peak to Peak Output Voltage 0.4 V (min) 0.266 V (min) 0.6 V (max) 0.4 V (max) VTX-DIFFP-P = 2*|VTX-D+-VTX-D-| = 0.8 V (min.) = 1.2 V (max.) De emphasized Bit 0V VTX-Diff-P-P (max) =0.566V (3 dB) VTX-DE-RATIO = -3.5 dB (Typ.) VTX-Diff-P-P (min) =0.505V = -3.0 dB (Min.) (4 dB) = -4.0 dB (Max.) Transition Bit VTX-Diff-P-P (min) =0.8V 2.5G de-emphasis = -3.5 +/- 0.5 0.7 UI 5G de-emphasis = -3.5 +/- 0.5 OR -6.0 +/- 0.5 Eye mask Low swing voltage levels = no de-emphasis PCI Express Workshop – Version 1 4
Transmit Signal Specifications Rise and Fall Time Trise > 0.125 UI Tfall > 0.125 UI Measured between 20-80% at transmitter package pins PCI Express Workshop – Version 1 5
PCI Tx/Rx Return Loss – Return Loss • RLTX-DIFF 10 dB measured over 50 MHz to 1.25 GHz • RLTX-CM 6 dB measured over 50 MHz to 1.25 GHz – Differential Impedance – 100 Ohms (Typ.) – 80 Ohms (Min.) – 20 Ohms (Max.) – Unit Interval (UI) – 400 ps (Typ.) – 399.88 ps (Min.) – 400.12 ps (Max.) • Differential return loss measured for package + Rx die • Differential return loss Requirements : -10 dB or better • Die termination should be 50 Ohms PCI Express Workshop – Version 1 6 age 6 P
Simulation Compliance Eye TTX-MAX-JITTER = 1-TTX-EYE 0.75 UI = 0.25 UI Rather than including jitter in the simulation, include its effects to qualify eye diagram performance VTX-Diff-P-P (min) =0.175V TX Jitter Simulation Compliance Eye 0V + = PCI Express Workshop – Version 1 7
Receiver Eye Mask 0.0875 V (min.) 0V VTX-Diff-P-P (min) =0.175V 0.4 UI PCI Express Workshop – Version 1 8
Stackup and Trace Topologies • Four layer stackup (0.062 in PCB) with 0.5 Oz copper for microstrip • 1 Oz copper for 6+ layer strip line structure • Trace length matching between pairs not required due to embedded clock and lane de-skew in the receiver – Makes routing easier and longer trace traces feasible (max lane to lane skew is 1.6 ns) • Max. recommended trace length on system board < 12 in • Max. recommended trace length on add in card < 3.5 in • Maximum skew tolerable within differential pair is 5 mil for add in card, 10 mil for system board Non Interleaved Interleaved TX TX TX RX TX RX 5 mil 7 mil 20 mil 4.4 mil 4.4 mil VCC VCC 47 mil 47 mil VSS VSS 4.4 mil 4.4 mil PCI Express Workshop – Version 1 9
System Jitter Budget for 2.5 GT/s Jitter Contribution Min Rj (ps) Max Dj (ps) Tj at BER 10-12 % (ps) @ 2.5 GT/s TX 2.8 60.6 100 22 Ref Clock 4.7 41.9 108 23 Media 0 90 90 20 RX 2.8 120.6 160 35 Linear Total Tj 458 Root Sum Square 399.13 (RSS) Total Tj The Rj of the components are independent and convolve as the root sum square. RSS equation for BER 10-12 Tj = Σ Djn +14.069 *√ Σ Rjn2 PCI Express Workshop – Version 1 10
System Jitter Budget for 5 GT/s Jitter Contribution Min Rj (ps) Max Dj (ps) Tj at BER 10-12 % (ps) @ 5 GT/s TX 2.8 30 50 22 Ref Clock 4.7 0 43.6 19 Media 0 58 58 25 RX 2.8 60 80 34 Linear Total Tj 231.6 Root Sum Square 200 (RSS) Total Tj The Rj of the components are independent and convolve as the root sum square. RSS equation for BER 10-12 Tj = Σ Djn +14.069 *√ Σ Rjn2 PCI Express Workshop – Version 1 11
PCI Express Link Components • Transmitters/Receivers on an ASIC on a system board • Package • Via breakout • Differential transmit/receive traces on system board • Via for signal transition to inter-layer • PCI Express connector and add-in card interface/riser card interface • Differential transmit/receive traces on add-in card • AC-coupling capacitors • Transmitter/Receivers on an ASIC on the add-in card PCI Express Workshop – Version 1 12
Exercise 1. Create a PCI Express source in ADS 2. Create a PCI Express simulation compliance transmitter mask 3. Create a second source with jitter added PCI Express Workshop – Version 1 13
PCI-Express Design Guide Allow easy setup and simulation of a PCI Express Channel Provides – Easy simulation setup – Representative channel components – Allow you to quickly predict the effect of your design on the system performance PCI Express Workshop – Version 1 14
Component of PCI Express Design Guide • Transmitter – Source with de-emphasis – Source with jitter – SERDES model • Channel – Packages model – Via breakout – Daughter card traces – PCI-Express connector – System board trace • Eye mask – Transmit mask – Receive mask • Physical components – Package – Add card trace PCI Express Workshop – Version 1 15
Create a PCI Express Compliance Source in ADS • Transmitter data rate 2.5 Gbps (400 ps) • Output voltage level for the transition bit 400 mV • De-emphasis 3.5 dB • Rise/fall time (20-80%) 0.125 UI • Rise/fall time mismatch 0.10 UI (max) • Random jitter 2.8 ps • Periodic jitter 60.6 psec (1.5 MHz) • Total jitterp-p 0.25 UI • Common mode voltage level 0V • Output differential impedance 100 Ohms PCI Express Workshop – Version 1 16
Exercise -1 • Simulate PCI Express Transmitter Run simulation PCI Express Workshop – Version 1 17
Eye Diagram Voltage Level Of Differential Signal Data Rate Differential Voltage De-emphasis Level Transition Bit Mask De-emphasized Bit Mask Exercise: Change the eye diagram measurement for single ended voltage Exercise: Plot time domin voltage waveform PCI Express Workshop – Version 1 18
Single Ended Eye Diagram PCI Express Workshop – Version 1 19
Eye Diagram (contd.) Change De-emphasis Level De-emphasized Bit Mask PCI Express Workshop – Version 1 20
PCI Express Source with Jitter Run simulation Jitter parameters PCI Express Workshop – Version 1 21
Basic PCI Express Channel Simulation 16” Channel PCI Express Workshop – Version 1 22
Receive Mask Testing Mask includes transmitter contribution due to jitter Mask will automatically position itself in the center of eye PCI Express Workshop – Version 1 23
Channel with Via Models PCI Express Workshop – Version 1 24
Tuning Interconnect Parameters PCI Express Workshop – Version 1 25
Modeling Crosstalk Channel PCI Express Workshop – Version 1 26
Exercise- Package Simulation PCI Express Workshop – Version 1 27
PCI Express Connector Simulation PCI Express Workshop – Version 1 28
Exercise-5 Create a PCI Express Channel Transmitter Package Via breakout Daughter card trace Connector System board trace Via breakout Package PCI Express Workshop – Version 1 29
Exercise-5 Create a PCI Express Channel Transmitter Package Via breakout Daughter card trace Connector System board trace Via breakout Package PCI Express Workshop – Version 1 30
Create a PCI Express Channel (contd.) Transmitter Package Via breakout Daughter card trace Connector System board trace Via breakout Package PCI Express Workshop – Version 1 31
Create a PCI Express Channel (contd.) Transmitter Package Via breakout Connector Via breakout Package Node name: outp 4” trace 12” trace Node name: outp R= 50 Ohm C= 2 pF Add in Card Trace System Board Trace PCI Express Workshop – Version 1 32
Simulated Data 200 100 outp, mV 0 -100 -200 0 20 40 60 80 100 time, nsec 0.4 0.2 outp-outn 0.0 -0.2 -0.4 0 20 40 60 80 100 time, nsec PCI Express Workshop – Version 1 33
Eye Diagram Plot 0.4 0.2 eye_plot 0.0 How do we create eye mask? -0.2 -0.4 0 100 200 300 400 500 600 700 800 900 time, psec PCI Express Workshop – Version 1 34
Install Mask Templates PCI Express Workshop – Version 1 35
PCI Express Channel Simulation PCI Express Workshop – Version 1 36
Performance Comparison Add results from basic channel simulation and compare results Simple Channel Actual Channel PCI Express Workshop – Version 1 37
TDR Simulation System Board Trace Add-in Card Trace Package + Via breakout Connector Package + Via breakout PCI Express Workshop – Version 1 38
Layout Co-Simulation Package Model Add in Card Package Model PCI Express Workshop – Version 1 39
Momentum Simulation PCI Express Workshop – Version 1 40
Package Co-simulation PCI Express Workshop – Version 1 41
3D Preview of Package PCI Express Workshop – Version 1 42
Transistor Level Driver Model PCI Express Workshop – Version 1 43
Verification- Transmitter Eye Mask Where all we failed in the eye mask? PCI Express Workshop – Version 1 44
PCI Express Channel with Stratix-II GX Driver PCI Express Workshop – Version 1 45
Eye Diagram Performance PCI Express Workshop – Version 1 46
Equalizer Simulation Push inside and see details how equalizer is defined PCI Express Workshop – Version 1 47
Equalized Cable Simulation PCI Express Workshop – Version 1 48
Eye Diagram Performance PCI Express Workshop – Version 1 49
Using Frequency Domain Model to Create De- emphasis PCI Express Workshop – Version 1 50
Coder/De-Coder PCI Express Workshop – Version 1 51
Input and Output Data Stream PCI Express Workshop – Version 1 52

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ADS Workshop on PCI Express(r)

  • 1. ADS Workshop on PCI Express® PCI EXPRESS is a registered trademark of the PCI –SIG FTE 2008 AE22 Lab: PCI- ExpressGroup/Presentation Title Page 1 2008-May-05MonthRestricted Agilent ##, 200X
  • 2. Agenda • Brief introduction to key specifications • Create and analyze PCI Express channel PCI Express Workshop – Version 1 2
  • 3. PCI Express Physical Channel Point to Point serial link communication PCI Gen1 – 2.5 GT/s/lane (Giga transfer per second) PCI Gen2 – 5.0 GT/s/lane Each lane is AC coupled Transmit PCI Express Connector Device A Device B Receive • AC coupling capacitor lane • Min value – 75 nF • Max value – 200 nF • Preferred value 100 nF • Size 0402 provide best performance 0603 is fair • Should be symmetrically placed with in a diff pair PCI Express Workshop – Version 1 3
  • 4. Transmit Signal Specifications Differential Peak to Peak Output Voltage 0.4 V (min) 0.266 V (min) 0.6 V (max) 0.4 V (max) VTX-DIFFP-P = 2*|VTX-D+-VTX-D-| = 0.8 V (min.) = 1.2 V (max.) De emphasized Bit 0V VTX-Diff-P-P (max) =0.566V (3 dB) VTX-DE-RATIO = -3.5 dB (Typ.) VTX-Diff-P-P (min) =0.505V = -3.0 dB (Min.) (4 dB) = -4.0 dB (Max.) Transition Bit VTX-Diff-P-P (min) =0.8V 2.5G de-emphasis = -3.5 +/- 0.5 0.7 UI 5G de-emphasis = -3.5 +/- 0.5 OR -6.0 +/- 0.5 Eye mask Low swing voltage levels = no de-emphasis PCI Express Workshop – Version 1 4
  • 5. Transmit Signal Specifications Rise and Fall Time Trise > 0.125 UI Tfall > 0.125 UI Measured between 20-80% at transmitter package pins PCI Express Workshop – Version 1 5
  • 6. PCI Tx/Rx Return Loss – Return Loss • RLTX-DIFF 10 dB measured over 50 MHz to 1.25 GHz • RLTX-CM 6 dB measured over 50 MHz to 1.25 GHz – Differential Impedance – 100 Ohms (Typ.) – 80 Ohms (Min.) – 20 Ohms (Max.) – Unit Interval (UI) – 400 ps (Typ.) – 399.88 ps (Min.) – 400.12 ps (Max.) • Differential return loss measured for package + Rx die • Differential return loss Requirements : -10 dB or better • Die termination should be 50 Ohms PCI Express Workshop – Version 1 6 age 6 P
  • 7. Simulation Compliance Eye TTX-MAX-JITTER = 1-TTX-EYE 0.75 UI = 0.25 UI Rather than including jitter in the simulation, include its effects to qualify eye diagram performance VTX-Diff-P-P (min) =0.175V TX Jitter Simulation Compliance Eye 0V + = PCI Express Workshop – Version 1 7
  • 8. Receiver Eye Mask 0.0875 V (min.) 0V VTX-Diff-P-P (min) =0.175V 0.4 UI PCI Express Workshop – Version 1 8
  • 9. Stackup and Trace Topologies • Four layer stackup (0.062 in PCB) with 0.5 Oz copper for microstrip • 1 Oz copper for 6+ layer strip line structure • Trace length matching between pairs not required due to embedded clock and lane de-skew in the receiver – Makes routing easier and longer trace traces feasible (max lane to lane skew is 1.6 ns) • Max. recommended trace length on system board < 12 in • Max. recommended trace length on add in card < 3.5 in • Maximum skew tolerable within differential pair is 5 mil for add in card, 10 mil for system board Non Interleaved Interleaved TX TX TX RX TX RX 5 mil 7 mil 20 mil 4.4 mil 4.4 mil VCC VCC 47 mil 47 mil VSS VSS 4.4 mil 4.4 mil PCI Express Workshop – Version 1 9
  • 10. System Jitter Budget for 2.5 GT/s Jitter Contribution Min Rj (ps) Max Dj (ps) Tj at BER 10-12 % (ps) @ 2.5 GT/s TX 2.8 60.6 100 22 Ref Clock 4.7 41.9 108 23 Media 0 90 90 20 RX 2.8 120.6 160 35 Linear Total Tj 458 Root Sum Square 399.13 (RSS) Total Tj The Rj of the components are independent and convolve as the root sum square. RSS equation for BER 10-12 Tj = Σ Djn +14.069 *√ Σ Rjn2 PCI Express Workshop – Version 1 10
  • 11. System Jitter Budget for 5 GT/s Jitter Contribution Min Rj (ps) Max Dj (ps) Tj at BER 10-12 % (ps) @ 5 GT/s TX 2.8 30 50 22 Ref Clock 4.7 0 43.6 19 Media 0 58 58 25 RX 2.8 60 80 34 Linear Total Tj 231.6 Root Sum Square 200 (RSS) Total Tj The Rj of the components are independent and convolve as the root sum square. RSS equation for BER 10-12 Tj = Σ Djn +14.069 *√ Σ Rjn2 PCI Express Workshop – Version 1 11
  • 12. PCI Express Link Components • Transmitters/Receivers on an ASIC on a system board • Package • Via breakout • Differential transmit/receive traces on system board • Via for signal transition to inter-layer • PCI Express connector and add-in card interface/riser card interface • Differential transmit/receive traces on add-in card • AC-coupling capacitors • Transmitter/Receivers on an ASIC on the add-in card PCI Express Workshop – Version 1 12
  • 13. Exercise 1. Create a PCI Express source in ADS 2. Create a PCI Express simulation compliance transmitter mask 3. Create a second source with jitter added PCI Express Workshop – Version 1 13
  • 14. PCI-Express Design Guide Allow easy setup and simulation of a PCI Express Channel Provides – Easy simulation setup – Representative channel components – Allow you to quickly predict the effect of your design on the system performance PCI Express Workshop – Version 1 14
  • 15. Component of PCI Express Design Guide • Transmitter – Source with de-emphasis – Source with jitter – SERDES model • Channel – Packages model – Via breakout – Daughter card traces – PCI-Express connector – System board trace • Eye mask – Transmit mask – Receive mask • Physical components – Package – Add card trace PCI Express Workshop – Version 1 15
  • 16. Create a PCI Express Compliance Source in ADS • Transmitter data rate 2.5 Gbps (400 ps) • Output voltage level for the transition bit 400 mV • De-emphasis 3.5 dB • Rise/fall time (20-80%) 0.125 UI • Rise/fall time mismatch 0.10 UI (max) • Random jitter 2.8 ps • Periodic jitter 60.6 psec (1.5 MHz) • Total jitterp-p 0.25 UI • Common mode voltage level 0V • Output differential impedance 100 Ohms PCI Express Workshop – Version 1 16
  • 17. Exercise -1 • Simulate PCI Express Transmitter Run simulation PCI Express Workshop – Version 1 17
  • 18. Eye Diagram Voltage Level Of Differential Signal Data Rate Differential Voltage De-emphasis Level Transition Bit Mask De-emphasized Bit Mask Exercise: Change the eye diagram measurement for single ended voltage Exercise: Plot time domin voltage waveform PCI Express Workshop – Version 1 18
  • 19. Single Ended Eye Diagram PCI Express Workshop – Version 1 19
  • 20. Eye Diagram (contd.) Change De-emphasis Level De-emphasized Bit Mask PCI Express Workshop – Version 1 20
  • 21. PCI Express Source with Jitter Run simulation Jitter parameters PCI Express Workshop – Version 1 21
  • 22. Basic PCI Express Channel Simulation 16” Channel PCI Express Workshop – Version 1 22
  • 23. Receive Mask Testing Mask includes transmitter contribution due to jitter Mask will automatically position itself in the center of eye PCI Express Workshop – Version 1 23
  • 24. Channel with Via Models PCI Express Workshop – Version 1 24
  • 25. Tuning Interconnect Parameters PCI Express Workshop – Version 1 25
  • 26. Modeling Crosstalk Channel PCI Express Workshop – Version 1 26
  • 27. Exercise- Package Simulation PCI Express Workshop – Version 1 27
  • 28. PCI Express Connector Simulation PCI Express Workshop – Version 1 28
  • 29. Exercise-5 Create a PCI Express Channel Transmitter Package Via breakout Daughter card trace Connector System board trace Via breakout Package PCI Express Workshop – Version 1 29
  • 30. Exercise-5 Create a PCI Express Channel Transmitter Package Via breakout Daughter card trace Connector System board trace Via breakout Package PCI Express Workshop – Version 1 30
  • 31. Create a PCI Express Channel (contd.) Transmitter Package Via breakout Daughter card trace Connector System board trace Via breakout Package PCI Express Workshop – Version 1 31
  • 32. Create a PCI Express Channel (contd.) Transmitter Package Via breakout Connector Via breakout Package Node name: outp 4” trace 12” trace Node name: outp R= 50 Ohm C= 2 pF Add in Card Trace System Board Trace PCI Express Workshop – Version 1 32
  • 33. Simulated Data 200 100 outp, mV 0 -100 -200 0 20 40 60 80 100 time, nsec 0.4 0.2 outp-outn 0.0 -0.2 -0.4 0 20 40 60 80 100 time, nsec PCI Express Workshop – Version 1 33
  • 34. Eye Diagram Plot 0.4 0.2 eye_plot 0.0 How do we create eye mask? -0.2 -0.4 0 100 200 300 400 500 600 700 800 900 time, psec PCI Express Workshop – Version 1 34
  • 35. Install Mask Templates PCI Express Workshop – Version 1 35
  • 36. PCI Express Channel Simulation PCI Express Workshop – Version 1 36
  • 37. Performance Comparison Add results from basic channel simulation and compare results Simple Channel Actual Channel PCI Express Workshop – Version 1 37
  • 38. TDR Simulation System Board Trace Add-in Card Trace Package + Via breakout Connector Package + Via breakout PCI Express Workshop – Version 1 38
  • 39. Layout Co-Simulation Package Model Add in Card Package Model PCI Express Workshop – Version 1 39
  • 40. Momentum Simulation PCI Express Workshop – Version 1 40
  • 41. Package Co-simulation PCI Express Workshop – Version 1 41
  • 42. 3D Preview of Package PCI Express Workshop – Version 1 42
  • 43. Transistor Level Driver Model PCI Express Workshop – Version 1 43
  • 44. Verification- Transmitter Eye Mask Where all we failed in the eye mask? PCI Express Workshop – Version 1 44
  • 45. PCI Express Channel with Stratix-II GX Driver PCI Express Workshop – Version 1 45
  • 46. Eye Diagram Performance PCI Express Workshop – Version 1 46
  • 47. Equalizer Simulation Push inside and see details how equalizer is defined PCI Express Workshop – Version 1 47
  • 48. Equalized Cable Simulation PCI Express Workshop – Version 1 48
  • 49. Eye Diagram Performance PCI Express Workshop – Version 1 49
  • 50. Using Frequency Domain Model to Create De- emphasis PCI Express Workshop – Version 1 50
  • 51. Coder/De-Coder PCI Express Workshop – Version 1 51
  • 52. Input and Output Data Stream PCI Express Workshop – Version 1 52