Zuken - Improve pcb quality and cost with concurrent power integrity analysis - pcb west 2011

1. Improve PCB Quality and Cost withConcurrent Power Integrity AnalysisRalf Brüning, Product Manager High-Speed DesignSolutions/Senior PartnerHumair Mandavia, Senior Technical Marketing Manager

2. Agenda• Increasing challenges with power distribution systems on modern high-speed PCBs• The problem: – IC input impedance behavior – Resonance behavior of PDS – Role of decoupling capacitors• EDA methodology for concurrent power integrity simulation throughout PCB design process• Summary/Outlook PCB Design Problems PCB Design Problems2 © Zuken

3. Traditional Verification Disciplines3 © Zuken

4. Power Distribution SystemsDC Voltages are not equally distributed and not considered ideal over copper planes 3.27V 3.3V 3.25V Loads Voltage Source Example: 3.3V Power Distribution System“Voltage drops” occur on the copper area and within the vias4 © Zuken

5. Basic Electrical Concepts I V• Resistors dissipate energy – Resistance = Voltage / Current (R = V / I) R – Voltage = Current  Resistance (V = I  R) I• Capacitors store energy in an electric field VV V – Charge = Capacitance  Voltage (q = CV) + C – Current (q / time) = C  (V / t) (I = C  V / t) – Power plane over ground plane is a great capacitor! I / t V• Inductors store energy in a magnetic field + – Voltage = Inductance  (I / t) (V = L  I / t) L – Oppose current changes with a voltage – Inductive kick: pull the plug on a vacuum cleaner when it’s running!5 © Zuken

6. Voltage Supply for ICs:Power Distribution System (PDS)• The power distribution system (PDS) will provide voltages and charge to the ICs on a PCB• Charge on the board must be supplied over a broad frequency range: - Low frequency activities (we still have them) - In MHz range for CPU-peripheral interfaces - At the clock frequency (several hundreds of MHz) - Provide a low impedance path for parasitic voltages at various harmonics of the clock6 © Zuken

7. Power Plane Resonances ImpedanceBehavior• Power Plane Pair input impedance vs. frequency shows varied behavior in different ranges: Capacitive behavior (“DC”) Z=1/jC 2D-Resonances Continue to infinity… LC-Series resonance of the Inductive plate capacitor behavior of the with the plane’s plane inductance Local dependency of Plane Impedance7 © Zuken

8. Power Plane Pairs Concerns• Power plane pairs are used to provide the switching current to the ICs in a higher frequency range where decoupling capacitors cannot work effectively (f>20-50 MHz).• A constant low impedance is required in a wide frequency range between the fundamental clock frequency f0 of the ICs and several 10x harmonics of f0• Resonances cause significantly higher impedances!  If one or more harmonics of f0 coincide with a plane’s resonance frequency, the IC’s function may fail! f0 Local dependency of Plane Impedance8 © Zuken

9. When Integrated Circuits Switch …. TTL Inverter VCC R1 R2 Q1 Q4 Q 3 D1 V(t) Q 2 + - Last R3 GND Input Intern Output • They need charge. 1.8V • Voltage has to be delivered (for reaching logic levels). VH • A switching current will occur! VL GND Relation between voltage & current?  Ohm’s law9 © Zuken

10. Power Integrity in Reality Proper Power Supply of a Large FPGA A Xilinx FPGA with 456 pins: • Controls a video grabber card • 64 bits can switch in parallel (worst case, with a rise time of 750ps) • Output pin drives into a load of 15pf The maximum switching current can be determined by: Vcc 2.5VI  n * C *  64 *15 pf  3.2 A t 0.75ns Based on this maximum current, the impedance limit to guarantee a ripple of less than 125 mV (5% of 2.5 V) : U 125mV Z   0.039 I 3.2 A 10 © Zuken

11. Power Integrity: Switching Current• IC Switching current depends on: - Number of active outputs - Activity state - Driver rise and fall times TTL Inverter VCC - Clock frequencies - Load conditions R1 R2 Q1 Q4 Q 3 D1 V(t) Q 2 + - Last R3 GND Input Intern Output11 © Zuken

12. Example: Ztarget of a Freescale Power-PC Area to be determined by PCB designPicture © Freescale Table © Freescale12 © Zuken

13. PCB Design Process Changing Traditional design flow to address power integrity issues Conceptual Test Schematic Placement Layout Prototyping Design Measurements Design flow with power integrity analysis during layout Concurrent PI Simulation Conceptual Test Schematic Placement Layout Prototyping Design Measurements13 © Zuken

14. Common Management of Power IntegrityDecoupling Capacitors (DeCaps):• Often used on “per default” basis (eg.; each IC)• Values are based on past experience or design guidelines (eg.; 47nF, 100nF,…)• Decision drivers are typically “rules of thumb” or “fear-decouplers”• Connection between ICs and power-planes using discrete components and long traces usually result in: – Parasitic inductances – Parallel connection in series to GND  very high impedance and parallel capacitor circuit – Outcome: ‒ Efficiency is reduced (can be narrowed down to zero) ‒ Low-pass filters with low resonance frequencies (LC-Resonance) ‒ Current loops  EMC antennas Vdd Ground14 © Zuken

15. Parasitic Inductance of DeCapsThe following inductance should be taken into account for PI consideration: • Connecting traces (rule of thumb: ~1nH per mm) • ESL of the DeCap (Package) • Inductance of the PDS (eg,; Vcc/GND) • 2 x Via-Inductance, which can be calculated by hand as follows: With:   4h   LVia  2h ln    1 h = PCB-thickness resp. Via-length  d   and: d = Via-diameter IC Decap Vcc GND15 Source: Johnson & Graham’s : A Handbook of Black Magic © Zuken

16. Real Capacitors Equivalent Circuit C L ESR Capacitor Z Resonance frequency of a capacitor fres  1 / 2 L  C ESR fres1 fres2 log f C=10nF, L= 25nH (including trace)  f res  10 MHz C=10nF, L= 2.5nH (SMD-Pads)  f res  33 MHz16 © Zuken

17. Decoupling Capacitors and Resonances17 © Zuken

18. Decoupling Capacitors: Design RulesDistance of decoupling capacitor to IC pin: - Investigation of the influence of distance d between IC (source) and a decoupling capacitor DeCap d Source18 © Zuken

19. Decoupling Capacitors: Design RulesDistance of DeCaps to IC Pin: Distance d has significant influence on efficiency and resonance behavior, but not in the high frequency range (where DeCaps are not effective at all). Pure Plane d=2mm d=5cm d=10cm d19 © Zuken

20. Decoupling Capacitors: Design Rules• Does more DeCaps result in improved resonance behavior? - Distance = 2cm, up to 4 DeCaps at 10nF Port2 DeCaps Source20 © Zuken

21. Decoupling Capacitors: Design Rules• Variation of the number of the DeCaps – Identical DeCaps with identical connection• Consequence: Number of DeCaps have limited impact in quality and quantity (resonance in frequency point and magnitude) but there is no general rule  more does not always mean better Pure Plane 1 Decap 2 Decaps 3 Decaps 4 Decaps21 © Zuken

22. Application: Decoupling Analysis & What IfDeCap potentially not effective ?Change Value within Lightning from 470p to 100N  Quick What-If22 © Zuken

23. Application: Effectiveness of Decoupling• Impedance distribution at target frequencies show impact of decoupling capacitors• Indicate quality of placement location, value and connection inductance• Placement or connection can be changed on the fly in Lightning for what if capabilities23 © Zuken

24. Application: DDR2 Power SupplySymetrical modules, with different Power/GND connection 35Ohm @550MHz D1 V1 D1 D2 11Ohm @650MHz V1 V2 D2 V2 better24 © Zuken

25. Application: Plate Capacitance of PDS Plate capacitance should be considered for power and ground plane overlaps25 © Zuken

26. Application: Decoupling CapacitorConnection  Inductance Effect• Automotive Motor Control Unit – Changed connection strategy reduces inductance from 16nH to 7.5nH26 © Zuken

27. Application: Changing PWR/GND Shapesto Improve PDN BehaviorMotor Control Unit – Increased PDS shapes and better connection of decoupling capacitors allows reduction in the number of decoupling capacitors by 40%  saving PCB and manufacturing costs.27 © Zuken

28. Power Integrity in Reality:2.5 V PDS Impedance for the Xilinx Spartan3Target impedance: 0.039Ohm (=limit voltage rippleto +/- 5 %) Computation time toget these figures?Minimum at66 MHz – intended,or at least known? Resonances at 33MhZ and 990 MHz  a problem? Is a modification of the decoupling scheme or a shift of these28 resonances needed? © Zuken

29. There are more voltages to supply…12 Layer Design  Task: Optimization of PDS Capacitance between the layer +2.5V + 2.5 V and GND 0.47 nFCapacitance between the layer + 1.2 V and GND 0.48 nF +1.2V Impact of Decaps Impact of Decaps plane area plane area decaps decaps29 © Zuken

30. Results: Different Power Trace Length 28 mm 28 mm 165 mm 28 mm 86 mm 35 mm 35 mm 25 mm 35 mm track plane plane plane track track30 Length 25 mm Length 86 mm Length 165 mm © Zuken

32. SummaryPower integrity analysis early in the design flow can save cost andimprove quality• Early detection of issues in power distribution systems• Verify effectiveness of decoupling capacitors• Confirm quality of voltage and current distribution to avoid voltage drops32 © Zuken