Rhino labs Prese4th ntation At FPGA Camp, Santa Clara, CA


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Presentation by Guy Marom of Rhino Labs at the 4th FPGA Camp in Santa Clara.
More details visit http://www.fpgacentral.com/fpgacamp or http://www.fpgacentral.com

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Rhino labs Prese4th ntation At FPGA Camp, Santa Clara, CA

  1. 1. FPGA System Design Challenges and Solutions Guy MaromApril 6, 2011 www.rhinolabsinc.com 1
  2. 2. Agenda 1. Who are we 2. FPGA system design challenges 3. Proposed Solution 4. Concluding remarksApril 6, 2011 www.rhinolabsinc.com 2
  3. 3. Who we are Rhino Labs is a leading supplier of Integrated Compute Elements (iCE) We are a Silicon Valley based manufacture of highly integrated compute elements Target markets: networking, T&M, medical, industrial Product lines  FPGA based – Today‟s discussion  SoC based (ARM, MIPS64 multi core solutions)April 6, 2011 www.rhinolabsinc.com 3
  4. 4. Who we are Rhino Labs Engages Customers from Block diagrams to Certified FPGA Based Systems FPGA CPU Front C C Side P64H2 HI to PCI SS Bus bridge SS SS (FSB) C Memory C SS MC4 PCI-X Hub H SS Memory Sub-systemsbusses Interface SS Two (2) C C Vid eo I C DDR C C H (Double P64H2 HI to PCI bridge Data Rate) C C Memory Busses Low speed 33MHz PCI bus April 6, 2011 www.rhinolabsinc.com 4
  5. 5. What is iCE: Integrated Compute Element DDR3 (1GB) Platform USB Host/Peripheral flash NOR flash USB / UART QUAD 10/100/1000 Ethernet I2C EPROM V-6 XC6VLX240T 10/100/1000 Ethernet Clock gen unit DVI Video PCIe MGTs GPIOs System ACE Configuration I/F iCE modules integrates CPUs/FPGAs, DDR3, Flash, EPROM, clocks, reset, networking and Standard I/O interfaces in a small packageApril 6, 2011 www.rhinolabsinc.com 5
  6. 6. FPGA System Design Challenges System Design Challenges Today’s FPGAs for today’s FPGAs. Highly integrated …  Signal Integrity for CPU, sram, mem cntl.,  DDR3 ….1067 MHz std IPs & I/Fs such as  High speed serial IOs usb2, PCIe, GE, IOs, …  USB3 ……4.8 Gb/s Huge programmable  4xPCIe v2 …6.4 Gb/s fabrics, complex power  Ethernet ……10 Gb/s paradigm  Cross talk and maintain Allows quick time to clean power distribution market compared with  Maintain required air flow ASICApril 6, 2011 www.rhinolabsinc.com 6
  7. 7. Using Standard FPGA System Design Adds Time and Costs System design HW Design Components selection schematics SW Design SI analysis (pre layout) Logic Design Layout (placement & BSP routing) Application Logic Design Fab and assembly OS porting Design and Fab MFG, bring up and test Logic Design Board Bring up and Application SW verifications development 3-6 months Estimated cost: ~$100KsApril 6, 2011 www.rhinolabsinc.com 7
  8. 8. Example Application #1: T&M using FPGA Designing a standard T&M application card – the “standard” way  Fast FPGA device – V6 or V7  Associated DDR memory  Fast interfaces – PCIe x4/x8  GE or 10GE – for stand alone PWR DDR DDR application GE/10GE  Configuration devices PCIe FPGA  Clocking, Reset, Logic  Software and/or hardware CONFIG integration  OS and applications Expertise required: HW design, Signal integrity , layout, FPGA tools, logic design , power design, thermal & temp analysis, OS/App, HSIO, component sourcing, etc.April 6, 2011 www.rhinolabsinc.com 8
  9. 9. Proposed Solution iCE to save time and costGet a head start:• Use an Off-the-shelf iCE (Integrated Compute Element) device from Rhino Labs• Design a simpler than originally needed carrier card• Focus on logic and SW applications• Be in the market 6-9 months earlierApril 6, 2011 www.rhinolabsinc.com 9
  10. 10. Example Application #2 : Network Security BoxDesign a networksecurity unit• Fast standard networking interfaces SD 1GE/10GE• management ports• Logging capabilities and interfacesApril 6, 2011 www.rhinolabsinc.com 10
  11. 11. Network Security Unit example continuedNetwork security unit • Design and bring up a Firewall unit POW CF/SD • FPGA and or SoC ER based processing unit DDR DDR • Fast networking FPGA/ Flash SoC Quad interfaces (GE/10GE) GE • logging and storing Configuration mgmt Usb 2.0 capabilities reset Clock genApril 6, 2011 www.rhinolabsinc.com 11
  12. 12. The iCE Approach: Network Security UnitNetwork security unit• Drop an iCE unit, POWE CF/SD connect a simplified R power circuitry• Focus on your software application• Move to production in a simplified operation April 6, 2011 www.rhinolabsinc.com 12
  13. 13. FPGA System Design: Approach that Saves time and costs System design HW Design Components selection Complete schematics SI analysis (pre layout) SW Design Logic Design Layout (placement & BSP routing) Application Logic Design Fab and assembly OS porting Design and Fab MFG, bring up and test Board Bring up and Logic Design Application SW verifications development 80% of work Significantly reduce is done  costs and risk.April 6, 2011 www.rhinolabsinc.com 13
  14. 14. Recommendations for today‟s FPGA Systems Design Using off-the-shelf „Integrated Compute Element‟ hardware lets the customer focus on logic design and application software Establish your manufacturing partner ideally before design start Get a partner on board who has extensive experience in delivering standard modules, custom subsystems, and certified productsApril 6, 2011 www.rhinolabsinc.com 14
  15. 15. Concluding Remarks Today‟s FPGAs are creating challenges and opportunities for FPGA designers iCEs can be used as building blocks to save time and costs iCE will help you focus more on logic design and sw application Thanks April 6, 2011 www.rhinolabsinc.com 15