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Differentiable Neural Computer

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Hybrid computing using a neural network with dynamic external memory

http://www.nature.com/nature/journal/v538/n7626/full/nature20101.html

Published in: Technology
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Differentiable Neural Computer

  1. 1. Differentiable Neural Computer Taehoon Kim 2016-10-27
  2. 2. V : vector H : header
  3. 3. DNC architecture
  4. 4. DNC architecture CPU RAM
  5. 5. 3 types of Attention 1. Content lookup (뭐랑 비슷한가) • 데이터 사이에 연관성(유사도)을 고려 2. Temporal links (누구랑 친한가) • 인풋의 정보를 읽고 연속적인 데이터를 가져옴 3. Allocation (어디다 넣을 것인가) • Write header에게 빈 공간을 알려줌
  6. 6. 메모리 𝑀 • 미분 가능한 어텐션을 주소를 찾는데 사용 • 주소라기 보단 distribution이라고 이해하는게 좋음 • 컴퓨터는 discrete한 메모리 주소를 사용 • Weightings = 주소 • 𝑀은 𝑁×𝑊 크키의 행렬
  7. 7. 읽기와 쓰기 • 𝒘 (weighting) : 어떤 장소가 얼마나 수정이 되는지 • 읽기 : 𝒓 = ∑ 𝑀 𝑖,+ 𝒘 𝒓 [𝑖]. /01 , (‘+’는 𝑗 = 1, … , 𝑊 모두를 의미) • 𝒓 (read vector) : 각 메모리에 weighting을 곱하고 더하면 • 𝒘 𝒓 (read weighting) • 쓰기 : 𝑀 𝑖, 𝑗 ← 𝑀 𝑖, 𝑗 1 − 𝒘7 𝑖 𝑒 𝑗 + 𝒘7 𝑖 𝑣[𝑗]
  8. 8. Method
  9. 9. 1. Controller Network 𝒩
  10. 10. 매 시간 𝑡마다 1. Input V 𝑥> ∈ ℝA 를 데이터 혹은 환경으로부터 받음 2. Output V 𝑦> ∈ ℝC 를 벹어 target V 𝑧> ∈ ℝC 를 계산 • SL일 경우 𝑧> = predictive distribution • RL일 경우 𝑧> = action distribution
  11. 11. 매 시간 𝑡마다 3. 메모리 𝑀>E1 ∈ ℝ.×F 에서 Read H를 사용해서 • R개의 read V 𝑟>E1 1 , … , 𝑟>E1 H 를 읽음 4. 메모리 𝑀>E1과의 상호작용을 정하는 interface V 𝜉>를 계산 • 𝒳> = [𝑥>; 𝑟>E1 1 ; … ; 𝑟>E1 H ] • 편의를 위해 read, input V를 붙여 하나의 controller input V를 정 의
  12. 12. 네트워크 • 모든 뉴럴 네트워크를 𝒩로 사용할 수 있음 • 논문에서는 LSTM를 약간 바꾼 네트워크를 사용
  13. 13. LSTM
  14. 14. LSTM • 𝒊 𝒕 𝒍 = 𝜎 𝑊/ P 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏/ P • 𝒇 𝒕 𝒍 = 𝜎 𝑊U P 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏U P • 𝒐 𝒕 𝒍 = 𝜎 𝑊U P 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏W P • 𝑪 𝒕 𝒍 = 𝒊 𝒕 𝒍 ∗ tanh 𝑊^ P 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏^ P + 𝒇 𝒕 𝒍 ∗ 𝑪 𝒕E𝟏 𝒍 • 𝒉 𝒕 𝒍 = 𝒐 𝒕 𝒍 ∗ tanh 𝑪 𝒕 𝒍
  15. 15. LSTM • 𝒊 𝒕 𝒍 = 𝜎 𝑊/ P 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏/ P • 𝒇 𝒕 𝒍 = 𝜎 𝑊U P 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏U P • 𝒐 𝒕 𝒍 = 𝜎 𝑊U P 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏W P • 𝑪 𝒕 𝒍 = 𝒊 𝒕 𝒍 ∗ tanh 𝑊^ P 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏^ P + 𝒇 𝒕 𝒍 ∗ 𝑪 𝒕E𝟏 𝒍 • 𝒉 𝒕 𝒍 = 𝒐 𝒕 𝒍 ∗ tanh 𝑪 𝒕 𝒍 Cell state는 정보를 빼거나 추가할 때 사용된다 Input gate Forget gate Output gate
  16. 16. • 𝒊 𝒕 𝒍 = 𝜎 𝑊/ P 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏/ P • 𝒇 𝒕 𝒍 = 𝜎 𝑊U P 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏U P • 𝒐 𝒕 𝒍 = 𝜎 𝑊U P 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏W P • 𝑪 𝒕 𝒍 = 𝒊 𝒕 𝒍 ∗ tanh 𝑊^ P 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏^ P + 𝒇 𝒕 𝒍 ∗ 𝑪 𝒕E𝟏 𝒍 • 𝒉 𝒕 𝒍 = 𝒐 𝒕 𝒍 ∗ tanh 𝑪 𝒕 𝒍 𝑪 𝟎 𝟎 𝒙 𝟏 = 𝒉 𝟏 E𝟏 𝒉 𝟎 𝟎 𝒐 𝟏 𝟎 𝒇 𝟏 𝟎 𝒊 𝟏 𝟎 𝒈 𝟏 𝟎 𝑪 𝟏 𝟎 𝒉 𝟏 𝟎 𝑪 𝟏 𝟏 𝒉 𝟏 𝟏 𝑪 𝟎 𝟏 𝒉 𝟎 𝟏 𝒐 𝟏 𝟏 𝒇 𝟏 𝟏 𝒊 𝟏 𝟏 𝒈 𝟏 𝟏
  17. 17. Controller Network 𝒩 𝓧 𝒕 𝓋𝒕, 𝝃 𝒕
  18. 18. Controller Network 𝒩 • 𝒊 𝒕 𝒍 = 𝜎 𝑊/ P 𝓧 𝒕; 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏/ P • 𝒇 𝒕 𝒍 = 𝜎 𝑊U P 𝓧 𝒕; 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏U P • 𝒐 𝒕 𝒍 = 𝜎 𝑊W P 𝓧 𝒕; 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏W P • 𝒔 𝒕 𝒍 = 𝑖> P ∗ tanh 𝑊^ P 𝓧 𝒕; 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏^ P + 𝑓> P ∗ 𝒔 𝒕E𝟏 𝒍 • 𝒉 𝒕 𝒍 = 𝑜> P ∗ tanh 𝒔 𝒕 𝒍 𝓧 𝒕 𝒉 𝒕 𝒍E𝟏 𝒉 𝒕E𝟏 𝒍
  19. 19. 𝒔 𝟎 𝟏 𝒉 𝟏 𝟎𝒙 𝟏 𝒉 𝟎 𝟏 𝒐 𝟏 𝟏 𝒇 𝟏 𝟏 𝒊 𝟏 𝟏 𝒈 𝟏 𝟏 𝒔 𝟏 𝟏 𝒉 𝟏 𝟏 𝒔 𝟏 𝟐 𝒉 𝟏 𝟐 𝒔 𝟎 𝟐 𝒉 𝟎 𝟐 𝒐 𝟏 𝟐 𝒇 𝟏 𝟐 𝒊 𝟏 𝟐 𝒈 𝟏 𝟐 𝑴 𝟎 • 𝒊 𝒕 𝒍 = 𝜎 𝑊/ P 𝓧 𝒕; 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏/ P • 𝒇 𝒕 𝒍 = 𝜎 𝑊U P 𝓧 𝒕; 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏U P • 𝒐 𝒕 𝒍 = 𝜎 𝑊W P 𝓧 𝒕; 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏W P • 𝒔 𝒕 𝒍 = 𝑖> P ∗ tanh 𝑊^ P 𝓧 𝒕; 𝒉 𝒕E𝟏 𝒍 ; 𝒉 𝒕 𝒍E𝟏 + 𝑏^ P + 𝑓> P ∗ 𝒔 𝒕E𝟏 𝒍 • 𝒉 𝒕 𝒍 = 𝑜> P ∗ tanh 𝒔 𝒕 𝒍 … ℎ> k = 0 …ℎk P = 0 𝒳1
  20. 20. 𝒔 𝟎 𝟏 𝒉 𝟏 𝟎𝒙 𝟏 𝒉 𝟎 𝟏 𝒐 𝟏 𝟏 𝒇 𝟏 𝟏 𝒊 𝟏 𝟏 𝒈 𝟏 𝟏 𝒔 𝟏 𝟏 𝒉 𝟏 𝟏 𝒔 𝟏 𝟐 𝒉 𝟏 𝟐 𝒔 𝟎 𝟐 𝒉 𝟎 𝟐 𝒐 𝟏 𝟐 𝒇 𝟏 𝟐 𝒊 𝟏 𝟐 𝒈 𝟏 𝟐 𝑴 𝟎 𝑪 𝟎 𝟎 𝒉 𝟎 𝟎 𝒐 𝟏 𝟎 𝒇 𝟏 𝟎 𝒊 𝟏 𝟎 𝒈 𝟏 𝟎 𝑪 𝟏 𝟎 𝒉 𝟏 𝟎 𝑪 𝟏 𝟏 𝒉 𝟏 𝟏 𝑪 𝟎 𝟏 𝒉 𝟎 𝟏 𝒐 𝟏 𝟏 𝒇 𝟏 𝟏 𝒊 𝟏 𝟏 𝒈 𝟏 𝟏 𝒙 𝟏 = 𝒉 𝟏 E𝟏 𝒳1
  21. 21. Controller Network 𝒩 • 모든 𝒕에 대해서 𝒉 𝒕 𝟎 = 𝟎 • 모든 𝒕에 대해서 𝒉 𝟎 𝒍 = 𝟎 • 매 시간 controller는 두개의 값을 벹어냄 • Output V 𝓋> = 𝑊m ℎ> 1 ; … ; ℎ> n • Interface V 𝜉> ∈ ℝ F×o pqFprHpq = 𝑊s ℎ> 1 ; … ; ℎ> n 𝝃 𝒕 𝒗 𝒕
  22. 22. 𝒔 𝟎 𝟏 𝒉 𝟏 𝟎𝒙 𝟏 𝒉 𝟎 𝟏 𝒐 𝟏 𝟏 𝒇 𝟏 𝟏 𝒊 𝟏 𝟏 𝒈 𝟏 𝟏 𝒔 𝟏 𝟏 𝒉 𝟏 𝟐 𝒔 𝟎 𝟐 𝒉 𝟎 𝟐 𝒐 𝟏 𝟐 𝒇 𝟏 𝟐 𝒊 𝟏 𝟐 𝒈 𝟏 𝟐 𝑴 𝟎 𝒉 𝟐 𝟎𝒙 𝟐 𝒉 𝟏 𝟏 𝒐 𝟐 𝟏 𝒇 𝟐 𝟏 𝒊 𝟐 𝟏 𝒈 𝟐 𝟏 𝒔 𝟐 𝟏 𝒉 𝟐 𝟏 𝒔 𝟐 𝟐 𝒉 𝟐 𝟐 𝒔 𝟏 𝟐 𝒐 𝟐 𝟐 𝒇 𝟐 𝟐 𝒊 𝟐 𝟐 𝒈 𝟐 𝟐 𝑴 𝟏 𝓋 𝟏 𝜉 𝟏 𝓋 𝟐 𝜉 𝟐 𝒚 𝟏 𝒚 𝟐 𝑴 𝟐
  23. 23. Controller Network 𝒩 • (𝓋>, 𝜉>) = 𝒩 𝒳1; … ; 𝒳> ; 𝜃 • 𝒳> = [𝑥>; 𝑟>E1 1 ; … ; 𝑟>E1 H ] • 만약 recurrent가 아니라 feedforward였다면, • (𝓋>, 𝜉>) = 𝒩 𝒳>; 𝜃 • 𝑦> = 𝓋> + 𝑊x 𝒓𝒕 𝟏 ; … ; 𝒓𝒕 𝑹 , 𝑊x ∈ ℝC×HF • 𝒓𝒕 𝟏 ; … ; 𝒓𝒕 𝑹 를 추가해 방금 읽은 메모리를 보고 결과를 만들도록 함
  24. 24. Interface parameters • Interface V 𝜉>는 메모리 상호작용을 결정하는 파라미터들로 구성됨 • 각 파라미터는 함수들에 의해 가질 수 있는 값의 범위가 조절됨 • logistic sigmoid function : [0,1] 사이의 값 • ‘Oneplus’ function : 1, ∞ 사이의 값 • 𝑜𝑛𝑒𝑝𝑙𝑢𝑠 𝑥 = 1 + 𝑙𝑜𝑔(1 + 𝑒ƒ )
  25. 25. Interface parameters • 𝑅개의 read key 𝑘> x,/ ∈ ℝF; 1 ≤ 𝑖 ≤ 𝑅 • 𝑅개의 read strength {𝛽> x,/ = 𝑜𝑛𝑒𝑝𝑙𝑢𝑠(𝛽> x,/ ) ∈ [1, ∞); 1 ≤ 𝑖 ≤ 𝑅} • write key 𝑘> 7 ∈ ℝ7 • wright strength 𝛽> 7 = 𝑜𝑛𝑒𝑝𝑙𝑢𝑠 𝛽> 7 ∈ [1, ∞) • 𝑅개의 free gates {𝑓> / = 𝜎 𝑓> / ∈ [0,1]; 1 ≤ 𝑖 ≤ 𝑅}
  26. 26. Interface parameters • 𝑅개의 free gates {𝑓> / = 𝜎 𝑓> / ∈ [0,1]; 1 ≤ 𝑖 ≤ 𝑅} • allocation gate 𝑔> Š = 𝜎 𝑔> Š ∈ [0,1] • write gate 𝑔> 7 = 𝜎 𝑔> 7 ∈ [0,1] • 𝑅개의 read modes {𝜋> / = 𝑠𝑜𝑓𝑡𝑚𝑎𝑥 𝜋> / ∈ 𝒮q; 1 ≤ 𝑖 ≤ 𝑅}
  27. 27. 메모리 읽고 쓰기 • 얼마나 읽고 쓸지는 weightings에 의해 결정 • 각 벡터들은 양수이며, 모든 값의 합은 최대 1 • ∆.= 𝛼 ∈ ℝ. : 𝛼/ ∈ 0,1 , ∑ 𝛼/ . /01 ≤ 1 • 읽기: 𝑅개의 read weightings 𝑤> x,1 , … , 𝑤> x,H ∈ ∆. 이 사용 • 𝑟> / = 𝑀> “ 𝑤> x,/ ∈ ℝF • 읽어진 read vector들은 다음 time-step에 입력으로 사용
  28. 28. 메모리 읽고 쓰기 • 쓰기 : 𝑀> = 𝑀>E1 ∘ 𝐸 − 𝒘 𝒕 𝒘 𝒆 𝒕 “ + 𝒘 𝒕 𝒘 𝒗 𝒕 “ • 하나의 write weighting 𝑤> 7 ∈ Δ. • Erase V 𝑒> ∈ 0,1 F , Write V 𝑣> ∈ ℝF • ∘는 element-wise multiplication을 의미 • 𝐸 ∈ ℝ.×F 는 1만으로 구성된 행렬
  29. 29. 메모리 addressing • 쓰기 • Content-based addressing + dynamic memory allocation • 읽기 • Content-based addressing + temporal memory linkage
  30. 30. Content-based addressing 𝒞 𝑀, 𝒌, 𝛽 𝑖 = exp 𝒟 𝒌, 𝑀[𝑖,+] 𝛽 ∑ exp 𝒟 𝒌, 𝑀[𝑗,+] 𝛽Ÿ • Lookup key : 𝒌 ∈ ℝF • Key strength: 𝛽 ∈ 1, ∞ • 𝒟 𝑢, 𝑣 = +¡ ¡ (cosine similarity)
  31. 31. Content-based addressing • Weighting 𝒞 𝑀, 𝒌, 𝛽 ∈ 𝒮¢은 메모리 위치에 대한 normalized된 확률 분포 • normalized : 벡터 값들의 합이 1 • Read H, write H 모두에 사용됨
  32. 32. Dynamic memory allocation • Controller가 메모리를 필요한 만큼 할당하고 free하기 위해 • 사용 가능한 메모리 주소들을 free list라는 리스트에 저장 • 𝒖> ∈ 0,1 . : memory usage vector • 𝒖k = 𝟎 • 메모리에 쓰기 전에 controller는 각각의 read head마다 하나씩 free gate 𝑓> / 들을 벹고 읽어진 메모리들이 free될지 안될지를 결정
  33. 33. Dynamic memory allocation • 𝜓> ∈ 0,1 . 는 한 메모리가 얼마나 free 되지 않을지를 나타냄 • 𝜓> = ∏ 𝟏 − 𝑓> / 𝑤>E1 x,/H /01 • Usage vector 𝒖> = 𝒖>E1 + 𝑤>E1 7 − 𝒖>E1 ∘ 𝑤>E1 7 ∘ 𝜓> • 𝒖> = 𝒖>E1 ∘ 1 − 𝑤>E1 7 + 𝑤>E1 7 ∘ 𝜓> • 사용되었다 = 사용 중이다 (높은 𝒖) or 방금전에 쓰여졌다 (낮은 𝒖) • 𝜓> 𝑖 ≈ 1, free gate에 의해 유지된다는 의미 • 모든 write는 usage를 증가시킨다 • 메모리는 오직 free gate 𝑓> / 에 의해 비워질 수 있다
  34. 34. Dynamic memory allocation • 𝑢>가 정해지고 나면 free list 𝜙> ∈ ℤ. 가 정해진다 • 𝜙>: 메모리 index를 usage가 증가하는 방향으로 정렬 • 𝜙>[1]은 가장 적게 사용된 index • Allocation weighting 𝒂𝒕 ∈ Δ.는 새로 쓸 index를 계산 • 만약 𝒖 𝒕 = 𝟏라면 𝒂> = 𝟎 𝒂𝒕 𝜙> 𝑗 = 1 − 𝒖𝒕 𝜙> 𝑗 ª 𝒖𝒕 𝜙> 𝑖 ŸE1 /01
  35. 35. Write weighting • Controller는 새로운 메모리 혹은 content에 의해 결정된 위 치에 쓸 수 있고, 아얘 쓰지 않겠다고 결정할 수 있음 • Write content weighting 𝒄𝒕 𝒘 ∈ 𝒮. • 𝒄𝒕 𝒘 = 𝒞 𝑀>E1, 𝒌𝒕 𝒘 , 𝛽> 7
  36. 36. Write weighting • Write weighting 𝑤> 7 ∈ Δ. • 𝒘 𝒕 𝒘 = 𝑔> 7 𝑔> Š 𝒂𝒕 + 1 − 𝑔> Š 𝒄𝒕 𝒘 • 𝑔> 7 ∈ [0,1] : write gate. 0일 경우 아무것도 쓰지 않음 • 𝑔> Š ∈ 0,1 : allocation gate • 어디에 쓸 것인가, 새로운 곳? 혹은 Context로 찾은곳?
  37. 37. Temporal memory linkage • Memory allocation은 어떤 순서로 메모리가 써졌는지 모른다 • 하지만 순서를 기억해 둬야할 상황이 있다 • Temporal link matrix 𝐿> ∈ 0,1 .×. • 𝐿>[𝑖, 𝑗]는 주소 j 이후에 i에 얼마나 쓰여졌는가를 나타냄 • 𝐿> 𝑖,+ ∈ Δ., 𝐿> +, 𝑗 ∈ Δ.
  38. 38. Temporal memory linkage • 𝐿>를 정의하기 위해서 𝒑> ∈ Δ.가 필요 • 각 𝒑>[𝑖]는 어느 i가 마지막으로 쓰여졌는가의 정도를 나타냄 • 𝒑k = 0 • 𝒑> = 1 − ∑ 𝒘> 7 𝑖/ 𝒑>E1 + 𝐰¯ ° • 𝑳> 𝑖, 𝑗 = 1 − 𝑤> 7 𝑖 − 𝑤> 7 𝑗 𝐿>E1 𝑖, 𝑗 + 𝑤> 7 𝑖 𝑝>E1 𝑗 • 𝑳> 𝑖, 𝑗 = 0 ∀𝑖, 𝑗 • 𝑳> 𝑖, 𝑗 = 0 ∀𝑖 • 𝑳> 𝑖, 𝑖 = 0 ∀𝑖: 자기 자신으로의 링크는 무시됨 (계산하기 어려움)
  39. 39. Temporal memory linkage • 𝐿>를 정의하기 위해서 𝒑> ∈ Δ.가 필요 • 각 𝒑>[𝑖]는 어느 i가 마지막으로 쓰여졌는가의 정도를 나타냄 • 𝒑k = 0 • 𝒑> = 1 − ∑ 𝒘> 7 𝑖/ 𝒑>E1 + 𝐰¯ ° • 𝑳> 𝑖, 𝑗 = 1 − 𝑤> 7 𝑖 − 𝑤> 7 𝑗 𝐿>E1 𝑖, 𝑗 + 𝑤> 7 𝑖 𝑝>E1 𝑗 • 𝑳> 𝑖, 𝑗 = 0 ∀𝑖, 𝑗 • 𝑳> 𝑖, 𝑗 = 0 ∀𝑖 • 𝑳> 𝑖, 𝑖 = 0 ∀𝑖: 자기 자신으로의 링크는 무시됨 (계산하기 어려움)
  40. 40. Temporal memory linkage • 𝐿> : 특정 메모리에서 이전 or 이후에 얼마나 읽었는지의 정도 • Backward weighting 𝑏> / ∈ Δ. = 𝐿> “ 𝑤>E1 x,/ • Forward weighting 𝑓> / ∈ Δ. = 𝐿> 𝑤>E1 x,/
  41. 41. Sparse link matrix

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