SlideShare a Scribd company logo

UDSM and BiCMOS Technologies Lecture

•
•
A
aicdesign
1 of 15
Download to read offline
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-1 LECTURE 040 - ULTRA-DEEP SUBMICRON AND BiCMOS TECHNOLOGIES LECTURE ORGANIZATION Outline • Ultra-deep submicron CMOS technology - Features - Advantages - Problems • BiCMOS technology process flow - CMOS is typical submicron (0.5 μm) • Summary CMOS Analog Circuit Design, 2nd Edition Reference New material CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-2 ULTRA-DEEP SUBMICRON (UDSM) CMOS TECHNOLOGY USDM Technology • Lmin 0.1 microns • Minimum feature size less than 100 nanometers • Today’s state of the art: - 65 nm drawn length - 15 nm lateral diffusion (35 nm gate length) - 1.2 nm transistor gate oxide - 8 layers of copper interconnect • Specialized processing is used to increase drive capability and maintain low off currents CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-3 65 Nanometer CMOS Technology TEM cross-section of a 35 nm NMOS and PMOS transistors.† NMOS: PMOS: NMOS 220 nm pitch These transistors utilize enhanced channel strains to increase drive capability and to reduce off currents. † P. Bai, et. Al., “A 65nm Lobic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57 μm2 SRAM Cell, IEEE Inter. Electron Device Meeting, Dec. 12-15, 2005. CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-4 UDSM Metal and Interconnects Physical aspects: Layer Pitch (nm) Thickness (nm) Aspect Ratio Isolation 220 230 - Polysilicon 220 90 - Contacted Gate Pitch 220 - - Metal 1 210 170 1.6 Metal 2 210 190 1.8 Metal 3 220 200 1.8 Metal 4 280 250 1.8 Metal 5 330 300 1.8 Metal 6 480 430 1.8 Metal 7 720 650 1.8 Metal 8 1080 975 1.8 CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-5 What are the Advantages of UDSM CMOS Technology? Digital Viewpoint: • Improved Ion/Ioff 70 Mbit SRAM chip: • Reduced gate capacitance • Higher drive current capability • Reduced interconnect density • Reduction of active power Analog Viewpoint: • More levels of metal • Higher fT • Higher capacitance density • Reduced junction capacitance per gm CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-6 What are the Disadvantages of UDSM CMOS Technology (for Analog)? • Reduction in power supply resulting in reduced headroom • Gate leakage currents • Reduced small-signal intrinsic gains • Increased nonlinearity (IIP3) • Noise and matching?? Intrinsic gain and IP3 as a function of the gate overdrive for decreasing VDS:† † Anne-Johan Annema, et. Al., “Analog Circuits in Ultra-Deep-Submicron CMOS,” IEEE J. of Solid-State Circuits, Vol. 40, No. 1, Jan. 2005, pp. 132- 143. CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-7 What is the Gate Leakage Problem? Gate current occurs in thin oxide devices due to direct tunneling through the thin oxide. Gate current depends on: 1.) The gate-source voltage (and the drain-gate voltage) iGS = K1vGS exp(K2vGS) and iGD = K3vGD exp(K4vGD) 2.) Gate area – NMOS leakage 6nA/μm2 and PMOS leakage 3nA/μm2 Unfortunately, the gate leakage current is nonlinear with respect to the gate-source and gate-drain voltages. A possible model is: f(vGD) f(vGS) 051205-03 − vGD + + f(vSG) vGS f(vDG) − + vSG − − vDG + NMOS PMOS Large Signal Models ggd ggs NMOS gsg gdg PMOS Small Signal Models Base current cancellation schemes used for BJTs are difficult to apply to the MOSFET. CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-8 Gate Leakage and fgate The gate leakage can be represented by a conductance, ggate, in parallel with the gate capacitance, Cgate. Since these two elements have identical area dependence, they result in a frequency, fgate, that is fairly independent of the drain-source voltage, vds. fgate = ggate 2Cgate 1.5·1016vGS 2etox(vGS-13.6)(NMOS) 0.5·1016vGS 2etox(vGS-13.6)(PMOS) where tox is in nm and vGS is in V. For frequencies above fgate the MOSFET looks capacitive and below fgate, the MOSFET looks resistive (gate leakage). CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-9 UDSM CMOS Technology Summary • Increased transconductance and frequency capability • Low power supply voltages • Reduced parasitics • Gate leakage causes challenges for analog applications of UDSM technology - Can no longer use the MOSFET for capacitance - Conflict between matching and gate leakage • Other issues - Noise - Zero temperature coefficient behavior - Etc. CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-10 BiCMOS TECHNOLOGY Typical 0.5μm BiCMOS Technology Masking Sequence: 1. Buried n+ layer 9. Base oxide/implant 17. Contacts 2. Buried p+ layer 10. Emitter implant 18. Metal 1 3. Collector tub 11. Poly 1 19. Via 1 4. Active area 12. NMOS lightly doped drain 20. Metal 2 5. Collector sinker 13. PMOS lightly doped drain 21. Via 2 6. n-well 14. n+ source/drain 22. Metal 3 7. p-well 15. p+ source/drain 23. Nitride passivation 8. Emitter window 16. Silicide protection Notation used in the following slides: BSPG = Boron and Phosphorus doped Silicate Glass (oxide) Kooi Nitride = A thin layer of silicon nitride on the silicon surface as a result of the reaction of silicon with the HN3 generated, during the field oxidation. TEOS = Tetro-Ethyl-Ortho-Silicate. A chemical compound used to deposit conformal oxide films. CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-11 n+ and p+ Buried Layers Starting Substrate: p-substrate 1μm BiCMOS-01 5μm n+ and p+ Buried Layers: NPN Transistor PMOS Transistor NMOS Transistor n+ buried layer p+ buried layer p-substrate n+ buried layer p+ buried layer 1μm 5μm BiCMOS-02 CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-12 Epitaxial Growth NPN Transistor PMOS Transistor NMOS Transistor p-well n-well p-well n+ buried layer p-substrate n-well n+ buried layer p+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-03 Comment: • As the epi layer grows vertically, it assumes the doping level of the substrate beneath it. • In addition, the high temperature of the epitaxial process causes the buried layers to diffuse upward and downward. CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-13 Collector Tub NPN Transistor PMOS Transistor NMOS Transistor n-well p-well n+ buried layer p+ buried layer p-substrate p-well Original Area of CollectorTub Implant Collector Tub n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-04 Comment: • The collector area is developed by an initial implant followed by a drive-in diffusion to form the collector tub. CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-14 Active Area Definition NPN Transistor PMOS Transistor NMOS Transistor n-well p-well n+ buried layer p+ buried layer p-substrate p-well Collector Tub n+ buried layer p+ buried layer Nitride α-Silicon p-type Epitaxial Silicon 1μm 5μm BiCMOS-05 Comment: • The silicon nitride is use to impede the growth of the thick oxide which allows contact to the substrate • -silicon is used for stress relief and to minimize the bird’s beak encroachment CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-15 Field Oxide NPN Transistor PMOS Transistor NMOS Transistor FOX Field Oxide Field Oxide Field Oxide n-well p-well n+ buried layer p+ buried layer p-substrate FOX p-well Collector Tub n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-06 Comments: • The field oxide is used to isolate surface structures (i.e. metal) from the substrate CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-16 Collector Sink and n-Well and p-Well Definitions NPN Transistor PMOS Transistor NMOS Transistor Threshold Adjust Anti-Punch Through FOX Field Oxide Field Oxide Collector Sink Anti-Punch Through Field Oxide Threshold Adjust n-well p-well p-well n+ buried layer p+ buried layer p-substrate Collector Tub FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-07 CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-17 Base Definition NPN Transistor PMOS Transistor NMOS Transistor FOX Field Oxide Field Oxide Field Oxide n-well p-well p-well n+ buried layer p+ buried layer p-substrate FOX Collector Tub n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-08 CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-18 Definition of the Emitter Window and Sub-Collector Implant NPN Transistor PMOS Transistor NMOS Transistor FOX Field Oxide Field Oxide n-well Field Oxide p-well p-well n+ buried layer p+ buried layer p-substrate FOX Sacrifical Oxide Sub-Collector n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-09 CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-19 Emitter Implant PMOS Transistor NMOS Transistor FOX Field Oxide Field Oxide n-well Field Oxide p-well p-well n+ buried layer p+ buried layer p-substrate NPN Transistor Emitter Implant Collector Tub FOX Sub-Collector n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-10 Comments: • The polysilicon above the base is implanted with n-type carriers CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-20 Emitter Diffusion NPN Transistor PMOS Transistor NMOS Transistor FOX Field Oxide Field Oxide n-well Field Oxide p-well p-well n+ buried layer p+ buried layer p-substrate FOX Emitter n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-11 Comments: • The polysilicon not over the emitter window is removed and the n-type carriers diffuse toward the base forming the emitter CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-21 Formation of the MOS Gates and LD Drains/Sources NPN Transistor PMOS Transistor NMOS Transistor FOX Field Oxide Field Oxide Field Oxide n-well p-well p-well n+ buried layer p+ buried layer p-substrate FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-12 Comments: • The surface of the region where the MOSFETs are to be built is cleared and a thin gate oxide is deposited with a polysilicon layer on top of the thin oxide • The polysilicon is removed over the source and drain areas • A light source/drain diffusion is done for the NMOS and PMOS (separately) CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-22 Heavily Doped Source/Drain NPN Transistor PMOS Transistor NMOS Transistor FOX Field Oxide Field Oxide Field Oxide n-well p-well p-well n+ buried layer p+ buried layer p-substrate FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-13 Comments: • The sidewall spacers prevent the heavy source/drain doping from being near the channel of the MOSFET CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-23 Siliciding NPN Transistor PMOS Transistor NMOS Transistor Silicide TiSi2 Silicide TiSi2 Silicide TiSi2 FOX Field Oxide Field Oxide n-well Field Oxide p-well p-well n+ buried layer p+ buried layer p-substrate FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-14 Comments: • Siliciding is used to reduce the resistance of the polysilicon and to provide ohmic contacts to the base, emitter, collector, sources and drains CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-24 Contacts Tungsten Plugs Tungsten Plugs Tungsten Plugs TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG Field Oxide Field Oxide Field Field Oxide Oxide n-well p-well p-well n+ buried layer p+ buried layer p-substrate FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm FOX BiCMOS-15 5μm Comments: • A dielectric is deposited over the entire wafer • One of the purposes of the dielectric is to smooth out the surface • Tungsten plugs are used to make electrical contact between the transistors and metal1 CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-25 Metal1 Metal1 Metal1 Metal1 TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG Field Oxide Field Oxide Field Field Oxide Oxide n-well p-well p-well n+ buried layer p+ buried layer p-substrate FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm FOX BiCMOS-16 5μm CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-26 Metal1-Metal2 Vias Tungsten Plugs Oxide/ SOG/ Oxide TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG Field Oxide Field Oxide Field Field Oxide Oxide n-well p-well p-well n+ buried layer p+ buried layer p-substrate FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm FOX BiCMOS-17 5μm CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-27 Metal2 Metal 2 Oxide/ SOG/ Oxide TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG Field Oxide Field Oxide Field Field Oxide Oxide n-well p-well p-well n+ buried layer p+ buried layer p-substrate FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm FOX BiCMOS-18 5μm CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-28 Metal2-Metal3 Vias TEOS/ BPSG/ SOG Oxide/ SOG/ Oxide TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG Field Oxide Field Oxide Field Field Oxide Oxide n-well p-well p-well n+ buried layer p+ buried layer p-substrate FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm FOX BiCMOS-19 5μm Comments: • The metal2-metal3 vias will be filled with metal3 as opposed to tungsten plugs CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-29 Completed Wafer Nitride (Hermetically seals the wafer) Metal3 TEOS/ BPSG/ SOG Oxide/ SOG/ Oxide Oxide/SOG/Oxide Metal3 Vias TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG Field Oxide Field Oxide Field Field Oxide Oxide n-well p-well p-well n+ buried layer p+ buried layer p-substrate FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm FOX BiCMOS-20 5μm CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-30 SUMMARY • UDSM technology typically has a minimum channel length less than 0.1μm • UDSM transistors utilize enhanced channel strains to increase drive capability and reduce off currents • Advantages of UDSM technology include: - Smaller devices - Higher speeds and transconductances - Improved Ion/Ioff • Disadvantages of UDSM technology include: - Gate leakage currents - Reduced small signal gains - Increased nonlinearity • BiCMOS technology - Offers both CMOS transistors and a high performance vertical BJT - CMOS is typically a generation behind - Silicon germanium can be used to enhance the BJT performance CMOS Analog Circuit Design © P.E. Allen - 2010

Recommended

S3 s short course intro soi apps (1)
S3 s short course intro soi apps (1)S3 s short course intro soi apps (1)
S3 s short course intro soi apps (1)cddsoitec
 
CMOS SOI Technology
CMOS SOI TechnologyCMOS SOI Technology
CMOS SOI Technologymehdisimoussa
 
SOI
SOISOI
SOIKASHISH GROVER
 
Ultra-thin body SOI MOSFETs: Term Paper_class presentation on Advanced topics...
Ultra-thin body SOI MOSFETs: Term Paper_class presentation on Advanced topics...Ultra-thin body SOI MOSFETs: Term Paper_class presentation on Advanced topics...
Ultra-thin body SOI MOSFETs: Term Paper_class presentation on Advanced topics...prajon
 
Fin Fet Technology by SAMRA
Fin Fet Technology by SAMRAFin Fet Technology by SAMRA
Fin Fet Technology by SAMRABal Partap Singh
 
Ultra Thin Body SOI FETs
Ultra Thin Body SOI FETsUltra Thin Body SOI FETs
Ultra Thin Body SOI FETssindhu reddy
 
Soi aalam
Soi aalamSoi aalam
Soi aalamaalamkhan
 
Silicon on Insulator (SOI) Technology
Silicon on Insulator (SOI) TechnologySilicon on Insulator (SOI) Technology
Silicon on Insulator (SOI) TechnologySudhanshu Janwadkar
 

Recommended

S3 s short course intro soi apps (1)
S3 s short course intro soi apps (1)S3 s short course intro soi apps (1)
S3 s short course intro soi apps (1)cddsoitec
 
CMOS SOI Technology
CMOS SOI TechnologyCMOS SOI Technology
CMOS SOI Technologymehdisimoussa
 
SOI
SOISOI
SOIKASHISH GROVER
 
Ultra-thin body SOI MOSFETs: Term Paper_class presentation on Advanced topics...
Ultra-thin body SOI MOSFETs: Term Paper_class presentation on Advanced topics...Ultra-thin body SOI MOSFETs: Term Paper_class presentation on Advanced topics...
Ultra-thin body SOI MOSFETs: Term Paper_class presentation on Advanced topics...prajon
 
Fin Fet Technology by SAMRA
Fin Fet Technology by SAMRAFin Fet Technology by SAMRA
Fin Fet Technology by SAMRABal Partap Singh
 
Ultra Thin Body SOI FETs
Ultra Thin Body SOI FETsUltra Thin Body SOI FETs
Ultra Thin Body SOI FETssindhu reddy
 
Soi aalam
Soi aalamSoi aalam
Soi aalamaalamkhan
 
Silicon on Insulator (SOI) Technology
Silicon on Insulator (SOI) TechnologySilicon on Insulator (SOI) Technology
Silicon on Insulator (SOI) TechnologySudhanshu Janwadkar
 
Analog Mixed-Signal Design in FinFET Processes
Analog Mixed-Signal Design in FinFET Processes Analog Mixed-Signal Design in FinFET Processes
Analog Mixed-Signal Design in FinFET Processes Design World
 
Ic tech unit 5- VLSI Process Integration
Ic tech unit 5- VLSI Process IntegrationIc tech unit 5- VLSI Process Integration
Ic tech unit 5- VLSI Process Integrationkriticka sharma
 
CMP CW CIEL Aluminium Cable Glands - CMP Cable Glands with Cast Integral Eart...
CMP CW CIEL Aluminium Cable Glands - CMP Cable Glands with Cast Integral Eart...CMP CW CIEL Aluminium Cable Glands - CMP Cable Glands with Cast Integral Eart...
CMP CW CIEL Aluminium Cable Glands - CMP Cable Glands with Cast Integral Eart...Thorne & Derrick International
 
Athens Standard & Technical
Athens Standard & TechnicalAthens Standard & Technical
Athens Standard & TechnicalGianluca Musetti
 
High-k für Alle - Beyond DRAM capacitors and HKMG
High-k für Alle - Beyond DRAM capacitors and HKMGHigh-k für Alle - Beyond DRAM capacitors and HKMG
High-k für Alle - Beyond DRAM capacitors and HKMGJonas Sundqvist
 
Vlsi 2
Vlsi 2Vlsi 2
Vlsi 2idris01111
 
CMP Zen A324 Insulated Aluminium Cable Glands with Cast Integral Earth Lug (S...
CMP Zen A324 Insulated Aluminium Cable Glands with Cast Integral Earth Lug (S...CMP Zen A324 Insulated Aluminium Cable Glands with Cast Integral Earth Lug (S...
CMP Zen A324 Insulated Aluminium Cable Glands with Cast Integral Earth Lug (S...Thorne & Derrick International
 
HIGH-K DEVICES BY ALD FOR SEMICONDUCTOR APPLICATIONS
HIGH-K DEVICES BY ALD FOR SEMICONDUCTOR APPLICATIONSHIGH-K DEVICES BY ALD FOR SEMICONDUCTOR APPLICATIONS
HIGH-K DEVICES BY ALD FOR SEMICONDUCTOR APPLICATIONSJonas Sundqvist
 
Emc design and interconnection techniques
Emc design and interconnection techniquesEmc design and interconnection techniques
Emc design and interconnection techniquesUma Rajaram
 
Semiconductor overview
Semiconductor overviewSemiconductor overview
Semiconductor overviewNabil Chouba
 
On cmos fabrication
On cmos fabricationOn cmos fabrication
On cmos fabricationDIlawar Singh
 
Finfet
FinfetFinfet
FinfetAditya Singh
 
W06 Design and function of a functional earth system in copper-based networks
W06 Design and function of a functional earth system in copper-based networksW06 Design and function of a functional earth system in copper-based networks
W06 Design and function of a functional earth system in copper-based networksPROFIBUS and PROFINET InternationaI - PI UK
 
FD-SOI Harnessing the Power - DAC 2016 Austin Presentation
FD-SOI Harnessing the Power - DAC 2016 Austin PresentationFD-SOI Harnessing the Power - DAC 2016 Austin Presentation
FD-SOI Harnessing the Power - DAC 2016 Austin PresentationRick Tewell
 
THE CMOS VLSI DESIGN
THE CMOS VLSI DESIGNTHE CMOS VLSI DESIGN
THE CMOS VLSI DESIGNsuryateja swamy
 
22nm tri-gate technology
22nm tri-gate technology22nm tri-gate technology
22nm tri-gate technologyArjun Challu
 
Potential of an ALD compatible ferroelectric
Potential of an ALD compatible ferroelectricPotential of an ALD compatible ferroelectric
Potential of an ALD compatible ferroelectricJonas Sundqvist
 
Timothy j cash_mini_career_portfolio
Timothy j cash_mini_career_portfolioTimothy j cash_mini_career_portfolio
Timothy j cash_mini_career_portfolioTimothy Cash
 
Milan Futurology V1.1
Milan Futurology V1.1Milan Futurology V1.1
Milan Futurology V1.1Gianluca Musetti
 
Ehud tzuri 3 d challanges new
Ehud tzuri 3 d challanges newEhud tzuri 3 d challanges new
Ehud tzuri 3 d challanges newchiportal
 
Lect2 up030 (100324)
Lect2 up030 (100324)Lect2 up030 (100324)
Lect2 up030 (100324)aicdesign
 
Lect2 up020 (100324)
Lect2 up020 (100324)Lect2 up020 (100324)
Lect2 up020 (100324)aicdesign
 

More Related Content

What's hot

Analog Mixed-Signal Design in FinFET Processes
Analog Mixed-Signal Design in FinFET Processes Analog Mixed-Signal Design in FinFET Processes
Analog Mixed-Signal Design in FinFET Processes Design World
 
Ic tech unit 5- VLSI Process Integration
Ic tech unit 5- VLSI Process IntegrationIc tech unit 5- VLSI Process Integration
Ic tech unit 5- VLSI Process Integrationkriticka sharma
 
CMP CW CIEL Aluminium Cable Glands - CMP Cable Glands with Cast Integral Eart...
CMP CW CIEL Aluminium Cable Glands - CMP Cable Glands with Cast Integral Eart...CMP CW CIEL Aluminium Cable Glands - CMP Cable Glands with Cast Integral Eart...
CMP CW CIEL Aluminium Cable Glands - CMP Cable Glands with Cast Integral Eart...Thorne & Derrick International
 
Athens Standard & Technical
Athens Standard & TechnicalAthens Standard & Technical
Athens Standard & TechnicalGianluca Musetti
 
High-k für Alle - Beyond DRAM capacitors and HKMG
High-k für Alle - Beyond DRAM capacitors and HKMGHigh-k für Alle - Beyond DRAM capacitors and HKMG
High-k für Alle - Beyond DRAM capacitors and HKMGJonas Sundqvist
 
CMP Zen A324 Insulated Aluminium Cable Glands with Cast Integral Earth Lug (S...
CMP Zen A324 Insulated Aluminium Cable Glands with Cast Integral Earth Lug (S...CMP Zen A324 Insulated Aluminium Cable Glands with Cast Integral Earth Lug (S...
CMP Zen A324 Insulated Aluminium Cable Glands with Cast Integral Earth Lug (S...Thorne & Derrick International
 
HIGH-K DEVICES BY ALD FOR SEMICONDUCTOR APPLICATIONS
HIGH-K DEVICES BY ALD FOR SEMICONDUCTOR APPLICATIONSHIGH-K DEVICES BY ALD FOR SEMICONDUCTOR APPLICATIONS
HIGH-K DEVICES BY ALD FOR SEMICONDUCTOR APPLICATIONSJonas Sundqvist
 
Emc design and interconnection techniques
Emc design and interconnection techniquesEmc design and interconnection techniques
Emc design and interconnection techniquesUma Rajaram
 
Semiconductor overview
Semiconductor overviewSemiconductor overview
Semiconductor overviewNabil Chouba
 
FD-SOI Harnessing the Power - DAC 2016 Austin Presentation
FD-SOI Harnessing the Power - DAC 2016 Austin PresentationFD-SOI Harnessing the Power - DAC 2016 Austin Presentation
FD-SOI Harnessing the Power - DAC 2016 Austin PresentationRick Tewell
 
22nm tri-gate technology
22nm tri-gate technology22nm tri-gate technology
22nm tri-gate technologyArjun Challu
 
Potential of an ALD compatible ferroelectric
Potential of an ALD compatible ferroelectricPotential of an ALD compatible ferroelectric
Potential of an ALD compatible ferroelectricJonas Sundqvist
 
Timothy j cash_mini_career_portfolio
Timothy j cash_mini_career_portfolioTimothy j cash_mini_career_portfolio
Timothy j cash_mini_career_portfolioTimothy Cash
 
Ehud tzuri 3 d challanges new
Ehud tzuri 3 d challanges newEhud tzuri 3 d challanges new
Ehud tzuri 3 d challanges newchiportal
 

What's hot (20)

Analog Mixed-Signal Design in FinFET Processes
Analog Mixed-Signal Design in FinFET Processes Analog Mixed-Signal Design in FinFET Processes
Analog Mixed-Signal Design in FinFET Processes
 
Ic tech unit 5- VLSI Process Integration
Ic tech unit 5- VLSI Process IntegrationIc tech unit 5- VLSI Process Integration
Ic tech unit 5- VLSI Process Integration
 
CMP CW CIEL Aluminium Cable Glands - CMP Cable Glands with Cast Integral Eart...
CMP CW CIEL Aluminium Cable Glands - CMP Cable Glands with Cast Integral Eart...CMP CW CIEL Aluminium Cable Glands - CMP Cable Glands with Cast Integral Eart...
CMP CW CIEL Aluminium Cable Glands - CMP Cable Glands with Cast Integral Eart...
 
Athens Standard & Technical
Athens Standard & TechnicalAthens Standard & Technical
Athens Standard & Technical
 
High-k für Alle - Beyond DRAM capacitors and HKMG
High-k für Alle - Beyond DRAM capacitors and HKMGHigh-k für Alle - Beyond DRAM capacitors and HKMG
High-k für Alle - Beyond DRAM capacitors and HKMG
 
Vlsi 2
Vlsi 2Vlsi 2
Vlsi 2
 
CMP Zen A324 Insulated Aluminium Cable Glands with Cast Integral Earth Lug (S...
CMP Zen A324 Insulated Aluminium Cable Glands with Cast Integral Earth Lug (S...CMP Zen A324 Insulated Aluminium Cable Glands with Cast Integral Earth Lug (S...
CMP Zen A324 Insulated Aluminium Cable Glands with Cast Integral Earth Lug (S...
 
HIGH-K DEVICES BY ALD FOR SEMICONDUCTOR APPLICATIONS
HIGH-K DEVICES BY ALD FOR SEMICONDUCTOR APPLICATIONSHIGH-K DEVICES BY ALD FOR SEMICONDUCTOR APPLICATIONS
HIGH-K DEVICES BY ALD FOR SEMICONDUCTOR APPLICATIONS
 
Emc design and interconnection techniques
Emc design and interconnection techniquesEmc design and interconnection techniques
Emc design and interconnection techniques
 
Semiconductor overview
Semiconductor overviewSemiconductor overview
Semiconductor overview
 
On cmos fabrication
On cmos fabricationOn cmos fabrication
On cmos fabrication
 
Finfet
FinfetFinfet
Finfet
 
W06 Design and function of a functional earth system in copper-based networks
W06 Design and function of a functional earth system in copper-based networksW06 Design and function of a functional earth system in copper-based networks
W06 Design and function of a functional earth system in copper-based networks
 
FD-SOI Harnessing the Power - DAC 2016 Austin Presentation
FD-SOI Harnessing the Power - DAC 2016 Austin PresentationFD-SOI Harnessing the Power - DAC 2016 Austin Presentation
FD-SOI Harnessing the Power - DAC 2016 Austin Presentation
 
THE CMOS VLSI DESIGN
THE CMOS VLSI DESIGNTHE CMOS VLSI DESIGN
THE CMOS VLSI DESIGN
 
22nm tri-gate technology
22nm tri-gate technology22nm tri-gate technology
22nm tri-gate technology
 
Potential of an ALD compatible ferroelectric
Potential of an ALD compatible ferroelectricPotential of an ALD compatible ferroelectric
Potential of an ALD compatible ferroelectric
 
Timothy j cash_mini_career_portfolio
Timothy j cash_mini_career_portfolioTimothy j cash_mini_career_portfolio
Timothy j cash_mini_career_portfolio
 
Milan Futurology V1.1
Milan Futurology V1.1Milan Futurology V1.1
Milan Futurology V1.1
 
Ehud tzuri 3 d challanges new
Ehud tzuri 3 d challanges newEhud tzuri 3 d challanges new
Ehud tzuri 3 d challanges new
 

Similar to UDSM and BiCMOS Technologies Lecture

Lect2 up030 (100324)
Lect2 up030 (100324)Lect2 up030 (100324)
Lect2 up030 (100324)aicdesign
 
Lect2 up020 (100324)
Lect2 up020 (100324)Lect2 up020 (100324)
Lect2 up020 (100324)aicdesign
 
MOSFET, SOI-FET and FIN-FET-ABU SYED KUET
MOSFET, SOI-FET and FIN-FET-ABU SYED KUETMOSFET, SOI-FET and FIN-FET-ABU SYED KUET
MOSFET, SOI-FET and FIN-FET-ABU SYED KUETA. S. M. Jannatul Islam
 
Easiest Monolithic 3D IC
Easiest Monolithic 3D ICEasiest Monolithic 3D IC
Easiest Monolithic 3D ICZvi Or-Bach
 
11.proposed thermal circuit model for the cost effective design of fin fet
11.proposed thermal circuit model for the cost effective design of fin fet11.proposed thermal circuit model for the cost effective design of fin fet
11.proposed thermal circuit model for the cost effective design of fin fetAlexander Decker
 
Proposed thermal circuit model for the cost effective design of fin fet
Proposed thermal circuit model for the cost effective design of fin fetProposed thermal circuit model for the cost effective design of fin fet
Proposed thermal circuit model for the cost effective design of fin fetAlexander Decker
 
DfR Advanced Packaging
DfR Advanced PackagingDfR Advanced Packaging
DfR Advanced PackagingGreg Caswell
 
CMOS VLSI design
CMOS VLSI designCMOS VLSI design
CMOS VLSI designRajan Kumar
 
Structural and Electrical Analysis of Various MOSFET Designs
Structural and Electrical Analysis of Various MOSFET DesignsStructural and Electrical Analysis of Various MOSFET Designs
Structural and Electrical Analysis of Various MOSFET DesignsIJERA Editor
 
Using polysilicon as a gate contact instead of metal in CMOS
Using polysilicon as a gate contact instead of metal in CMOSUsing polysilicon as a gate contact instead of metal in CMOS
Using polysilicon as a gate contact instead of metal in CMOSEng Ansam Hadi
 
Vlsi design and fabrication ppt
Vlsi design and fabrication pptVlsi design and fabrication ppt
Vlsi design and fabrication pptManjushree Mashal
 

Similar to UDSM and BiCMOS Technologies Lecture (20)

Lect2 up030 (100324)
Lect2 up030 (100324)Lect2 up030 (100324)
Lect2 up030 (100324)
 
Lect2 up020 (100324)
Lect2 up020 (100324)Lect2 up020 (100324)
Lect2 up020 (100324)
 
MOSFET, SOI-FET and FIN-FET-ABU SYED KUET
MOSFET, SOI-FET and FIN-FET-ABU SYED KUETMOSFET, SOI-FET and FIN-FET-ABU SYED KUET
MOSFET, SOI-FET and FIN-FET-ABU SYED KUET
 
Easiest Monolithic 3D IC
Easiest Monolithic 3D ICEasiest Monolithic 3D IC
Easiest Monolithic 3D IC
 
Ijetr011811
Ijetr011811Ijetr011811
Ijetr011811
 
Cmos
CmosCmos
Cmos
 
11.proposed thermal circuit model for the cost effective design of fin fet
11.proposed thermal circuit model for the cost effective design of fin fet11.proposed thermal circuit model for the cost effective design of fin fet
11.proposed thermal circuit model for the cost effective design of fin fet
 
Proposed thermal circuit model for the cost effective design of fin fet
Proposed thermal circuit model for the cost effective design of fin fetProposed thermal circuit model for the cost effective design of fin fet
Proposed thermal circuit model for the cost effective design of fin fet
 
My VLSI.pptx
My VLSI.pptxMy VLSI.pptx
My VLSI.pptx
 
DfR Advanced Packaging
DfR Advanced PackagingDfR Advanced Packaging
DfR Advanced Packaging
 
A0210106
A0210106A0210106
A0210106
 
Larrys Tech Library
Larrys Tech LibraryLarrys Tech Library
Larrys Tech Library
 
CMOS VLSI design
CMOS VLSI designCMOS VLSI design
CMOS VLSI design
 
Structural and Electrical Analysis of Various MOSFET Designs
Structural and Electrical Analysis of Various MOSFET DesignsStructural and Electrical Analysis of Various MOSFET Designs
Structural and Electrical Analysis of Various MOSFET Designs
 
Cmos
CmosCmos
Cmos
 
Using polysilicon as a gate contact instead of metal in CMOS
Using polysilicon as a gate contact instead of metal in CMOSUsing polysilicon as a gate contact instead of metal in CMOS
Using polysilicon as a gate contact instead of metal in CMOS
 
cmos of metal oxide field effect tansistor
cmos of metal oxide field effect tansistorcmos of metal oxide field effect tansistor
cmos of metal oxide field effect tansistor
 
VLSI
VLSIVLSI
VLSI
 
Vlsi design and fabrication ppt
Vlsi design and fabrication pptVlsi design and fabrication ppt
Vlsi design and fabrication ppt
 
N well process
N well processN well process
N well process
 

More from aicdesign

Lect2 up400 (100329)
Lect2 up400 (100329)Lect2 up400 (100329)
Lect2 up400 (100329)aicdesign
 
Lect2 up390 (100329)
Lect2 up390 (100329)Lect2 up390 (100329)
Lect2 up390 (100329)aicdesign
 
Lect2 up380 (100329)
Lect2 up380 (100329)Lect2 up380 (100329)
Lect2 up380 (100329)aicdesign
 
Lect2 up370 (100329)
Lect2 up370 (100329)Lect2 up370 (100329)
Lect2 up370 (100329)aicdesign
 
Lect2 up360 (100329)
Lect2 up360 (100329)Lect2 up360 (100329)
Lect2 up360 (100329)aicdesign
 
Lect2 up350 (100328)
Lect2 up350 (100328)Lect2 up350 (100328)
Lect2 up350 (100328)aicdesign
 
Lect2 up340 (100501)
Lect2 up340 (100501)Lect2 up340 (100501)
Lect2 up340 (100501)aicdesign
 
Lect2 up330 (100328)
Lect2 up330 (100328)Lect2 up330 (100328)
Lect2 up330 (100328)aicdesign
 
Lect2 up320 (100328)
Lect2 up320 (100328)Lect2 up320 (100328)
Lect2 up320 (100328)aicdesign
 
Lect2 up310 (100328)
Lect2 up310 (100328)Lect2 up310 (100328)
Lect2 up310 (100328)aicdesign
 
Lect2 up300 (100328)
Lect2 up300 (100328)Lect2 up300 (100328)
Lect2 up300 (100328)aicdesign
 
Lect2 up290 (100328)
Lect2 up290 (100328)Lect2 up290 (100328)
Lect2 up290 (100328)aicdesign
 
Lect2 up280 (100328)
Lect2 up280 (100328)Lect2 up280 (100328)
Lect2 up280 (100328)aicdesign
 
Lect2 up270 (100328)
Lect2 up270 (100328)Lect2 up270 (100328)
Lect2 up270 (100328)aicdesign
 
Lect2 up260 (100328)
Lect2 up260 (100328)Lect2 up260 (100328)
Lect2 up260 (100328)aicdesign
 
Lect2 up250 (100328)
Lect2 up250 (100328)Lect2 up250 (100328)
Lect2 up250 (100328)aicdesign
 
Lect2 up240 (100328)
Lect2 up240 (100328)Lect2 up240 (100328)
Lect2 up240 (100328)aicdesign
 
Lect2 up230 (100327)
Lect2 up230 (100327)Lect2 up230 (100327)
Lect2 up230 (100327)aicdesign
 
Lect2 up220 (100327)
Lect2 up220 (100327)Lect2 up220 (100327)
Lect2 up220 (100327)aicdesign
 
Lect2 up210 (100327)
Lect2 up210 (100327)Lect2 up210 (100327)
Lect2 up210 (100327)aicdesign
 

More from aicdesign (20)

Lect2 up400 (100329)
Lect2 up400 (100329)Lect2 up400 (100329)
Lect2 up400 (100329)
 
Lect2 up390 (100329)
Lect2 up390 (100329)Lect2 up390 (100329)
Lect2 up390 (100329)
 
Lect2 up380 (100329)
Lect2 up380 (100329)Lect2 up380 (100329)
Lect2 up380 (100329)
 
Lect2 up370 (100329)
Lect2 up370 (100329)Lect2 up370 (100329)
Lect2 up370 (100329)
 
Lect2 up360 (100329)
Lect2 up360 (100329)Lect2 up360 (100329)
Lect2 up360 (100329)
 
Lect2 up350 (100328)
Lect2 up350 (100328)Lect2 up350 (100328)
Lect2 up350 (100328)
 
Lect2 up340 (100501)
Lect2 up340 (100501)Lect2 up340 (100501)
Lect2 up340 (100501)
 
Lect2 up330 (100328)
Lect2 up330 (100328)Lect2 up330 (100328)
Lect2 up330 (100328)
 
Lect2 up320 (100328)
Lect2 up320 (100328)Lect2 up320 (100328)
Lect2 up320 (100328)
 
Lect2 up310 (100328)
Lect2 up310 (100328)Lect2 up310 (100328)
Lect2 up310 (100328)
 
Lect2 up300 (100328)
Lect2 up300 (100328)Lect2 up300 (100328)
Lect2 up300 (100328)
 
Lect2 up290 (100328)
Lect2 up290 (100328)Lect2 up290 (100328)
Lect2 up290 (100328)
 
Lect2 up280 (100328)
Lect2 up280 (100328)Lect2 up280 (100328)
Lect2 up280 (100328)
 
Lect2 up270 (100328)
Lect2 up270 (100328)Lect2 up270 (100328)
Lect2 up270 (100328)
 
Lect2 up260 (100328)
Lect2 up260 (100328)Lect2 up260 (100328)
Lect2 up260 (100328)
 
Lect2 up250 (100328)
Lect2 up250 (100328)Lect2 up250 (100328)
Lect2 up250 (100328)
 
Lect2 up240 (100328)
Lect2 up240 (100328)Lect2 up240 (100328)
Lect2 up240 (100328)
 
Lect2 up230 (100327)
Lect2 up230 (100327)Lect2 up230 (100327)
Lect2 up230 (100327)
 
Lect2 up220 (100327)
Lect2 up220 (100327)Lect2 up220 (100327)
Lect2 up220 (100327)
 
Lect2 up210 (100327)
Lect2 up210 (100327)Lect2 up210 (100327)
Lect2 up210 (100327)
 

UDSM and BiCMOS Technologies Lecture

  • 1. Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-1 LECTURE 040 - ULTRA-DEEP SUBMICRON AND BiCMOS TECHNOLOGIES LECTURE ORGANIZATION Outline • Ultra-deep submicron CMOS technology - Features - Advantages - Problems • BiCMOS technology process flow - CMOS is typical submicron (0.5 μm) • Summary CMOS Analog Circuit Design, 2nd Edition Reference New material CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-2 ULTRA-DEEP SUBMICRON (UDSM) CMOS TECHNOLOGY USDM Technology • Lmin 0.1 microns • Minimum feature size less than 100 nanometers • Today’s state of the art: - 65 nm drawn length - 15 nm lateral diffusion (35 nm gate length) - 1.2 nm transistor gate oxide - 8 layers of copper interconnect • Specialized processing is used to increase drive capability and maintain low off currents CMOS Analog Circuit Design © P.E. Allen - 2010
  • 2. Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-3 65 Nanometer CMOS Technology TEM cross-section of a 35 nm NMOS and PMOS transistors.† NMOS: PMOS: NMOS 220 nm pitch These transistors utilize enhanced channel strains to increase drive capability and to reduce off currents. † P. Bai, et. Al., “A 65nm Lobic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57 μm2 SRAM Cell, IEEE Inter. Electron Device Meeting, Dec. 12-15, 2005. CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-4 UDSM Metal and Interconnects Physical aspects: Layer Pitch (nm) Thickness (nm) Aspect Ratio Isolation 220 230 - Polysilicon 220 90 - Contacted Gate Pitch 220 - - Metal 1 210 170 1.6 Metal 2 210 190 1.8 Metal 3 220 200 1.8 Metal 4 280 250 1.8 Metal 5 330 300 1.8 Metal 6 480 430 1.8 Metal 7 720 650 1.8 Metal 8 1080 975 1.8 CMOS Analog Circuit Design © P.E. Allen - 2010
  • 3. Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-5 What are the Advantages of UDSM CMOS Technology? Digital Viewpoint: • Improved Ion/Ioff 70 Mbit SRAM chip: • Reduced gate capacitance • Higher drive current capability • Reduced interconnect density • Reduction of active power Analog Viewpoint: • More levels of metal • Higher fT • Higher capacitance density • Reduced junction capacitance per gm CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-6 What are the Disadvantages of UDSM CMOS Technology (for Analog)? • Reduction in power supply resulting in reduced headroom • Gate leakage currents • Reduced small-signal intrinsic gains • Increased nonlinearity (IIP3) • Noise and matching?? Intrinsic gain and IP3 as a function of the gate overdrive for decreasing VDS:† † Anne-Johan Annema, et. Al., “Analog Circuits in Ultra-Deep-Submicron CMOS,” IEEE J. of Solid-State Circuits, Vol. 40, No. 1, Jan. 2005, pp. 132- 143. CMOS Analog Circuit Design © P.E. Allen - 2010
  • 4. Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-7 What is the Gate Leakage Problem? Gate current occurs in thin oxide devices due to direct tunneling through the thin oxide. Gate current depends on: 1.) The gate-source voltage (and the drain-gate voltage) iGS = K1vGS exp(K2vGS) and iGD = K3vGD exp(K4vGD) 2.) Gate area – NMOS leakage 6nA/μm2 and PMOS leakage 3nA/μm2 Unfortunately, the gate leakage current is nonlinear with respect to the gate-source and gate-drain voltages. A possible model is: f(vGD) f(vGS) 051205-03 − vGD + + f(vSG) vGS f(vDG) − + vSG − − vDG + NMOS PMOS Large Signal Models ggd ggs NMOS gsg gdg PMOS Small Signal Models Base current cancellation schemes used for BJTs are difficult to apply to the MOSFET. CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-8 Gate Leakage and fgate The gate leakage can be represented by a conductance, ggate, in parallel with the gate capacitance, Cgate. Since these two elements have identical area dependence, they result in a frequency, fgate, that is fairly independent of the drain-source voltage, vds. fgate = ggate 2Cgate 1.5·1016vGS 2etox(vGS-13.6)(NMOS) 0.5·1016vGS 2etox(vGS-13.6)(PMOS) where tox is in nm and vGS is in V. For frequencies above fgate the MOSFET looks capacitive and below fgate, the MOSFET looks resistive (gate leakage). CMOS Analog Circuit Design © P.E. Allen - 2010
  • 5. Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-9 UDSM CMOS Technology Summary • Increased transconductance and frequency capability • Low power supply voltages • Reduced parasitics • Gate leakage causes challenges for analog applications of UDSM technology - Can no longer use the MOSFET for capacitance - Conflict between matching and gate leakage • Other issues - Noise - Zero temperature coefficient behavior - Etc. CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-10 BiCMOS TECHNOLOGY Typical 0.5μm BiCMOS Technology Masking Sequence: 1. Buried n+ layer 9. Base oxide/implant 17. Contacts 2. Buried p+ layer 10. Emitter implant 18. Metal 1 3. Collector tub 11. Poly 1 19. Via 1 4. Active area 12. NMOS lightly doped drain 20. Metal 2 5. Collector sinker 13. PMOS lightly doped drain 21. Via 2 6. n-well 14. n+ source/drain 22. Metal 3 7. p-well 15. p+ source/drain 23. Nitride passivation 8. Emitter window 16. Silicide protection Notation used in the following slides: BSPG = Boron and Phosphorus doped Silicate Glass (oxide) Kooi Nitride = A thin layer of silicon nitride on the silicon surface as a result of the reaction of silicon with the HN3 generated, during the field oxidation. TEOS = Tetro-Ethyl-Ortho-Silicate. A chemical compound used to deposit conformal oxide films. CMOS Analog Circuit Design © P.E. Allen - 2010
  • 6. Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-11 n+ and p+ Buried Layers Starting Substrate: p-substrate 1μm BiCMOS-01 5μm n+ and p+ Buried Layers: NPN Transistor PMOS Transistor NMOS Transistor n+ buried layer p+ buried layer p-substrate n+ buried layer p+ buried layer 1μm 5μm BiCMOS-02 CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-12 Epitaxial Growth NPN Transistor PMOS Transistor NMOS Transistor p-well n-well p-well n+ buried layer p-substrate n-well n+ buried layer p+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-03 Comment: • As the epi layer grows vertically, it assumes the doping level of the substrate beneath it. • In addition, the high temperature of the epitaxial process causes the buried layers to diffuse upward and downward. CMOS Analog Circuit Design © P.E. Allen - 2010
  • 7. Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-13 Collector Tub NPN Transistor PMOS Transistor NMOS Transistor n-well p-well n+ buried layer p+ buried layer p-substrate p-well Original Area of CollectorTub Implant Collector Tub n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-04 Comment: • The collector area is developed by an initial implant followed by a drive-in diffusion to form the collector tub. CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-14 Active Area Definition NPN Transistor PMOS Transistor NMOS Transistor n-well p-well n+ buried layer p+ buried layer p-substrate p-well Collector Tub n+ buried layer p+ buried layer Nitride α-Silicon p-type Epitaxial Silicon 1μm 5μm BiCMOS-05 Comment: • The silicon nitride is use to impede the growth of the thick oxide which allows contact to the substrate • -silicon is used for stress relief and to minimize the bird’s beak encroachment CMOS Analog Circuit Design © P.E. Allen - 2010
  • 8. Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-15 Field Oxide NPN Transistor PMOS Transistor NMOS Transistor FOX Field Oxide Field Oxide Field Oxide n-well p-well n+ buried layer p+ buried layer p-substrate FOX p-well Collector Tub n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-06 Comments: • The field oxide is used to isolate surface structures (i.e. metal) from the substrate CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-16 Collector Sink and n-Well and p-Well Definitions NPN Transistor PMOS Transistor NMOS Transistor Threshold Adjust Anti-Punch Through FOX Field Oxide Field Oxide Collector Sink Anti-Punch Through Field Oxide Threshold Adjust n-well p-well p-well n+ buried layer p+ buried layer p-substrate Collector Tub FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-07 CMOS Analog Circuit Design © P.E. Allen - 2010
  • 9. Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-17 Base Definition NPN Transistor PMOS Transistor NMOS Transistor FOX Field Oxide Field Oxide Field Oxide n-well p-well p-well n+ buried layer p+ buried layer p-substrate FOX Collector Tub n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-08 CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-18 Definition of the Emitter Window and Sub-Collector Implant NPN Transistor PMOS Transistor NMOS Transistor FOX Field Oxide Field Oxide n-well Field Oxide p-well p-well n+ buried layer p+ buried layer p-substrate FOX Sacrifical Oxide Sub-Collector n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-09 CMOS Analog Circuit Design © P.E. Allen - 2010
  • 10. Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-19 Emitter Implant PMOS Transistor NMOS Transistor FOX Field Oxide Field Oxide n-well Field Oxide p-well p-well n+ buried layer p+ buried layer p-substrate NPN Transistor Emitter Implant Collector Tub FOX Sub-Collector n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-10 Comments: • The polysilicon above the base is implanted with n-type carriers CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-20 Emitter Diffusion NPN Transistor PMOS Transistor NMOS Transistor FOX Field Oxide Field Oxide n-well Field Oxide p-well p-well n+ buried layer p+ buried layer p-substrate FOX Emitter n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-11 Comments: • The polysilicon not over the emitter window is removed and the n-type carriers diffuse toward the base forming the emitter CMOS Analog Circuit Design © P.E. Allen - 2010
  • 11. Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-21 Formation of the MOS Gates and LD Drains/Sources NPN Transistor PMOS Transistor NMOS Transistor FOX Field Oxide Field Oxide Field Oxide n-well p-well p-well n+ buried layer p+ buried layer p-substrate FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-12 Comments: • The surface of the region where the MOSFETs are to be built is cleared and a thin gate oxide is deposited with a polysilicon layer on top of the thin oxide • The polysilicon is removed over the source and drain areas • A light source/drain diffusion is done for the NMOS and PMOS (separately) CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-22 Heavily Doped Source/Drain NPN Transistor PMOS Transistor NMOS Transistor FOX Field Oxide Field Oxide Field Oxide n-well p-well p-well n+ buried layer p+ buried layer p-substrate FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-13 Comments: • The sidewall spacers prevent the heavy source/drain doping from being near the channel of the MOSFET CMOS Analog Circuit Design © P.E. Allen - 2010
  • 12. Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-23 Siliciding NPN Transistor PMOS Transistor NMOS Transistor Silicide TiSi2 Silicide TiSi2 Silicide TiSi2 FOX Field Oxide Field Oxide n-well Field Oxide p-well p-well n+ buried layer p+ buried layer p-substrate FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm 5μm BiCMOS-14 Comments: • Siliciding is used to reduce the resistance of the polysilicon and to provide ohmic contacts to the base, emitter, collector, sources and drains CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-24 Contacts Tungsten Plugs Tungsten Plugs Tungsten Plugs TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG Field Oxide Field Oxide Field Field Oxide Oxide n-well p-well p-well n+ buried layer p+ buried layer p-substrate FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm FOX BiCMOS-15 5μm Comments: • A dielectric is deposited over the entire wafer • One of the purposes of the dielectric is to smooth out the surface • Tungsten plugs are used to make electrical contact between the transistors and metal1 CMOS Analog Circuit Design © P.E. Allen - 2010
  • 13. Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-25 Metal1 Metal1 Metal1 Metal1 TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG Field Oxide Field Oxide Field Field Oxide Oxide n-well p-well p-well n+ buried layer p+ buried layer p-substrate FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm FOX BiCMOS-16 5μm CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-26 Metal1-Metal2 Vias Tungsten Plugs Oxide/ SOG/ Oxide TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG Field Oxide Field Oxide Field Field Oxide Oxide n-well p-well p-well n+ buried layer p+ buried layer p-substrate FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm FOX BiCMOS-17 5μm CMOS Analog Circuit Design © P.E. Allen - 2010
  • 14. Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-27 Metal2 Metal 2 Oxide/ SOG/ Oxide TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG Field Oxide Field Oxide Field Field Oxide Oxide n-well p-well p-well n+ buried layer p+ buried layer p-substrate FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm FOX BiCMOS-18 5μm CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-28 Metal2-Metal3 Vias TEOS/ BPSG/ SOG Oxide/ SOG/ Oxide TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG Field Oxide Field Oxide Field Field Oxide Oxide n-well p-well p-well n+ buried layer p+ buried layer p-substrate FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm FOX BiCMOS-19 5μm Comments: • The metal2-metal3 vias will be filled with metal3 as opposed to tungsten plugs CMOS Analog Circuit Design © P.E. Allen - 2010
  • 15. Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-29 Completed Wafer Nitride (Hermetically seals the wafer) Metal3 TEOS/ BPSG/ SOG Oxide/ SOG/ Oxide Oxide/SOG/Oxide Metal3 Vias TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG Field Oxide Field Oxide Field Field Oxide Oxide n-well p-well p-well n+ buried layer p+ buried layer p-substrate FOX n+ buried layer p+ buried layer p-type Epitaxial Silicon 1μm FOX BiCMOS-20 5μm CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-30 SUMMARY • UDSM technology typically has a minimum channel length less than 0.1μm • UDSM transistors utilize enhanced channel strains to increase drive capability and reduce off currents • Advantages of UDSM technology include: - Smaller devices - Higher speeds and transconductances - Improved Ion/Ioff • Disadvantages of UDSM technology include: - Gate leakage currents - Reduced small signal gains - Increased nonlinearity • BiCMOS technology - Offers both CMOS transistors and a high performance vertical BJT - CMOS is typically a generation behind - Silicon germanium can be used to enhance the BJT performance CMOS Analog Circuit Design © P.E. Allen - 2010