This document discusses ultra-thin body SOI MOSFETs. It describes how SOI technology uses a layered silicon-insulator-silicon substrate to improve performance and reduce short-channel effects compared to conventional silicon. Ultra-thin body SOI can further suppress short-channel effects and reduce sub-threshold gate leakage. The document examines the effects of body doping, buried oxide thickness, inversion charge, and mobility on ultra-thin body SOI MOSFET performance. It concludes that ultra-thin body SOI with high-k gate dielectrics can improve scaling and performance for high-density, low-power applications.

1. Ultra-thin Body SOI MOSFETs Prajon Raj Shakya Master of Science in Electrical Engineering Instructor: Dr. Long Que Electrical Engineering Program Louisiana Tech University Ruston, LA 71272, USA

3. Control over SCE (short-channel effect) and scaling device architecture.

4. Layered Si-Insulator-Si substrate in place of conventional Si.

5. SiO2, or SiGe: insulating material as BOX: improved performance and reduced SCE.

6. New generation SOI as multiple gate, FinFETs, triple gate, GAA (Gate All Around).

7. UTB-SOI suppress SCE, scale gate length and reduce sub-threshold gate leakage current.

8. For high density, high performance and low power applications.Fig. 1: Schematic diagram of an UTB-SOI MOSFET [8]

9. Performance of SOI devices 90% lower junction capacitance; near ideal sub-threshold swing; reduce device cross-talk; Lower junction leakage -> low switching energy of the transistor No latch-up; Increased radiation hardness Do not suffer from substrate reverse bias effects -> low-power devices. Better electrostatic control: reduce S-D leakage and SCE. Full dielectric isolation of the transistor Reduced junction area Impact ionization strongly balanced by thermal recombination. Critical drawback as: floating body effects: body potential shifts –shift in V T , sub-threshold swing, and kink effects: minimized by thinner silicon.

10. UTB SOI MOSFET SOI: PD-SOI (Partially depleted- SOI) and FD-SOI (Fully depleted-SOI) FD-SOI: small and well-controlled thickness channel; high series resistance Higher trans-conductance and reduced floating body effects compared to PD-SOI. Thin body thickness; reduced parasitic drain-to-body capacitance but drain field fringe increases DIBL (Drain Induced Barrier Lowering) and gate current worst at short-channel. PDSOI: thicker body; high drain-body capacitance and degraded operating speed. UTB concept evolve to control short-channel effect; along with TBO(Thin Buried Oxide) UTB: Typical body thickness: 1/4th of gate length While TBO: equivalent to gate length. Variation of Vt due to variation of body thickness overcomes all other factors in UTB-SOI devices.

11. Effect on Inversion charge Fig.2: Inversion charge density versus gate voltage for different buried oxide layer thicknesses in undoped UTB-SOI MOSFETs with the mid-gap gates for Vch = 0. [8] Fig. 3: Inversion charge density versus gate voltage for different silicon film thicknesses in undoped UTB-SOI MOSFETs with the mid-gap gates for Vch = 0. [8]

13. S,B and D: doped uniformly: DIBL and low-drain threshold rollofffs are defined with Vds=1V and 50mv, separately.

14. Substrate bias: 0 V to avoid threshold roll-off.

15. SCE reduced with high doping in silicon films (4-10nm) but high threshold voltage and low carrier mobility due to impurities.Fig.4: High drain threshold voltage roll-offs for SOI with varying channel doping concentration [9]

17. tBOX = 5nm has L min=38nm and increase with tBOX with L min=48nm for t BOX=100nm and 200nm.

18. S/D lateral field coupling in the BOX does not increase with BOX thickness after the tBOX is 2 times larger than the channel length of the device with 100mv threshold roll-off. Fig.5: High drain threshold voltage rol-loffs for doped FDSOI with different BOX thicknesses [9]

20. Limit of deca-nm regime.

21. 4-point method used to evaluate for µeffthickness from 44.5nm to 0.9nm.

22. Degradation of mobility below 3nm: due to influence of thickness/ surface roughness.Fig.6: Electron mobility vs. Ninv for body thicknesses from tSi=44.5nm down to 0.9nm and universal mobility after [10]

24. Mobility degradation starts after 2.7nm

25. Mobility in DG-UTB MOSFET is higher than SG-UTB MOSFET.Fig.7: µeff – Ninvcharactersistics of (110) pMOSFETs at 300K [11]

26. Conclusion Different types of SOI and UTB-SOI as improvement of performance. Various effects as of body doping, mobility enhancement and degradation and inversion charge. Presents the concept of UTB-SOI in terms of device scaling with improved performance. Further, various UTB-SOI as DG, SG, Fin-Fet, GAA and others are being developed for the better performance on various perspectives. UTB-SOI with the adoption of high-k/metal technique are also being developed that acts on the performance of limitation of mobility. Applications in high voltage and Smart Power ckt, RF ckt, Si-based optoelectronic devices, MEMS (Micro Electro Mechanical Systems), back-side illuminated image sensors etc.

27. References [1] B. G. Streetman and S. Banerjee, Solid State Electronic Devices, 5th ed. New Jersey: Prentice Hall, 2000. [2] B.-Y. Nguyen, G. Celler, and C. Mazuré, “A Review of SOI Technology and its Applications,”Journal of Integrated Circuits and Systems, vol. 4, no.4, pp. 51-54, 19th August 2009. [3] E. Sangiorgi, N. Barin, M. Braccioli, and C. Fiegna, “32nm Technology node Double-Gate SOI MOSFET using SiO2 gate stacks,” International Workshop on Nano CMOS, 2006, pp.38-42, Jan. 30 2006-Feb. 1 2006. [4] A. Griffoni, S. Thijs, C. Russ, D. Tremouilles, D. Linten, M. Scholz, E. Simoen, C. Claeys, G. Meneghesso, and G. Groeseneken, “Electrical-Based ESD Characterization of Ultrathin-Body SOI MOSFETs,” IEEE Transactions on Device and Materials Reliability, vol.10, no.1, pp.130-141, March 2010. [5] C. Yang-Kyu, K. Asano, N. Lindert, V. Subramanian, K. Tsu-Jae, J. Bokor, and H. Chenming, "Ultrathin-body SOI MOSFET for deep-sub-tenth micron era," IEEE Electron Device Letters, vol. 21, pp. 254-255, 2000. [6] S. A. Vitale, P. W. Wyatt, N. Checka, J. Kedzierski and C. L. Keast, "FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics," Proceedings of the IEEE , vol.98, no.2, pp.333-342, Feb. 2010. [7] Y. Fu-Liang, H. Jiunn-Ren, and L. Yiming, "Electrical Characteristic Fluctuations in Sub-45nm CMOS Devices," IEEE Custom Integrated Circuits Conference, 2006 (CICC '06), pp. 691-694, Sept. 2006. [8] J. He, X. Zhang, G. Zhang, M. Chan and Y. Wang, "A carrier-based analytic model for undoped (lightly doped) ultra-thin-body silicon-on-insulator (UTB-SOI) MOSFETs," 7th International Symposium on Quality Electronic Design, 2006. (ISQED '06), pp.6 pp.-132, 27-29 March 2006. [9] W. –Y. Lu, and Y. Taur, "Effect of Body Doping on the Scaling of Ultrathin SOI MOSFETs," International Conference on Simulation of Semiconductor Processes and Devices, 2006, pp.294-297, 6-8 Sept. 2006. [10] M. Schmidt, M.C. Lemme, H.D.B. Gottlob, H. Kurz, F. Driussi, and L. Selmi, "Mobility extraction of UTB n-MOSFETs down to 0.9 nm SOI thickness," 10th International Conference onUltimate Integration of Silicon, 2009 (ULIS 2009), pp.27-30, 18-20th March 2009. [11] T. Hiramoto, G. Tsutsui, K. Shimizu and M. Kobayashi, "Transport in ultra-thin-body SOI and silicon nanowire MOSFETs," InternationalSemiconductor Device Research Symposium, 2007, pp.1-2, 12-14 Dec. 2007.

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