1. Deyu (Darren) Jiao
785 Weyburn Terrace, Apt. 212, Los Angeles, CA 90024 | (919) 627-2748
7103 McQueen Drive, Durham, NC 27705 | deyu.jiao@duke.edu
EDUCATION
Duke University Durham, NC
M.S., Electrical & Computer Engineering, GPA: 3.9 May 2016
Relevant Coursework: CMOS VLSI Design Methodologies, Fundamental of Computer Systems and Engineering,
Semiconductor Devices of IC, Digital Integrated Circuits, Advanced Digital System Design, VLSI System Testing, Data
Structure and Algorism in C++, ASIC Verification
Southeast University Nanjing, China
B.S., Information Engineering (equivalent of Electrical Engineering in U.S.), GPA: 3.58 April 2014
WORK EXPERIENCE
Analog Designer Intern Nanjing, China
Institute of RF- & OE-ICS, China Nanjing Wireless Valley June 2013 – July 2013
 Increased 5 times unity-gain bandwidth and 1.75 times open-loop gain by creating layout by designing a two-stage
full differential op-amp on Cadence
 Achieved and exceeded the expected requirement of unity-gain bandwidth, open-loop gain, stability and power
consumption by allocating CMOS transistors' parameters, doing simulation and layout
PROJECT EXPERIENCE
Undergraduate Researcher, Southeast University Nanjing, China
Personal Computer Aide based on MFC September 2011
 Implemented functions of simultaneous performance with starting-up, automatic calculating and recording computer-
used time, timing reminder for rest, and writing memorandum by utilizing C++
 Realized setting the program to autorun on startup through registry operations
Design and Implementation of an Electromagnetic Spectrum Sensing Verification System March 2013
 Established a simple communication system with competence of spectrum sensing by setting up the physical
platform and software procedure, verifying the spectrum sensing and short-range communication using dynamic
spectrum resource
 Accomplished spectrum sensing through carrier sensing based on Received Signal Strength Indicator and the
determination of decision threshold
Graduate Researcher, Duke University Durham, NC
Un-pipelined Single-cycle Processor October 2014
 Implemented a 32-bit un-pipelined RISC processor based on simplified ISA by utilizing VHDL in Quartus II based
on FPGA
 Established a functional datapath by incorporating register file, instruction memory, data memory and ALU with
control signals
Write-back Cache based on FPGA November 2014
 Developed a direct-mapped 8MB write-back cache by utilizing VHDL in Quartus II based on FPGA
 Optimized the maximum clock frequency to 90 MHz and the hit latency to 2 clock cycle
Variable Frequency Pulse-Width Modulator November 2014
 Developed a 8-bit frequency divider, the input of which reached 16MHz, with divide ratio from 1 to 256 and 16-level
duty adjustment through full-custom VLSI layout design on Mentor Graphics
 Speeded up the circuit and decreased the latency by designing different structures of logic and minimized the area by
arranging layout considerately
AWARDS
One of 7 Finalists for 2013 Interdisciplinary Contest in Modeling, COMAP, U.S. April 2013
Excellent Leader of 7th
Students' Union, Southeast University, China December 2012