1. Zhengkai Ye
Address:305 Elan Village Ln Unit 323, San Jose, CA Cell: 551-222-1845 Email:zhengkaiye7@gmail.com
Objective More than 3 years’ hands-on experience in digital design and electrical design, familiar with
pipeline processor architecture, Verilog C/C++ System Verilog programming and signal design
concepts. Master Student in Electrical Engineering graduated May.2016, dual concentration on
Embedded Systems and Computer Architecture, specializing in hardware design, FPGA
development. Seeking a full-time/intern position in electrical and digital design.
Education Stevens Institute of Technology, Hoboken, NJ
Masterof Engineering in Electrical Engineering Expected May 2016
Concentration: Embedded Systems GPA: 3.78/4.0
Jiangnan University (JNU), WUXI, China
Bachelor degree of Communication Engineering June 2014
Experience Stevens Institute of Technology
Control Unit Designer, Design of 5-Stage Pipeline RISC processor Sept.2015-Dec.2015
 Worked with teammates to develop processorarchitecture, including Bus, ALU, and
Control Unit, Memory, Cache, and internal signals between parts and Instruction set
 Architected control unit in Modelsim with Verilog
 Coordinated with teammates to use block memory to simulate main memory and ROM,
and store compiled machine code
 Supported detecting and handling data/controlhazard, and interrupt/exceptions
System Designer, Complete Automatic UVM verification Platform Dec.2015
 Built a complete UVM structure tree, including base, environment, agent (driver, monitor,
sequence),scoreboard,reference model and sequencer.
 Used factory mechanism to achieve automatic verification
 Multiple sequences can be initiated to inject different kinds of transaction Utilized serial
System Designer, Verification Platform for 2x2 Ethernet Switch March.2016
 Designed a simple 2x2 Ethernet switch as DUT as well as its test bench module
 Constructed all modules, including DUT and test bench, in System Verilog
 Built verification platform, consisted by generator, driver, monitor and checker
 Operated the platform to generate constrained random data packet as input to DUT
System Designer, Implement of RS232 UART communication module on FPGA Mar.2016
 Separated the whole systeminto three parts: uart_txd, uart_rxd and speed_select
 Constructed three submodules with Verilog and instanced in a top module
 Synthesis and download the program into Altera Cyclone VI FPGA
 Utilized serial port monitor assistant to monitor data transferring between PC and FPGA
Jiangnan University Dec.2013-May.2014
System Designer, Research of size measurement based on linear CCD
 Architected digital logic circuits on Altera CPLD to generate CCD driving wave
 Layout schematic and PCB for interfacing CCD and 1GHZ A/D and FIFO as well as
CPLD, MCU and peripheral sockets
 Realized program of C8051 to read data and communicate with PC through RS485
 Debugged whole systemto fix bug, optimized the result accuracy to ±0.2mm
Team leader, Design of Simple Digital Storage Oscilloscope Sept.2012-Sept.2013
 Selected IC devices and Designed LCD display algorithm
 Designed and layout circuit for interfacing 1GHZ A/D, FIFO, and analog signal
processing branch,MCU and peripheral sockets
 Examined display result, optimized result by revise algorithm and program
Skills Software: Altium Designer, Mat lab, Modelsim, QUARTUS, MS office, Xilinx ISE
Languages: C, C++, Verilog/VHDL, Beginner Python.
Activities National Undergraduate Electronic Design Contest Sept.2013
“TI Cup” National Undergraduate Electronic Design Contest Aug.2012