SPICE MODEL of SSM3J117TU (Standard+BDS Model) in SPICE PARK

Device Modeling Report

COMPONENTS: Power MOSFET (Model Parameter)
PART NUMBER: SSM3J117TU
MANUFACTURER: TOSHIBA
Body Diode (Model Parameter) / ESD Protection Diode

Bee Technologies Inc.

All Rights Reserved Copyright (c) Bee Technologies Inc. 2008

MOSFET MODEL

Pspice model
Model description
parameter
LEVEL
L Channel Length
W Channel Width
KP Transconductance
RS Source Ohmic Resistance
RD Ohmic Drain Resistance
VTO Zero-bias Threshold Voltage
RDS Drain-Source Shunt Resistance
TOX Gate Oxide Thickness
CGSO Zero-bias Gate-Source Capacitance
CGDO Zero-bias Gate-Drain Capacitance
CBD Zero-bias Bulk-Drain Junction Capacitance
MJ Bulk Junction Grading Coefficient
PB Bulk Junction Potential
FC Bulk Junction Forward-bias Capacitance Coefficient
RG Gate Ohmic Resistance
IS Bulk Junction Saturation Current
N Bulk Junction Emission Coefficient
RB Bulk Series Resistance
PHI Surface Inversion Potential
GAMMA Body-effect Parameter
DELTA Width effect on Threshold Voltage
ETA Static Feedback on Threshold Voltage
THETA Modility Modulation
KAPPA Saturation Field Factor
VMAX Maximum Drift Velocity of Carriers
XJ Metallurgical Junction Depth
UO Surface Mobility


Transconductance Characteristic

Circuit Simulation Result

Measurement
Simulation

3
gfs

2

1

0
0.0 0.2 0.4 0.6 0.8 1.0
- ID : Drain Current A

Comparison table

gfs
-Id(A) Error(%)
Measurement Simulation
0.001 0.062 0.063 1.613
0.002 0.098 0.100 2.041
0.005 0.148 0.152 2.703
0.010 0.220 0.227 3.182
0.020 0.400 0.408 2.000
0.050 0.470 0.485 3.191
0.100 0.725 0.750 3.448
0.200 1.020 1.050 2.941
0.500 1.460 1.475 1.027
1.000 1.940 1.969 1.495


Vgs-Id Characteristic

Circuit Simulation result

-10A

-1.0mA
0V -1.0V -2.0V -3.0V -4.0V
I(V3)
V_V1

Evaluation circuit

V3

0Vdc

U1
SSM3J117TU V2

-3

V1

-3

0


Comparison Graph


10.00
Measurement
Simulation

1.00
- ID : Drain Current A

0.10

0.01

0.00
0.0 1.0 2.0 3.0 4.0
- VGS : Gate to Source Voltage V

Simulation Result

-VGS(V)
-ID(A) Error (%)
0.001 1.620 1.634 0.864
0.002 1.650 1.646 -0.242
0.005 1.670 1.669 -0.060
0.010 1.710 1.696 -0.819
0.020 1.750 1.734 -0.914
0.050 1.810 1.807 -0.166
0.100 1.885 1.892 0.371
0.200 2.005 2.007 0.100
0.500 2.250 2.246 -0.178
1.000 2.450 2.509 2.408


Rds(on) Characteristic


-1.0A

-0.5A

0A
0V -50mV -100mV -150mV
I(VD_Sense)
V_VDS

Evaluation circuit

VD_Sense

0Vdc

U1
SSM3J117TU

VDS
10Vdc
VGS

-10Vdc

0

Simulation Result

ID=-1A, VGS=-10V Measurement Simulation Error (%)
R DS (on) () 0.080 0.080 0.000


Gate Charge Characteristic

-20V

-18V

-16V

-14V

-12V

-10V

-8V

-6V

-4V

-2V

0V
0 2n 4n 6n 8n 10n 12n 14n 16n 18n 20n
V(W1:4)
Time*1mA

Evaluation circuit

ION = 0uA
IOFF = 1mA
W
- U1
+ SSM3J117TU
W1 D2 I2
I1 = 0 I1 Dbreak 2
I2 = 1m
TD = 0
TR = 10n V1
TF = 10n
PW = 600u
PER = 1000u -20

0

Simulation Result

VDD=-20V,ID=-2A
Measurement Simulation Error (%)
,VGS=-10V
Qgs(nc) 1.680 1.680 0.000
Qgd(nc) 1.680 1.683 0.179
Qg(nc) 10.000 9.729 -2.710


Capacitance Characteristic

Measurement
Simulation

Simulation Result

Cbd(pF)
VDS(V) Error(%)
0.100 152.000 152.500 0.329
0.200 145.000 143.000 -1.379
0.500 125.000 125.000 0.000
1.000 105.000 106.000 0.952
2.000 85.000 85.000 0.000
5.000 60.000 60.500 0.833
10.000 44.000 45.000 2.273
20.000 35.000 35.000 0.000


Switching Time Characteristic


-20V

-16V

-12V

-8V

-4V

0V
1.6us 1.8us 2.0us 2.2us 2.4us 2.6us
V(L1:2)*3.75 V(R2:2)
Time

Evaluation circuit

R2
L2 15

50nH

U1
R3 L1 SSM3J117TU

PER = 200u
PW = 10u 10 30nH V1
TF = 1n -15Vdc
TR = 1n R1
TD = 2u
V2 = 8 V2 10

V1 = 0

0

Simulation Result

ID=-1A, VDD=-15V
Measurement Simulation Error(%)
VGS=-4V
Ton(ns) 16.000 16.397 2.481


Output Characteristic


-5.0A
-10V -6 V

-4 V
-4.0A

-3.6 V
-3.0A

-2.0A VGS= -3.3V
V

-1.0A

0A
0V -0.2V -0.4V -0.6V -0.8V -1.0V
I(V3)
V_V2

Evaluation circuit

V3

0Vdc

U1
SSM3J117TU

V2

-0.5
V1

-4

0


BODY DIODE SPICE MODEL
Forward Current Characteristic


10A

1.0A

100mA

10mA

1.0mA
0V 0.2V 0.4V 0.6V 0.8V 1.0V 1.2V
I(VD_Sense)
V_VDS

Evaluation Circuit

VD_Sense

0Vdc

U1
SSM3J117TU
VDS
10Vdc

0


Comparison Graph


1.00
Measurement
Simulation
Drain reverse current IDR(A)

0.10

0.01
0 0.2 0.4 0.6 0.8 1 1.2

Drain - Source voltage VDS(V)

Simulation Result

VDS(V) VDS(V)
-IDR(A) %Error
0.001 0.530 0.527 -0.566
0.002 0.545 0.548 0.550
0.005 0.575 0.576 0.174
0.010 0.600 0.598 -0.333
0.020 0.620 0.619 -0.161
0.050 0.650 0.649 -0.154
0.100 0.670 0.672 0.299
0.200 0.700 0.698 -0.286
0.500 0.740 0.742 0.270
1.000 0.785 0.785 0.000


Reverse Recovery Characteristic


400mA

300mA

200mA

100mA

-0mA

-100mA

-200mA

-300mA

-400mA
0.94us 0.98us 1.02us 1.06us 1.10us 1.14us
I(R1)
Time

Evaluation Circuit

R1

50

V1 = -9.4v V1
V2 = 10.6v U1
TD = 15n SSM3J117TU
TR = 1ns
TF = 8ns
PW = 1us
PER = 100us

0

Compare Measurement vs. Simulation

Measurement Simulation Error (%)
Trj(ns) 9.200 9.300 1.087


Reverse Recovery Characteristic Reference

Trj= 9.2 (ns)
Trb= 9.6 (ns)
Conditions:Ifwd=lrev=0.2(A),Rl=50

Example

Relation between trj and trb


ESD PROTECTION DIODE SPICE MODEL
Zener Voltage Characteristic


10mA

9mA

8mA

7mA

6mA

5mA

4mA

3mA

2mA

1mA

0A
0V 5V 10V 15V 20V 25V 30V 35V 40V 45V 50V
I(R1)
V_V1

Evaluation Circuit

R1

0.01m

V1
0Vdc U1
SSM3J117TU

R2

100MEG

0


Zener Voltage Characteristic Reference


SPICE MODEL of SSM3J117TU (Standard+BDS Model) in SPICE PARK

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