The reasons for the dominant use of CMOS Technology in the fabrication of VLSI chips are reliability, low power consumption, considerably low cost and most importantly scalability

1. Sequential Logic
Handouts: Lecture Slides
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 1

2. Something We Can’t Build (Yet)
What if youweregiventhefollowingdesignspecification:
When the button is pushed:
1) Turn on the light if
it is off
2) Turn off the light if
it is on
The light should change
state within a second
of the button press
button light
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 2
What makesthis circuitsodifferent
fromthose we’vediscussedbefore?
1. “State”–i.e.thecircuithasmemory
2. Theoutput waschangedbyainput
“event”(pushingabutton) rather
than aninput“value”

3. Digital State
One model of what we’d like to build
Combinationa
l Logic
Current
State
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 3
New
State
Input
Plan:BuildaSequentialCircuitwithstored digitalSTA
TE–
•Memorystores CURRENTstate, producedat output
•CombinationalLogiccomputes
•NEXTstate(from input,current state)
•OUTPUTbit (from input,currentstate)
•State changesonLOADcontrolinput
Output
Memor
y
Device
LOAD

4. 6.004 –Fall2002 9/24/02 L06 – SequentialLogic 4
Needed: Storage
Combinationallogicisstateless:
validoutputsalwaysreflectcurrentinputs.
Tobuilddeviceswithstate, weneedcomponentswhichstore
information(e.g.,state) forsubsequentaccess.
ROMs(andother combinationallogic)store information“wiredin”totheir
truth table
Read/Writememoryelementsarerequiredto builddevicescapableof
changingtheircontents.
Howcanwestore – andsubsequentlyaccess--abit?
• Mechanics:holesincards/tapes
• Optics: Film,CDs,DVDs,…
• Magneticmaterials
• Delaylines;moonbounce
• Stored charge

5. Storage: Using Capacitors
We’vechosento encodeinformationusingvoltagesandweknow
from6.002 that wecan“store”avoltageas chargeona
capacitor:
Pros:
compact– low
cost/bit (onBIG
memories)
Cons:
complexinterface
stable? (noise,…)
itleaks! refresh
N-channelfet serves
asaccessswitch VREF
Towrite:
Drive bit line, turn onaccess fet,
force storage cap to new voltage
Toread:
precharge bit line, turn on access fet,
detect (small)changeinbitlinevoltage
wordline
Bit
line
Supposewerefresh
CONTINUOUSL
Y?
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 6

6. Storage: Using Feedback
VIN
VOUT
IDEA:usepositivefeedbacktomaintainstorage indefinitely.
Ourlogicgatesarebuiltto restoremarginalsignallevels,so
noiseshouldn’tbeaproblem!
Result: abistable
storageelement
Feedbackconstraint:
VIN=VOUT
VTCfor
inverterpair
VIN
VOUT Threesolutions:
two end-pointsare
stable
middlepoint isunstable
Notaffected
bynoise
We’llget backtothis!
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 6

7. Y
S
B
Settable Storage Element
It’s easyto buildasettable storageelement(calledalatch)
usingalenientMUX:
0
1
G D QIN QOUT
0 -- 0 0
0 -- 1 1
1 0 -- 0
1 1 -- 1
“state” signal
appearsasboth
inputandoutput
QfollowsD
Qstable
A
D
G
Q
Here’safeedbackpath,
soit’s nolongera
combinationalcircuit.
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 7

8. New Device: D Latch
D Q
G
D
G
Q
TPD
V1 V2
V1 V2
TPD
G=1:
QfollowsD
G=0:
Qholds
G=1:QFollowsD,independentlyofQ’
G=0:QHoldsstable Q’,independently
ofD
Y
0
1
A
D
G
Q
Q’
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 8
BUT…AchangeinDorG
contaminatesQ,henceQ’
…howcanthispossibly
work?

9. A Plea for Lenience…
Y
0
1
A
D
G
Q
D
G
Q
V1 V2
V1 V2
TPD TPD
Doeslenienceguaranteea
workinglatch?
AssumeLENIENTMux,propagation
delayofTPD
Thenoutput validwhen
• G=1, Dstable forTPD,
independentlyofQ’;
or
• Q’=Dstable forTPD,
independentlyofG;or
• G=0, Q’stable forTPD,
independentlyofD
Q’
What if DandG
changeat about the
sametime…
G D Q’ Q
1 0 X 0
1 1 X 1
X 0 0 0
X 1 1 1
0 X 0 0
0 X 1 1
Q(D,G)
Q(D,Q’)
Q(G,Q’)
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 9

10. DStable
… with a little discipline
Y
0
1
A
D
G
Q
Q’
ToreliablylatchV2:
• ApplyV2 toD,holdingG=1
• After TPD,V2 appearsat Q=Q’
• After anotherTPD,Q’&Dbothvalid
for TPD;willholdQ=V2independently
ofG
• Set G=0,whileQ’&DholdQ=D
• After anotherTPD,G=0 andQ’
are sufficient to holdQ=V2
independentlyofD
D
G
Q
V2
V2
TPD TPD TPD
TSETUP THOLD
DynamicDisciplineforourlatch:
TSETUP= 2TPD: interval priorto G
transition for whichDmustbe
stable &valid
THOLD= TPD:interval followingG
transition for whichDmustbe
stable &valid
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 10

11. Lets try it out!
Combinationa
l Logic
D Q
G
Current
State
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 11
New
State
Input Output
Plan:BuildaSequentialCircuitwithonebitof STATE–
•Singlelatch holdsCURRENTstate
•CombinationalLogiccomputes
•NEXTstate(from input,current state)
•OUTPUTbit (from input,currentstate)
•State changeswhenG=1 (briefly!)
Whathappens
whenG=1?

12. Combinational Cycles
Combinationa
l Logic
G
D Q
Current
State
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 12
New
State
Input Output
WhenG=1, latch isTransparent…
… providesacombinationalpathfromDto Q.
Can’tworkwithouttricky timingconstrants onG=1 pulse:
•Mustfit withincontaminationdelayoflogic
•Must accommodatelatch setup,holdtimes
WanttosignalanINSTANT,notanINTERV
AL…
1

13. Flakey Control Systems
Here’sastrategy
for saving2 bucks
onthe Sumner
Tunnel!
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 13

14. Flakey Control Systems
Here’sastrategy
for saving2 bucks
onthe Sumner
Tunnel
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 14

15. Flakey Control Systems
Here’sastrategy
for saving2 bucks
onthe Sumner
Tunnel
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 15

16. Escapement Strategy
TheSolution:
Addtwogates
andonlyopen
oneat atime.
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 16

17. Escapement Strategy
TheSolution:
Addtwogates
andonlyopen
oneat atime.
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 17

18. Escapement Strategy
TheSolution:
Addtwogates
andonlyopen
oneat atime.
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 18

19. Escapement Strategy
TheSolution:
Addtwo gates
andonlyopen
oneat atime.
(Psst… Don’t
tellMassport)
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 19

20. Escapement Strategy
TheSolution:
Addtwo gates
andonlyopen
oneat atime.
(Psst… Don’t
tellMassport)
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 20

21. Escapement Strategy
TheSolution:
Addtwo gates
andonlyopen
oneat atime.
(Psst… Don’t
tellMassport)
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 21

22. Escapement Strategy
TheSolution:
Addtwo gates
andonlyopen
oneat atime.
(Psst… Don’t
tellMassport)
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 22

23. Escapement Strategy
TheSolution:
Addtwogates
andonlyopen
oneat atime.
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 23

24. Escapement Strategy
TheSolution:
Addtwogates
andonlyopen
oneat atime.
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 24

25. Escapement Strategy
TheSolution:
Addtwo gates
andonlyopen
oneat atime.
(Psst… Don’t
tellMassport)
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 25

26. Escapement Strategy
TheSolution:
Addtwo gates
andonlyopen
oneat atime.
(Psst… Don’t
tellMassport)
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 26

27. Escapement Strategy
TheSolution:
Addtwo gates
andonlyopen
oneat atime.
(Psst… Don’t
tellMassport)
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 27

28. Escapement Strategy
TheSolution:
Addtwo gates
andonlyopen
oneat atime.
(Psst… Don’t
tellMassport)
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 28

29. Escapement Strategy
TheSolution:
Addtwogates
andonlyopen
oneat atime.
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 29

30. Escapement Strategy
TheSolution:
Addtwogates
andonlyopen
oneat atime.
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 30

31. Escapement Strategy
TheSolution:
Addtwo gates
andonlyopen
oneat atime.
(Psst… Don’t
tellMassport)
KEY:Atnotime is there anopenpath
throughbothgates…
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 31

32. Edge-triggered Flip Flop
D Q
slave
G
G
Q D D Q Q
CLK
CLK
master
Observations:
onlyonelatch “transparent” at any
time:
master closedwhenslaveisopen
slaveclosedwhenmaster isopen
 nocombinationalpaththroughflip flop
Qonlychangesshortly after 0 1
transition of CLK,soflip flopappears
tobe“triggered” byrisingedgeof CLK
Thegate of this
latch is openwhen
the clockislow
D D Q
Thegate of this
latch is openwhen
the clockishigh
0
11
D 0
S
G
Q
(the feedbackpathinoneofthemasterorslavelatchesisalwaysactive)
Transitionsmark
instants, notintervals
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 32

33. Flip Flop Waveforms
D Q
slave
G
G
D D Q Q
D D Q
master
Q
CLK
CLK
D
CLK
Q
masterclosed
slaveopen
slaveclosed
masteropen
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 33

34. Um, about that hold time…
G
D D Q
master
D Q
slave
G
Q
CLK
ConsiderHOLDTIMErequirement forslave:
• Negative(1 0) clocktransition slavefreezesdata:
• SHOULDbenooutputglitch,sincemasterheldconstantdata;BUT
• master output contaminatedbychangeinGinput!
• HOLDTIMEof slavenot met, UNLESSweassume
sufficient contaminationdelayinthepathto its Dinput!
AccumulatedtCD thruinverter,G Qpathofmastermustcover
slavetHOLD for this designtowork!
Themaster’scontamination
delaymustmeet the hold
time of theslave
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 34

35. Flip Flop Timing - I
CLK
D
Q
D D Q Q
CLK
<tPD
>tCD
tPD: maximumpropagationdelay,CLKQ
tCD: minimumcontaminationdelay,CLKQ
>tSETUP
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 35
tSETUP: setuptime
guaranteethatDhaspropagatedthroughfeedbackpathbeforemastercloses
tHOLD: holdtime
guaranteemasterisclosedanddataisstablebeforeallowingDtochange
>tHOLD

36. Single-clock Synchronous Circuits
We’lluseFlipFlopsandRegisters–groupsofFFssharingaclock
input–inahighlyconstrainedwayto builddigitialsystems:
Single-clockSynchronousDiscipline
•Nocombinationalcycles
• Singleclocksignalsharedamong
allclockeddevices
• Onlycareaboutvalueofcombinational
circuits just beforerisingedgeof
clock
• Periodgreater thanevery
combinationaldelay
• Changesavedstate afternoise-
inducinglogictransitions have
stopped!
Doesthat
symbol
register?
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 36

37. Flip Flop Timing - II
CLK
t1
t1 =tCD,reg1 +tCD,1 >tHOLD,reg2
t2 =tPD,reg1 +tPD,1 <tCLK - tSETUP,reg2
1
D Q
reg1
D Q
reg2
CLK
Questionsfor register-baseddesigns:
howmuchtime for useful
work (i.e.for combinational
logic delay)?
doesit helpto guaranteea
minimumtCD? How‘bout
designingregisters sothat
tCD,reg > tHOLD,reg?
whathappensif CLK
signal doesn’tarriveat
the two registers at
exactly the sametime (a
phenomenon knownas
“clockskew”)?
t2
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 37

38. Model: Discrete Time
Active ClockEdgespunctuate time---
• Discrete Clockperiods
• Discrete StateVariables
• Discrete specifications(simplerules–egtables–relating
outputsto inputs,state variables)
• ABSTRACTION:FiniteStateMachines(next lecture!)
Combinationa
l Logic
Current
State
New
State
Input Output
Memor
y
Device
Clock
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 38

39. Sequential Circuit Timing
Questions:
• Constraints onTCDfor thelogic?
• Minimumclockperiod?
• Setup, Holdtimes forInputs?
Current
State
New
State
Input Output
Clock
Combinationa
l Logic
tCD,L = ?
tPD,L = 5ns
tCD,R = 1ns
tPD,R = 3ns
tS,R = 2ns
tH,R =2ns
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 39
> 1 ns
>10 ns(TPD,R+TPD,L+ TS,R)
TS= TPD,L+TS,R
TH= TH,R-TCD,L
ThisisasimpleFiniteState Machine…moreonThursday!

40. Summary
“Sequential” Circuits (with memory):
Basicmemoryelements:
• Feedback,detailedanalysis=>
basiclevel-sensitivedevices
(eg,latch)
• 2 Latches=> Flop
• DynamicDiscipline:
constraints oninputtiming
Synchronous1-clocklogic:
• Simplerulesforsequential
circuits
• Yieldsclockedcircuit withTS,TH
constraints oninputtiming
Finite StateMachines
Thursday’sTopic!
>ts >th
D
Clk
Q
>tcd
<tpd
D Q D Q
Out
In
Clk
Combinational
logic
6.004 –Fall2002 9/24/02 L06 – SequentialLogic 40