1. System integration of Electronics Ernst Vrolijks June 2010

3. Moore’s law In 1965 Gordon Moore predicted that chip capacity would double every 18-24 months. G. Moore, ”Cramming more components onto integrated circuits”, Electronics, Vol. 38, Nb. 8 (1965) Itanium 2 (9 MB core) Itanium 2 Pentium 4 Pentium III Pentium II Pentium 486 386 286 8086 8080 8008 4004 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1960 1970 1980 1990 2000 2010 year transistors Over 40 years his prediction has been true.

5. Shrink drives cost per function and market growth Source: Gartner Dataquest, iSuppli, ASML 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 NAND cost, $ / GB NAND size, GB 0.01 0.10 1.00 10.0 100 1,000 10,000 Projected cross-over HDD - NAND, GB 60-80 GB 2-16 GB 80-150 GB 1 GB 4 GB 8 GB 10-20 GB

7. State-of-art water based immersion  =193nm, NA=1.20 45 nm L&S

8. Three options for 32 nm half-pitch Double patterning water immersion EUV sngl patterning Non-water Implication: Complexity increases

9. The EDEV Challenge ... EDEV's challenge = Fast & Predictable integration With increasing system complexity Multiple parallel developments

10. What do we do? Technology

11. Basic Principle Reticle Reticle stage Wafer Wafer stage Projection Lens

12. The ASML Product Wafer Stage (Expose) Projection Optics Wafer Stage (Measure) Illumination Optics Reticle Handler Wafer Handler User Interface Reticle Stage Measurement Systems

13. Deliverables of the Electronic Development (I) Local electronics Electronic functions in cabinets Remote Electronics Cabinets

14. Business Drivers Source: ICE Business Drivers Overlay Productivity Time To Market Critical Dimension

15. Business Drivers Business Drivers Overlay Productivity Time To Market Critical Dimension and Electronics Integration Organization Process Predictable&fast integration

16. How do we do it ? Organization/Process

17. PGP:EDEV Participation System : Subsystem: Module : Specification Design Test & Int. Specification Design Test & Int. Specification Design Test E-Architect : E-Designer : E-Integrator : PRS, SPS SDS TPS, TAR, ITP TPS, TAR, ITP EDS, HSI EPS TPS, TAR EDS EPS Feasibility System Definition Subsystem Definiton Integration Validation Realization V-Model

19. AT:12X0 body Split the machine in building blocks BB BB BB BB

20. Arrange blocks in logical, functional clusters FC Wafer Handling FC Illumination

22. Building blocks Range: 100 - 1000 Machine Functional Clusters Range: 20-40 12 NC’s Range: 50.000 – 100.000 System Breakdown based on FC’s Subsystems Range: upto 50?

23. From platforms to products Product I.A Product I.B Platform I + = = Selectable Building Blocks Products can be realized by changing only selected building blocks within a given platform Product II.A Product II.B Platform II Platform III + = = Over time building blocks evolve leading to ever increasing platform capabilities.

24. PGP:EDEV Participation System : Subsystem: Module : Specification Design Test & Int. Specification Design Test & Int. Specification Design Test E-Architect : E-Designer : E-Integrator : PRS, SPS SDS TPS, TAR, ITP TPS, TAR, ITP EDS, HSI EPS TPS, TAR EDS EPS Feasibility System Definition Subsystem Definiton Integration Validation Realization classic V-approach squeezes component level development Early start of development at all levels to meet time to market Early delivery of 1st unit for system integration, parallel maturing for volume deliveries

26. There is much Moore ...