ASML Investor day

1. Public
Martin van den Brink
President and
Chief Technology Officer
Technology
Strategy to Drive
Moore’s Law into
Next Decade

2. Public
Technology strategy
Key messages 29 Sept. 2021
Slide 2
• Holistic Lithography roadmap is driven by our unique
patterning control solutions that deliver customer value via
improved on product performance.
• ASML’s comprehensive product portfolio is aligned to our
customers’ roadmaps, delivering cost effective solutions in support
of all applications from leading edge to mature nodes
• Our next generation EUV technology, High-NA, is progressing
well and will be the engine to drive the lithography roadmap into
the next decade
• Continued execution of our strategic priorities is expected to
provide cost effective solutions for our customers, enable the
extension of the industry roadmap into the next decade, and
support our long-term sustainability commitment
• Moore’s Law is alive and well! Industry innovation
continues, fueled by system scaling, delivering highly valued
semiconductor products.
• Semiconductor system scaling enables exponential
performance improvement and energy reduction in support of
significant growth of data exchange.
• Customers’ roadmaps require continued shrink and
reduction in edge placement error to drive affordable scaling
into next decade.

3. Public
• Moore’s Law evolution
and customer roadmap
ASML’s strategic priorities

4. Public
Significant device innovation in logic ahead of us
scaling roadmap continues to 1 nm and beyond 29 Sept. 2021
Slide 4
Source: IMEC, Sri Samavedam, “Future logic scaling: Towards atomic channels and deconstructed chips”, IEDM, December 2020.
FinFET
5T
Nanosheets, BPR
5T
Forksheets, VHV std cell arch.
<5T
CFET, BEOL w/airgaps
4T
2D atomic channels
<4T
Buried power rail (BPR) Nanosheets Forksheets Metal etch w/ airgaps Metal etch w/ airgaps
VHV: Vertical-Horizontal-Vertical
PP: Poly Pitch (nm)
MP: dense metal pitch (nm)
CFET: Complementary FET
BPR
BPR
3 nm
PP: 44-48, MP: 21-24
2 nm
PP: 40-44, MP: 18-21
1,5 nm
PP: 40-44, MP: 18-21
1 nm and beyond
PP: 38-42, MP: 15-18

5. Public
Innovation is not limited to device level
TSMC’s system roadmap to >300 B transistors 29 Sept. 2021
Slide 5
Cu/LowK
SiGe
Immersion
HKMG
Co Capliner
Low-R Barrier
ELK
2P2E
3D FinFET
Low damage/hardening low-k & novel Cu fill
Self-aligned line w/ flexible space
Metal oxide ESL
EUV
New channel materials
> 300 B
> 50 B
transistors
transistors
A few transistors
200 MOS transistors
7B
transistors
15B
transistors
CoWos
InFo
Source: Mark Liu, TSMC, “Unleash the future of innovation” ISSCC, Feb 15, 2021
150B
transistors
CoWoS: Chip on Wafer on Substrate
FPGA: Field Programmable Grid Array
TSMC - SoIC™️
HBM: 3D High Speed Memory
InFo: Integrated Fan-Out
RDL: Re Distribution Layer
SoIC: System on Integrated Chips
WoW: Wafer on Wafer
CoW: Chip on Wafer
SOC: System on Chip

6. Public
Innovation is not limited to device level
TSMC’s system roadmap to >300 B transistors 29 Sept. 2021
Slide 6
Source: Mark Liu, TSMC, “Unleash the future of innovation” ISSCC, Feb 15, 2021
A few transistors
200 MOS transistors
7B
transistors
15B
transistors
> 50 B
transistors
150B
transistors
> 300 B
transistors
Cu/LowK
SiGe
Immersion
HKMG
Co Capliner
Low-R Barrier
ELK
2P2E
3D FinFET
Metal oxide ESL
EUV
Device scaling (Including foundry supply chain)
Circuit scaling (Including foundry customers)
Dimensional scaling (Including litho supply chain)
Architectural scaling by foundry customers
Low damage/hardening low-k & novel Cu fill
Self-aligned line w/ flexible space
New channel materials
CoWos
InFo
TSMC - SoIC™️
Chip level towards
system level
CoWoS: Chip on Wafer on Substrate
FPGA: Field Programmable Grid Array
HBM: 3D High Speed Memory
InFo: Integrated Fan-Out
RDL: Re Distribution Layer
SoIC: System on Integrated Chips
WoW: Wafer on Wafer
CoW: Chip on Wafer
SOC: System on Chip

7. Public
Moore’s Law evolution: the next decade
Traditional scaling metrics like clock frequency have been saturated since 2005 29 Sept. 2021
Slide 7
1970 1980 1990 2000 2010 2020 2030
Clock Frequency1
[MHz]
Public data Customer
projection
Speculation
Dennard
scaling
Post Dennard
scaling
Source: ¹Karl Rupp as published by: Shekar Bokar, QUALCOMM, “Future of computing in the so-called post Moore’s Law era”, International conference
for high performance computing, networking storage and analysis, November 18, 2020.
1018
1016
1014
1012
1010
108
1
1020
106
104
102

8. Public
Moore’s Law evolution: the next decade
Slide 8
29 Sept. 2021
1970 1980 1990 2000 2010 2020 2030
Device and layout
optimization Litho density2
(Contact Poly Pitch*Metal Pitch)-1
[109/mm2]
Transistor density2
[#/mm2]
Clock Frequency1
[MHz]
Public data Customer
projection
Speculation
Dennard
scaling
Post Dennard
scaling
Scaling metric of transistor and litho density continues in this decade
Sources: ¹Karl Rupp 2ASML data and projection using Rupp
1018
1016
1014
1012
1010
108
1
1020
106
104
102

9. Public
Moore’s Law evolution: the next decade
Slide 9
29 Sept. 2021
1970 1980 1990 2000 2010 2020 2030
Device and layout
optimization Litho density2
(Contact Poly Pitch*Metal Pitch)-1
[109/mm2]
Transistor density2
[#/mm2]
Clock Frequency1
[MHz]
Public data Customer
projection
Speculation
Dennard
scaling
Post Dennard
scaling
A system metric measuring energy and time efficiency combined
1018
1016
1014
1012
1010
108
1
1020
106
104
102
1Source: Robert H. Dennard et al. “Designof ionimplantedMOSFET’swith very smallphysicaldimensions”,IEEEJournal of solid-statecircuits,vol SC9, October1973, pp. 256-268.
• Energy-Efficient Performance for systems and devices defined as
• If applied per single device:
EEP = fc/e
fc = clock frequency [s-1]
e = the transistor switch energy [J]
• Using the Dennard¹ scaling model, when the dimension scales with k-1, frequency with k,
area with k-² and power density constant, it follows:
• EEP on-device level scales with k4
• If density (~k2) scales 2x every 2 year, then EEP (~k4) scales 4x every 2 year
[1/J.s]

10. Public
Moore’s law evolution: the next decade
Slide 10
29 Sept. 2021
1018
1016
1014
1012
1010
108
1970 1980 1990 2000 2010 2020 2030 2040
1
Device and layout
optimization
Device Energy Efficient Performance growth been saturated since 2005
1020
Litho density2
(Contact Poly Pitch*Metal Pitch)-1
[109/mm2]
Transistor density2
[#/mm2]
Transistor Energy
Efficient Performance2
[[1/J.s]
System Energy
Efficient Performance3
[1/J.s]
Clock Frequency1
[MHz]
Public data Customer
projection
Speculation
106
104
102
From transistor to
system scaling
Sources: ¹Karl Rupp, 2 ASML data and projection using Rupp
Dennard
scaling
Post Dennard
scaling

11. Public
Moore’s Law evolution: the next decade
Slide 11
29 Sept. 2021
1018
1016
1014
1012
1010
108
1970 1980 1990 2000 2010 2020 2030
1
Device and layout
optimization
1020
Litho density2
(Contact Poly Pitch*Metal Pitch)-1
[109/mm2]
Transistor density2
[#/mm2]
Transistor Energy
Efficient Performance2
[1/J.s]
Clock Frequency1
[MHz]
Public data Customer
projection
Speculation
106
104
102
System Energy Efficient Performance growth 3x/2yrs continues to 2040
System improvements
dominated by Transistor scaling
System
scaling
Source: TSMC, Mark Liu, “Unleash the future of innovation” ISSCC, Feb 15, 2021.

12. Public
Moore’s law evolution: the next decade
Slide 12
29 Sept. 2021
1018
1016
1014
1012
1010
108
1970 1980 1990 2000 2010 2020 2030 2040
1
Device and layout
optimization
From cost per transistor through density, to cost of time and energy through systems
1020
Litho density2
(Contact Poly Pitch*Metal Pitch)-1
[109/mm2]
Transistor density2
[#/mm2]
Transistor Energy
Efficient Performance2
[[1/J.s]
System Energy
Efficient Performance3
[1/J.s]
Clock Frequency1
[MHz]
Sources: ¹Karl Rupp, 2ASML data and projection using Rupp, 3Mark Liu, TSMC, normalized to transistor EEP in 2005.
Public data Customer
projection
Speculation
106
104
102
From transistor to
system scaling
Dennard
scaling
Post Dennard
scaling

13. Public
Moore’s law evolution: the next decade
Slide 13
29 Sept. 2021
1018
1016
1014
1012
1010
108
1970 1980 1990 2000 2010 2020 2030 2040
1
Device and layout
optimization
System scaling to satisfy the need for performance and energy consumption
1020
Litho density2
(Contact Poly Pitch*Metal Pitch)-1
[109/mm2]
Transistor density2
[#/mm2]
Transistor Energy
Efficient Performance2
[[1/J.s]
System Energy
Efficient Performance3
[1/J.s]
Clock Frequency1
[MHz]
Sources: ¹Karl Rupp, 2ASML data and projection using Rupp, 3Mark Liu, TSMC, normalized to transistor EEP in 2005.
System improvements
dominated by Transistor scaling
System
scaling
106
104
102
From transistor to
system scaling

14. Public
AMD 3D chiplet gives an 3.1-3.8 EEP improvement
By integrating memory with the processor in one package 29 Sept. 2021
Slide 14
Source: Lisa Su, AMD,
“Accelerating the ecosystem”, Computex keynote 2021, June 2 2021
3x power reduction,
4-25% speed improvement
Structural silicon
64MB L3 cache die
Direct copper-to-copper bond
Through Silicon Vias (TSVs) for
silicon-to-silicon communication
Up to 8-core “Zen 3” CCD

15. Public
Moore’s law evolution: the next decade
Slide 15
29 Sept. 2021
1018
1016
1014
1012
1010
108
1970 1980 1990 2000 2010 2020 2030 2040
1
Device and layout
optimization
System scaling to satisfy the need for performance and energy consumption
1020
Litho density2
(Contact Poly Pitch*Metal Pitch)-1
[109/mm2]
Transistor density2
[#/mm2]
Transistor Energy
Efficient Performance2
[[1/J.s]
System Energy
Efficient Performance3
[1/J.s]
Clock Frequency1
[MHz]
Sources: ¹Karl Rupp, 2ASML data and projection using Rupp, 3Mark Liu, TSMC, normalized to transistor EEP in 2005.
System improvements
dominated by Transistor scaling
System
scaling
Public data Customer
projection
Speculation
106
104
102
From transistor to
system scaling

16. Public
Litho density scaling continues in this decade
Overlay and Optical Proximity Correction errors shrink aggressively 29 Sept. 2021
Slide 16
Source: Average customer roadmap extended by ASML extrapolation May 2021, averaged with 2020 IRDS Roadmap Mustafa Badaroglu,
“IRDS IFT – More Moore Spring meeting, IEEE, April 21, 2020
2x every 6 years

17. Public
Memory roadmap for the next decade
DRAM scaling below 10 nm and NAND stacking continues > 600 layers 29 Sept. 2021
Slide 17
Source: Sk hynix, S.H.Lee, "Memory's journey towards the future ITC world, IEEE IRPS 21 March 21, 2021
DRAM
After 10 years
1y 1z 1a 1b 1c 1d 0a
< 10 nm
Challenge
Now
NAND
After 10 years
96 128 176 2xx 3xx 4xx 5xx 6xx
> 600 layers
Challenge
Now

18. Public
Projection of lithography layers by technology
29 Sept. 2021
Slide 18
Source: ASML Corporate Strategy and Marketing estimates
Logic
DRAM
3D-NAND
5 nm 3 nm 2 nm ~1.5 nm 1 nm
KrF
KrF
KrF
1A 1B 1C 0A 0B
176L 2xxL 3xxL 4xxL 5xxL
EUV – High-NA
ArFi
KrF
ArF
EUV
I-Line
2021
Layer stack
Layer stack
Layer stack
~2030

19. Public
Projection of lithography layers by technology
Lithography layer count grows, driven by DUV and EUV 29 Sept. 2021
Slide 19
Source: ASML Corporate Strategy and Marketing estimates
Logic
DRAM
3D-NAND
5 nm 3 nm 2 nm ~1.5 nm 1 nm
KrF
KrF
KrF
1A 1B 1C 0A 0B
176L 2xxL 3xxL 4xxL 5xxL
EUV – High-NA
DUV
EUV
2021
Layer stack
Layer stack
Layer stack
~2030

20. Public
Semiconductor and shrink roadmap: the next decades
29 Sept. 2021
Slide 20
Relative
manufacturing
cost
per
component
1962
1965
1970
Number of components per integrated circuit
10
1 10² 10³ 10⁴ 10⁵
10²
10³
10⁴
10⁵
1
10
In the next decade, system scaling continues to fuel the need
of advanced semiconductor solutions where litho shrink
remains key to improving circuit density and cost.
The shrink roadmap requires innovation to improve litho
performance at lower cost and higher productivity.
We continue to safeguard our approach by developing trusting
relationships with customers, with stronger holistic products.
Implications for ASML

21. Public
Moore’s Law evolution
and customer roadmap
• ASML’s strategic priorities

22. Public
ASML’s strategic priorities
29 Sept. 2021
Slide 22
▪ Build a leading position in edge placement error
▪ Enable litho simplification for future nodes
▪ Drive DUV performance and market share
▪ EUV high-volume production performance, ramp and support
▪ Enhance execution capabilities to deliver performance, cost
and robustness to customers needs
Holistic litho and
applications
High-NA
DUV
competitiveness
EUV
industrialization
Strengthen
customer trust

23. Public
Our holistic portfolio is more important than ever
29 Sept. 2021
Slide 23
Lithography scanner with
advanced control capability
Etch and
deposition tools
DUV: XT and NXT
platform
EUV: NXE platform
YieldStar E-beam
Optical proximity correction
Optical metrology
E-beam metrology
E-beam inspection
Computational lithography
and computational metrology
Process window
Prediction and
Enhancement
Process window
Control
Process window
Detection

24. Public
29 Sept. 2021
Slide 24
Applications
EUV
High-NA
DUV
Our holistic portfolio is more important than ever

25. Public
Applications: strategic directions
Deliver leading solutions for optical and e-beam metrology and inspection 29 Sept. 2021
Slide 25
Nanometers
Customer Value ASML Apps product roadmap
Capturing more wafer signatures to
improve robust on-wafer process control
Tighter process capabilities
3→6 sigma control
Capturing small defects for
yield of advanced nodes
More measurements at fixed
metrology & inspection budget
Faster time-to-solution
• Productivity
• Robust alignment schemes
• Multibeam resolution
• Computationally guided inspection
• OPC accuracy, speed and user-friendliness
• Single process control platform and analytics
• Productivity/multibeam
• E-beam platform consolidation
Good wafers
per day per
unit cost
Time to yield
• Single Beam resolution and applications
• Edge Placement Error control
• Free-Form OPC and Machine Learning
APPS

26. Public
E-beam inspection has inherent resolution advantage
Increasing throughput through increasing parallelism with multibeam 29 Sept. 2021
Slide 26
60 10 1
40 20 8 6 4 2
0.0001
0.001
0.01
0.1
1
10
100
1000
10000
100000
1000000
Defect size [nm]
Throughput
[mm²/hr]
Min defect size for
2 nm node and below
Optical
Bright Field
Inspection
Single e-beam (R&D)
Gen 3 Multibeam (~2028)
Gen 2 Multibeam (~2024)
Gen 1 Multibeam (2021)
Scanning
electron
microscope
image
Increased
throughput
enables
additional HVM
applications
APPS

27. Public
Metrology, Inspection & Patterning Control Roadmap
Product status Definition
Development
Released
Scanner
Control
Application
Metrology
Inspection
(E-Beam)
(E-Beam)
Platform
Alignment
(Imaging Optimizer)
(Overlay Optimizer)
(Optical)
2020 2021 2022 2023 2024 ≥ 2025
29 Sept. 2021
Slide 27
Increasing Scanner Actuation (DUV and EUV), EPE Control
Scanner Interfaces
and Control Software
Overlay Metrology
YieldStar
Fast Stages, Multiple Wavelengths, Computational Metrology,
In-Device Metrology
Single Beam High Resolution, Large Field of View,
Massive Metrology, EPE metrology
E-beam
Metrology
E-Beam Defect
Inspection Multi-beam, Fast and Accurate Stages, High Landing Energy, Guided Inspection
Improved Model Accuracy, Inverse OPC,
Machine and Deep Learning, Etch Models
Computational
Lithography
APPS

28. Public
NXT:2050i in volume manufacturing at customers
20% overlay improvement, faster reliability and productivity ramp-up 29 Sept. 2021
Slide 28
140
0
20
120
100
80
60
40
200
180
160
3 4 5 6 7 8 9 10 11 14 15 16 17 18 19
1 2 12 13
Weeks after completing installation
MTBI
(hours)
180 hours reliability in 13 weeks
Matched machine
overlay ~1.2 nm
Dedicated chuck
overlay ~0.8 nm
NXT:2050i
NXT:2000i
NXT:2050i
NXT:2050i
Faster ramp
1 2 3 4 5 6 7 8 9 10 11
2000
3000
14 15 16 17 18 19 20 21 22 23
12 13
0
1000
4000
5000
6000
Wafers
per
day
Days after completing installation
5,000 wafers per day in 18 days
NXT:2050i
Higher availability
DUV

29. Public
DUV: Strategic directions
Deliver leading solutions for advanced capabilities and higher productivity 29 Sept. 2021
Slide 29
Customer value ASML DUV product roadmap
Overlay Improve overlay (stability) especially
for matching to EUV
Sustainable product & service offerings
Circular
economy
Productivity and overlay performance for
specific applications
New markets
Installed base Cost-competitive service offerings for
entire product lifecycle
• NXT:2100i with optics and alignment improvements
• System Node Extension Package roadmap
• Optimize re-use to secure cost competitive supply
• Mature XT platform with application specific options
• Extend i-line product portfolio for Mature markets (>40nm)
• Fab replacement solutions
• Productivity Enhancement Packages for installed base
• Value added service solutions increasing availability at
node performance
• Immersion productivity increase through
higher scan speed
• XT to NXT transition for dry lithography
More good wafers per day at
lower cost per wafer
Productivity &
Availability
DUV

30. Public
2020 2021 2022 2023 2024 2025
DUV product portfolio to support all market segments
29 Sept. 2021
Slide 30
NXT:2100i
1.3 nm | 295wph
NXT:2050i
1.5 nm | 295wph
NXT:1980Ei
2.5 nm | 295wph
NXT:2000i
2.0 nm | 275wph
NXT:1980Di
2.5 nm | 275wph
ArF
XT:1460K
5 nm | 205wph or 7.5 nm| 228wph
1.35 NA, 38 nm
0.93 NA, 57 nm
XT:860N
7.5 nm | 260wph
XT:1060K + PEP
5 nm | 220wph
XT:860M
7 nm** | 240 - 250wph
XT:1060K
5 nm | 205wph
0.93 NA, 80 nm
0.80 NA,110 nm
i-line XT:400M
20 nm** | 250wph
XT:400L
20 nm** | 230wph
0.65 NA, 220 nm
KrF
NA, Half pitch
Wavelength
NEXT
95%
5%
27%
66%
34%
70%
30%
Product status Definition
Development
Released
Product: Matched Machine Overlay* (nm)|Throughput(wph)
ArFi
critical
mid - critical
NXT:1980Fi
2.5 nm | 330wph
NXT:1470
4 nm | 300wph
NEXT
XT
NXT
XT
NXT
NXT:870
7.5 nm | 330wph
NEXT
NEXT
**Wafer inner field
Continue innovation on advanced NXT platform for improved imaging, overlay and productivity
Leverage of advanced NXT platform for improved productivity
Migrate to advanced NXT platform for improved imaging, overlay and productivity
Productivity increases on XT platform
Productivity increases on XT platform
Migrate to advanced NXT platform for performance and productivity
Productivity increases on XT platform and migrate to next system for high volume applications
DUV

31. Public
EUV 0.33 NA adoption enabled by platform maturity in
high-volume manufacturing 29 Sept. 2021
Slide 31
Source : ASML installed base data
0
500
1000
1500
2000
2500
2018 2019 2020 2021
3000
2017
Wafers
per
day
System output
Max wafers per day (single system, weekly average)
ASML commitment is expected to bring EUV availability >95%
and increase wafer per day output >50% by 2025
Installed base system availability
4 weeks moving average (end of period)
50%
55%
60%
65%
70%
75%
80%
85%
90%
100%
95%
Availability
EUV

32. Public
EUV: strategic directions
Enabling cost-efficient scaling for advanced nodes 29 Sept. 2021
Slide 32
Nanometers
Customer value using EUV ASML EUV product improvements
Good wafers
per day per cost
Cycle time and
time to market
Patterning cost saving for critical layers vs
alternatives (3x ArFi immersion and
above)
Higher yield due to less multiple
patterning layers (up to 9%)
Reduced process complexity leading to
shorter learning cycles and faster time-to-
yield
Better device performance: simpler
design and superior electrical
performance
Productivity
Less tools needed to meet fab capacity
due to higher throughput
• Technology roadmap: per node (resolution), improve
imaging, overlay and defectivity (reticle and wafer
level)
• Productivity roadmap over time: increase Productivity
to >200wph, Availability to >97%
Improvement sub system focus:
• Source (in-line refill, higher power, high reflective mirror)
• Mirrors (mirror heating measure, cooled mirrors)
• Stages and reticle (Reticle heating, high-accurate fast
stages, pellicle durability)
• Alignment (# marks, mark size, wafer clamp robustness)
EUV

33. Public
High-NAto prevent cycle time and process complexity increase
like low NA did for immersion 29 Sept. 2021
Slide 33
Transistor density [MTr/mm²]
10 100 1,000
1
2
3
3
5
process
complexity
(a.u.)
mask
steps,
cycletime
(product
dependent)
DUV
0.33-NA insertion supports single
patterning to reduce cycle time
EUV- 0.33NA
High-NA insertion opportunities to
continue Moore’s Law without any
penalty of cycle time increase
EUV- 0.55NA
2nm
3nm
7nm 5nm
10nm
16nm
Nodes (equivelant node names) [nm]
Alternative
Proposed baseline
Alternative
Proposed baseline
Note: Assuming 1.2 days per mask layer
EUV
0.55-NA
EUV
preferred
0.33-NA
EUV
Insertion

34. Public
High-NA EUV: strategic directions
Enabling cost-efficient scaling for next generation advanced nodes 29 Sept. 2021
Slide 34
Nanometers
Customer value High-NA EUV ASML High-NA EUV product improvements
Good wafers
per day per cost
Cycle time and
time to market
15% Patterning cost saving for critical
layers vs alternatives (2x EUV)
Higher yield due to less multiple
patterning layers: 35% less mask count
below 2 nm process node
Reduced process complexity leading to
15% shorter learning cycles and faster
time-to-yield
0.55 NA enables 1.7x smaller features
and 2.9x increased density
Performance
Higher imaging contrast enables 40%
improvement in local CDU
1.4x reduced pattern variability at 1.4x
lower dose
• Technology roadmap: per node (resolution), improve
imaging, overlay and defectivity (reticle and wafer
level)
• Productivity roadmap over time: increase Productivity
Focus for a successful insertion at
our customers
• Commonality with existing EUV platform to reduce
technological risk, cost of development and switch cost
at customer
• Focus on system maturity and serviceability to support
our customer high volume performance expectation
• Early engagement with our customers to address
ecosystems readiness
EUV

35. Public
High-NA EUV is in the realization phase
On multiple ASML and supplier locations 29 Sept. 2021
Slide 35
EUV 0.55 NA optics
Toulon, France, Frame milling
Oberkochen, Germany optics system manufacturing facilities
Veldhoven,
the Netherlands,
system bottom test
Wilton, USA, system top test
EUV

36. Public
2020 2021 2022 2023 2024 ≥2025
0.33 NA, 13 nm
NXE:3800E
<1.1 nm | >195 wph / 220wph
NXE:3400C
1.5 nm | 135 wph / 145 wph
NXE:4000F
<0.8nm|>220wph
NXE:3600D
1.1 nm | 160 wph
0.55 NA, 8 nm
EXE:5200
<0.8 nm | 220 wph
NA, Half pitch
Wavelength
Early Access
ASML
Customer
R&D
Customer
HVM
Customer timing 0.55 NA
EUV 0.55 NA is expected to be added to EUV portfolio
for high volume in 2025 - 2026 while continue improving the 0.33 NA platform 29 Sept. 2021
Slide 36
EUV
wafers/hours (wph) are based on 30mJ/cm²
1) 185wph@20mJ/cm2
2) 170wph@20mJ/cm²
3) Throughput upgrade
Product: Matched Machine Overlay (nm)|Throughput(wph)
Product status Definition
Development
Released
EXE:5000
at ASML fab
EXE:5000
<1.1nm|150wph
EXE platform, EUV 0.55 NA NXE platform, EUV 0.33 NA
EUV
0.55NA enabling affordable scaling beyond current decade
0.33NA continuous imaging, overlay and productivity improvements in line
with customers advanced node HVM requirements.

37. Public
Commonality across EUV, DUV & High-NA platforms
Allows faster and more cost-effective innovation, production and maintenance 29 Sept. 2021
Slide 37
TRUST
Common Technology
used in
DUV products: NXT
NXT (248nm dry) NXT (193 nm dry) NXT (193 nm wet)
NXT:870 NXT:1470 NXT:2050i
Level sensor
Alignment Sensor
Common Technology
used in both
DUV & EUV platform
DUV EUV
Metrology
Wafer handling
Common Technology
used in both
EUV platforms
Wafer handling
Level sensor
Alignment Sensor
Metrology
Wafer stager
Reticle stager
Source
EUV EUV High-NA

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Maximizing customers’ good wafers per day
Next to minimizing system down time 29 Sept. 2021
Slide 38
Historical service model:
Maximize scanner availability
System uptime
capable of producing
wafers
System downtime
according to
standardized
definition >97%
100%
TRUST
System uptime producing
customer wafers
Process-specific inefficiencies
e.g., system down to meet
customer specs, layer
qualification after system down,
defectivity monitoring and more
System downtime serving
customer needs
> 85-90%
100%
Uptime measuring
only good wafers per day
> 90-95%
100%
New service model:
Maximize good wafers per day

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EUV is the most energy efficient solution
We expect net energy savings of more than 45% over alternative processes 29 Sept. 2021
Slide 39
Source: Sri Samavedam a.o., IMEC, “Future of logic scaling: Towards atomic channels and deconstructed chips”, IEDM, Dec 2020, extended by ASML.
Electrical power reduction
0 5 10 15 20
145 wph
(today)
100 wph
220 wph
(2025)
- 45%
DryEtch
ArFi
Metallization
EUV
Metrology
Deposition
WetEtch
Side wall Assisted
Quadrupole Patterning
Immersion to EUV 0.33 productivity [wph]
0 5 10 15 20
EUV 0.33 to EUV 0.55 at 220 wph
Lito-Etch-Litho-Etch 0.33 NA
Litho-Etch 0.55 NA
- 46%
Electrical power reduction
EUV 0.33
EUV 0.55
TRUST

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Technology strategy
Key messages 29 Sept. 2021
Slide 40
• Holistic Lithography roadmap is driven by our unique
patterning control solutions that deliver customer value via
improved on product performance.
• ASML’s comprehensive product portfolio is aligned to our
customers’ roadmaps, delivering cost effective solutions in support
of all applications from leading edge to mature nodes
• Our next generation EUV technology, High-NA, is progressing
well and will be the engine to drive the lithography roadmap into
the next decade
• Continued execution of our strategic priorities is expected to
provide cost effective solutions for our customers, enable the
extension of the industry roadmap into the next decade, and
support our long-term sustainability commitment
• Moore’s Law is alive and well! Industry innovation
continues, fueled by system scaling, delivering highly valued
semiconductor products.
• Semiconductor system scaling enables exponential
performance improvement and energy reduction in support of
significant growth of data exchange.
• Customers’ roadmaps require continued shrink and
reduction in edge placement error to drive affordable scaling
into next decade.

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Forward Looking Statements
29 Sept. 2021
Slide 41
This presentation contains statements that are forward-looking, including statements with respect to expected industry and business environment trends including
expected growth, outlook and expected financial results, including expected net sales, gross margin, R&D costs, SG&A costs and effective tax rate, annual revenue
opportunity for 2025, financial model for 2025 and assumptions and expected growth rates and drivers, expected growth including growth rates 2020-2025 and 2020-
2030, total addressable market, growth opportunities beyond 2025 and expected annual growth rate in lithography and metrology and inspection systems and expected
annual growth rate in installed base management, expected trends in addressable market up to 2030, expected trends in Logic and Memory revenue opportunities, long
term growth opportunities and outlook, expected trends in demand and demand drivers, expected benefits and performance of systems and applications, semiconductor
end market trends, expected growth in the semiconductor industry including expected demand growth and capital spend in coming years, expected wafer demand
growth and investments in wafer capacity, expected lithography market demand and growth and spend, growth opportunities and drivers, expected trends in EUV and
DUV demand, sales, outlook, roadmaps, opportunities and capacity growth and expected EUV adoption, profitability, availability, productivity and output and estimated
wafer demand and improvement in value, expected trends in the applications business, expected trends in installed base management including expected revenues
and target margins, expected trends and growth opportunity in the applications business, expectations with respect to high-NA, the expectation of increased output
capacity, plans, strategies and strategic priorities and direction, expectation to increase capacity, output and production to meet demand, the expectation that Moore's
law will continue and Moore's law evolution, product, technology and customer roadmaps, and statements and intentions with respect to capital allocation policy,
dividends and share buybacks, including the intention to continue to return significant amounts of cash to shareholders through a combination of share buybacks and
growing annualized dividends and statements with respect to ESG commitment, sustainability strategy, targets, initiatives and milestones. You can generally identify
these statements by the use of words like "may", "will", "could", "should", "project", "believe", "anticipate", "expect", "plan", "estimate", "forecast", "potential", "intend",
"continue", "target", "future", "progress", "goal" and variations of these words or comparable words. These statements are not historical facts, but rather are based on
current expectations, estimates, assumptions and projections about our business and our future financial results and readers should not place undue reliance on them.
Forward-looking statements do not guarantee future performance and involve a number of substantial known and unknown risks and uncertainties. These risks and
uncertainties include, without limitation, economic conditions; product demand and semiconductor equipment industry capacity, worldwide demand and manufacturing
capacity utilization for semiconductors, semiconductor end-market trends, the impact of general economic conditions on consumer confidence and demand for our
customers’ products, performance of our systems, the impact of the COVID-19 outbreak and measures taken to contain it on the global economy and financial markets,
as well as on ASML and its customers and suppliers, and other factors that may impact ASML’s sales and gross margin, including customer demand and ASML’s ability
to obtain supplies for its products, the success of R&D programs and technology advances and the pace of new product development and customer acceptance of and
demand for new products, production capacity and our ability to increase capacity to meet demand, the number and timing of systems ordered, shipped and recognized
in revenue, and the risk of order cancellation or push out, production capacity for our systems including the risk of delays in system production and supply chain
capacity, constraints, shortages and disruptions, trends in the semi-conductor industry, our ability to enforce patents and protect intellectual property rights and the
outcome of intellectual property disputes and litigation, availability of raw materials, critical manufacturing equipment and qualified employees and trends in labor
markets, geopolitical factors, trade environment; import/export and national security regulations and orders and their impact on us, ability to meet sustainability targets,
changes in exchange and tax rates, available liquidity and liquidity requirements, our ability to refinance our indebtedness, available cash and distributable reserves for,
and other factors impacting, dividend payments and share repurchases, results of the share repurchase programs and other risks indicated in the risk factors included in
ASML’s Annual Report on Form 20-F for the year ended December 31, 2020 and other filings with and submissions to the US Securities and Exchange Commission.
These forward-looking statements are made only as of the date of this document. We undertake no obligation to update any forward-looking statements after the date of
this report or to conform such statements to actual results or revised expectations, except as required by law.

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