Sylvain Flamant has over 30 years of experience in digital signal processing, firmware design, and algorithm development. He has expertise in DSL technologies including designing timing recovery firmware and modeling systems in Mathcad. His work experience includes senior roles at Ikanos/Qualcomm and Wiltron/Anritsu developing DSP hardware and firmware. He holds an MSEE from Stanford University and patents in peak-to-average ratio reduction and clock signal recovery.

1. Sylvain Flamant
E-mail: sflamant@gmail.com Mobile: (408) 821-6498Contact
Information
PrimarySkills
DSL firmware, DSP firmware, DSP hardware, Algorithm Design
Expertise: Digital Signal Processing modeling & simulation, PAR reduction
Languages and Tools
Programming Languages: C, TI C25/C52 Assembly
Frameworks: Matlab, Mathcad
Lab Equipment: Spectrum Analyzers, Oscilloscopes, Signal Generators, etc.
Work
Experience Senior Staff Engineer, Ikanos/Qualcomm May 2003 - Sep 2016
San Jose, CA
• System designer for Timing Recovery (G.fast). TR firmware bring-up (with two
colleagues). Clock jitter optimization for FDD project.
• G.fast model to predict performance in Mathcad. VDSL model in C.
• Bandplans optimization for VDSL (interpolation, decimation, PSD shaping, Tim-
ing Advance, digital AGC, power back-off schemes, bit-swap, disturbers, numerous
simulations).
• Common mode optimization and testing at France Telecom lab in France.
• Hardware blocks designs (sole designer)
– Large and complex PAR reduction block (block & algorithm design, bit-exact
simulation, test vectors) to reduce the peak to average ratio by 3 dB, with a
rate loss of only 2-3% in order to reduce the cost of analog front-end.
– Cheaper new implementation of programmable FIR filter, without multipliers
by coding the difference between successive taps as powers of 2s and using a
feedback loop.
– Implementation of an octogonal norm, approaching the performance of the
Euclidian norm with less complexity.
Engineer and Senior Engineer, Wiltron/Anritsu July 1984 - May 2003
Morgan Hill, CA
• System design of optical spectrum analyzer and channel drop, using a narrow-
band thin layer optical filter and small step-motor to sweep the frequencies using
a complex general deconvolution scheme to calculate the spectrum.
• Verilog design on Xilinx FPGA for SONET OC3 and OC12 drops and error testing
(2001).
• Re-designing of a board with hybrid technology that was too expensive to manu-
facture, using a C52 DSP architecture and novel DSP algorithms (ADPCM mod-
ulation/demodulation to encode the voltage and current data to a remote board
doing the remote testing of the telephone line. Use of a digital filter between Tip
and Ring to autocalibrate and balance Tip and Ring).
• Extensive DSP firmware designs using TI C25 - TI C52 assembly.

2. • Embedded Firmware.
• Hardware designer (1984-1987). Board level, PLDs, FPGA for test equipment in
telephony.
Stanford University, Palo Alto, CA 1983-1984Education
MSEE, Communications/DSP focus.
ENSMM, Besan¸con, France 1978-1981
Dipl. ing. (M.Eng.) Mechanical Engineering
Universit´e de Franche-Compt´e, Besan¸con, France 1980-1981
DEA (MAS), Optics and Signal Processing, (concurrent with above)
Lyc´ee Pierre-de-Fermat, Toulouse, France 1976-1978
Classes pr´eparatoires aux grandes e´coles
Flamant, Sylvain et al. 2015. Method and apparatus for peak-to-averagePatents
ratio reduction. U.S. Patent 9,036,730 B2, filed Jan 9, 2012, and issued May 19, 2015.
Muralidhar, Karthik. Flamant, Sylvain. 2016. Recovery of a Clock Signal. Pat. Ref.
162191IN1, filed June 2016. Patent Pending.
Other ExperienceMiscellaneous
USA Swimming Official
Lifeguard/swimming instructor. Club Med, France (1983)
Cadet officer/2nd lieutenant, French artillery. France and Germany (1981-1983)
Languages
Fluent: English, French