Powerp Sveto 2 Eng

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Powerp Sveto 2 Eng

  1. 1. <ul><li>Experiences - know how resume </li></ul>10 November 2008 Svetozar Jovanovic
  2. 2. On June 1991 I’ve got five years degree in Electronic/electrical Engineering, achieved at the University Politecnico di Milano with thesis about fault tolerant multiprocessor system, based on Motorola 68000 processors. Was a system running on a real time multitasking operating system kernel, custom written. The purpose was a digital protection relay, secure system for high voltage 50KV power transmission line protection against short circuits. Won prize &quot; ERCOLE BOTTANI &quot; on 1990 , assigned to a best specializing branch student, for the last three years studies   Foreign Languages English: fluent Italian: fluent French: basic Serbian-Croatian : middle Svetozar Jovanovic
  3. 3. <ul><li>1991- 1998 Employing start-up and competences improvement: </li></ul><ul><li>HW-SW Developer – first experiences about coordination - integration of external suppliers, working in a small-medium companies </li></ul><ul><li>1998 - 2003 Met and employed by Altran-CEC : </li></ul><ul><li>Started as a Consultant in Italy, then continued in international context as Senior Consultant in Electronics in Belgium and Netherlands - between 1999 and 2003, approaching bigger and structured companies, learning new competences in research and development </li></ul><ul><li>2003-2006 Continued collaboration with Altran-CEC : </li></ul><ul><li>System integrator and Architect as Senior Consultant in Electronics, improving skills also using learned competences achieved in the international context , developing projects oriented activities </li></ul><ul><li>2006-2008 Started as a freelance experienced consultant : </li></ul><ul><li>System integrator and Architect in Electronics, managing and building a suppliers “NET” in order to coordinate it ,to provide at final customer a “handover” complete products </li></ul>Svetozar Jovanovic
  4. 4. <ul><li>Project management / planning, team set-up, project launching, subcontractors management </li></ul><ul><li>Feasibility study and resource requirements specification </li></ul><ul><li>Product concept, HW, SW, FW and system level requirements synthesis, </li></ul><ul><li>development , functional prototyping, cost analysis </li></ul><ul><li>C and Assembly programming, UML knowledge </li></ul><ul><li>VHDL design, FPGA and PLD, simulation and synthesis </li></ul><ul><li>IP integration, SoC on programmable devices </li></ul><ul><li>Analog and digital signal conditioning, filtering and elaboration , design </li></ul><ul><li>Image processing </li></ul><ul><li>Communication systems knowledge and experience </li></ul><ul><li>Project design care (EMC, signal integrity, reliability, testing, documentation) </li></ul>Svetozar Jovanovic
  5. 5. <ul><li>CASRAM RAIL / ITALIANA ( CARONNO PERTUSELLA – VA) SINCE March 2007 until now </li></ul><ul><li>Architect-System Designer in the technology innovation program for railways company </li></ul><ul><li>Objectives in the innovation program </li></ul><ul><li>Introduction: </li></ul><ul><li>Casram is a Switzerland medium railways company, which has also a Italian branch. The Italian branch has been set as innovation “pilot”, the aim of management was to increment the “technological” weight on the market with a set of new products. This in order to help the company penetration in railways market. </li></ul><ul><li>The innovation was arranged as follows: </li></ul><ul><ul><li>“ Revamping” of some old and technology obsolete parts of electronic boards </li></ul></ul><ul><ul><li>Concept and realisation of an innovative modular manoeuvre bench for the traction vehicles </li></ul></ul><ul><ul><li>Concept and realisation of an digital speedmeter as the equipment of traction vehicles </li></ul></ul>Svetozar Jovanovic
  6. 6. <ul><li>Details: </li></ul><ul><li>The “Revamping” of obsolete boards was based on a HW porting to a current technologies. Has been used an architecture based on DSP-FPGA “tandem” which has several advantages, some of them are: </li></ul><ul><li>Powerful and “cheap” (today) FW/SW platform </li></ul><ul><li>Integration of all discrete logic devices in a FPGA, included custom timers, monostables, glue logic, extra SRAM, dual port RAM </li></ul><ul><li>Capability of mutual-watchdog mechanism between FPGA and DSP, which gives high reliability, because the FPGA is continuously controlling if the other is alive or in crash, in the case of crash the FPGA resets the DSP autonomously, keeping the vital outputs alive until DSP restart to do it. </li></ul><ul><li>The same approach was used for the speedmeter (candidate to be a SIL2 class). </li></ul><ul><li>For the modular maneuver bench, one of the innovative aspects is that all the “control points” has its own electronic module, with its I/O to the destinations, and all the single modules are interfaced to each other trough redundant CAN B bus. This is simplifying enormously the cabling which stands in the traction vehicle harness. </li></ul><ul><li>Another aspect is that all the modules itself are doubled, and during the operations each one is controlling the vitality of the his twin. Both are driving and acquiring the I/O, so in the case of the failure of one, his twin still keep the job alive. </li></ul>CASRAM ITALIANA / RAIL Svetozar Jovanovic
  7. 7. CASRAM ITALIANA / RAIL Here follows the image of digital speedmater: Svetozar Jovanovic
  8. 8. CASRAM ITALIANA / RAIL Here follows the image of maneuovre integrated bench: Svetozar Jovanovic
  9. 9. PHILIPS SOUND & VISION (Belgium) in ITCL division (International technology centre of Leuven, February 1999 until October 2000) HW Senior Consultant-Architect in consumer electronics for a SSA (Solid state Audio) project Role, objectives, summary: SSA MP3 Architecture build-up, market inspection for a system components. Design of developing/debug/test system platform for a SSA ASIC, based on Arm 720 RISC CPU, and fixed point DSP (for confidentiality reasons the name is unknown), integrated together on AMBA bus structure. Power consumption (hall effect sensors on PCB traces current) evaluation, benchmarking of different algorithms . Project responsible for developing and debug/test branch, in team with Philips Semiconductors. Plan and organise and specs for integration activity in team Subcontractors co-ordination. Svetozar Jovanovic
  10. 10. <ul><li>Project Environment </li></ul><ul><li>Final objectives achieved through regular Team meetings, conference calls with Philips Semiconductors, missions in place, in order to keep in track plan objectives and real status of Project advancement. </li></ul><ul><li>Finalising board modular platform for operating application FW (Arm 720 and DSP) demo about decoding MP3/AAC sound using as core interface a FPGA within a complete IC/ASIC emulation AMBA BUS, so AHB, APB, ASB. </li></ul><ul><li>This before tape-out of IC/ ASIC. PLD/FPGA logic specs. </li></ul><ul><li>Summary: </li></ul><ul><li>Analogic design for audio signal treatment </li></ul><ul><li>Filters synthesis: </li></ul><ul><li>Antialias on ADC inputs </li></ul><ul><li>Butterworth filters for output signal conditioning (pass-band ripple close to zero) </li></ul><ul><li>C, C++, Assembly code developing Arm environment </li></ul><ul><li>Altera tools for VHDL </li></ul><ul><li>ViewLogic tools for Schematic entry and layout </li></ul><ul><li>VHDL design for ASIC Arm and AMBA blocks / wrappers emulation </li></ul><ul><li>Integration of VHDL libraries for standard blocks (UART, USB etc.) </li></ul>PHILIPS SOUND & VISION Svetozar Jovanovic
  11. 11. Block Schematics SSA LFBGA208 Socket POWER JTAG/TCB USB PPI IIC CD Block AD/DA/RC GPIO UART IIS/SPDIF LCD MCI SM Tuner RD24K FLASH SDRAM SRAM Hardware Interface Optional Hardware Interface Optional Plug In Module REAL24 SAA7750 1V8 2V5 8V 5V 3V3 PHILIPS SOUND & VISION Here follows the Solid state audio block diagram Svetozar Jovanovic
  12. 12. MAGNETI MARELLI (ITA, 1998- 1999) AUTOMOTIVE HW/System Senior Consultant in automotive for multifunctional car INFOCENTER, Lybra project: Role summary, objectives Development and design Graphic/control board 32 bit MIPS RISC processor based, for colour TFT 320 x 240 display imaging/messaging (up to 16 bit colour resolution), and interfaced with other car system components like navigation system, radio and car serial control link. Thermal evaluations, mixed switching/linear power supply architecture, improving power consumption. Electronic component selection and validation, and related problems (multiple sourcing, and replacing, cost, component life and availability) Preventive PCB layout architecture evaluation, and placement synthesis to obtain robust HW base from EMC and functional feasibility point of view, agreeing to mechanical/dimensional constraints. Final HW architecture synthesis, accordingly to functional requirements and peripheral system constraint, and also with ”open” architecture, to minimise future revising impact. HW/FW prototype start-up and low level FW/HW debug Project Environment summary Cadence tools for schematic entry and PCB layout, thermal simulation Compatibility to automotive thermal, electric norms, EMC and testing. Svetozar Jovanovic
  13. 13. MAGNETI MARELLI Car infocenter for LYBRA image: Svetozar Jovanovic
  14. 14. SOME OTHER CONSULTANCY EXPERIENCES: ALSTOM RAILWAYS ( SESTO S.GIOVANNI - MILAN April 2005 – January 2007 ) Architect-Designer in the embedded ETHERNET rack module for the interface with external world C.S.I.I ( MONZA) BANK SECURITY COMPANY ( December 2004 – March 2005) Architect and Senior Developer TCP/IP ETHERNET – 485 /232 bridge, integrated with a security Bank alarm system, to create a link between each agency and centralized watch place MARCONI – SELENIA, NAVY DEFENSE SYSTEM (GENOVA May 2003 – June 2004) Senior designer in the RX part of flying object, remote controlled over a unidirectional high frequency link with a TX control console on ship board (200 Km) operating range Svetozar Jovanovic
  15. 15. CONTACT INFORMATIONS: E-mail : [email_address] , [email_address] Mobile: 0039 338 239 49 93 Web-site: www.wireless-power.it Svetozar Jovanovic

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