1. Meiling
Chung
meilingchung168@gmail.com
•
(510)
366-­‐8309
SKILLS
Mentor:
Calibre
LVS/DRC,
Bump,
Antenna,
XRC,
Dummy
filled
Synopsys:
Star
RC
Cadence:
OPUS/Virtuoso
IC5,
IC6
Laker:
Laker_L4
EXPERIENCE
Senior
Layout
Designer,
VIA
Alliance
Technology,
Fremont,
CA
2013
–
Present
• Work
on
bandgap,
Regulator,
and
RTN
using
TSMC
16nm
process
Mobile
Industry
Processor
Interface
(MIPI)
IP
Technologies
used:
TSMC
28nm
6x2z
process
and
TSMC
28nm
5x2z
process
Designed
layout
of
low
power
(LP)
single
ended
transmitter
and
high
speed
(HS)
differential
transmitter,
LP
receivers,
PLL,
EDS
pads,
and
digital
circuits
Display
Port/High-­‐Definition
Multimedia
Interface
(DP/HDMI)
IP
Technologies
used:
TSMC
28nm/40nm/80nm
process
Designed
layout
for
DP/HDMI
differential
transmitters,
AUX
receivers,
PLL,
EDS
pads,
and
digital
circuits
Power
Management
IC
Technologies
used:
TSMC
0.35um
process
Worked
on
ESD
pad
ring
arrangement
for
the
bond
wiring.
Designed
the
layout
of
OpAmp,
comparator,
bandgap,
LDO,
and
digital
circuits
Power
Management
IC
Technologies
used:
TSMC
0.5um
process
Worked
on
laptop
power
management
IC
that
included
a
battery
charger
and
10
BUCKs.
Additionally
worked
on
different
OpAmps,
OSC,
and
digital
circuits
Senior
Layout
Designer,
VIA
Technology,
Fremont,
CA
2003
–
2013
USB
IP
Technologies
used:
TSMC
80nm
process
Designed
layout
of
USB
receiver,
transmitter,
PLL,
and
control
logics,
matching
and
balancing
devices
for
differential
input
receivers
SATA
IP
Technologies
used:
TSMC
80nm
process
Designed
layout
of
SATA
receiver
used
in
the
chipset
chip,
including
front
end
cells
and
control
logics
Layout
Designer,
VIA
Technology,
Fremont,
CA
2001
–
2003
GTL
PHY
Interface
Technologies
used:
TSMC
80nm
process
Designed
layout
of
digital
interface
for
communication
between
chipset
chip
and
CPU,
including
level
shifter,
clock
tree
and
DLL,
and
balanced
data
path
pipeline

2. IC
Layout
Designer,
Integrated
Circuit
Technology
Corp,
San
Jose,
CA
1991
–
2001
• Utilized
0.18um
1P5M
CMOS
technology
to
create
custom
layout
design
of
embedded
PLD
IC
Layout
Designer,
Media
Reality
Technologies
Inc,
Sunnyvale,
CA
1998
–
1999
• Utilized
0.35um
1P4M
CMOS
technology
to
create
custom
layout
design
of
LCD
OSD
chip
EDUCATION
Institute
of
Business
and
Technology,
Santa
Clara,
CA
Certificate
of
CMOS
Layout
Design,
1998
Mesa
Community
College,
Mesa,
AZ
Computer
Information
Systems
and
Accounting,
1993
Catholic
Fu-­‐Jen
University,
Taipei,
Taiwan
B.S.
in
Law,
1986