1. Curriculum Vitae
Jens Grunert
I authorise the use of my personal data in compliance with Article 13 of Legislative Decree No. 196/2003
PROFESSIONAL CAREER 2012 to present
Senior ASIC designer at STMicroelectronics, Agrate (Italy)
Duties and activities:
2015: Implementation of complex digital blocks in STM 28nm technology.
For floorplan use of SOC Encounter and INNOVUS from Cadence. For
place and route use of ICC2 from Synopsys. Development together with
Synopsys of the digital implementation flow for these blocks. Extensive
debugging of new tool features.
2014: Performance analysis of STM 14nm FDSOI technology by
implementing several blocks in SOC Encounter and ICC. First trials of
ICC2 (Synopsys, successor of ICC) using big blocks in 14nm process. Work
on FDSOI 28nm hierarchical network chip. Clock tree of toplevel using
SOC Encounter. Implementation of block using Olympus place and route
tool (Mentor Graphics).
2013: Toplevel implementation using SOC Encounter (Cadence) of 32nm
network ASIC, floorplan, partitioning and floorplan of several blocks.
Toplevel clock tree insertion using CCOPT (Cadence) based on a custom
clock structure using multiple tap points.
2012: Tapeout of 90nm design using SOC Encounter (Cadence),
implementation of very complex post mask changes. Tapeout of 2 blocks in
90nm using IC Compiler (Synopsys).
2009 to 2012
Senior ASIC designer and consultant for physical design at Pegasus
MicroDesign, Arcore (Italy)
2012: Power optimisation trials of 55nm technology for automotive
applications using SOC Encounter.
2011: Extensive technology correlation for 32nm ST process between SOC
Encounter and Primetime SI. Technology evaluation on several designs.
Physical synthesis using Design Compiler of 32nm designs.
2009 to 2010: Physical design using Sierra (Mentor Graphics), SOC
Encounter and ICC. Implementation of several blocks in 65/40/32nm
processes. Physical design tool comparisons using big 32nm block. Multi-
mode/multi-corner implementation (SOC Encounter) and static timing
analysis (Primetime dmsa) of 40nm design.
2004 to 2004
Senior ASIC designer, at MISARC, Agrate (Italy)

2. Curriculum Vitae
Jens Grunert
I authorise the use of my personal data in compliance with Article 13 of Legislative Decree No. 196/2003
Responsible for the introduction of complex digital backend flows in the
company. Work on several projects with successful tapeouts. Training of
young colleagues on the latest advanced tools and technology related issues
regarding DFT and digital backend. Participation to several software and
FPGA projects.
2008 to 2009: Consultant working for a Dublin based company. Physical
design of a multi power ASIC for multimedia applications using ICC in
TSMC 65 nanometer technology. Activity included toplevel floorplan,
implementation of timing critical blocks and assembly of the toplevel
design.
2008: Place and route, Synthesis, STA, DFT and ATPG of several blocks in
different technologies (STM BCD6, cmos65 and TSMC 65 nanometer). The
place and route was done using First Encounter and IC Compiler. Software
in C++ for viewing and post processing of physical design data based on lef
and def libraries (used in ST on several projects).
2007: Software project in C for microprocessor and PC. Synthesis, DFT
insertion and place and route of several blocks in 65nm using IC Compiler.
Power calculation and rail analysis using PrimeRail. Place and route of
several blocks using First Encounter.
2006: Backend of ASIC in 130nm. The tasks consisted of synthesis using
Design Compiler and PKS (Physical Synthesis from Cadence), clock gating,
DFT insertion and formal verification using Formality and Conformal. The
Place & Route of the design was done with Physical Compiler and First
Encounter. Trial Place & Route of a 90nm design using Magma.
2005: Advanced DFT using XDBIST covering stuck-at, at-speed, iddq and
bridging faults for complex automotive ASIC in 130nm requiring test
coverage above 99%. IDDQ vector selection with Power Fault, test pattern
generation with Tetramax, verification using VCS STILDPV, translation of
the pattern and porting to the target tester. Place & route in 90nm of a
block running at high frequency (1GHz) using Synopsys Physical Compiler
Astro and Magma flow. DFT insertion and ATPG for this block.
2004: Place & route in 180nm of large telecom ASIC using Magma flow.
Design steps included IO padring definition, static timing analysis, formal
verification, P&R and final lvs/drc. Set up backend flow based on Silicon
Ensemble for older technologies. Took part of FPGA design in VHDL.
1998 to 2004
Project leader semicustom design at STMicroelectronics, Agrate (Italy)
Main tasks were the support of ASIC customers throughout all steps from
direct customer contact, feasibility studies, synthesis, scan/BIST insertion
up to layout.

3. Curriculum Vitae
Jens Grunert
I authorise the use of my personal data in compliance with Article 13 of Legislative Decree No. 196/2003
2001 to 2003: Work on several big ASICs for telecommunication customers.
DFT insertion and ATPG vector generation. Powerfault simulation for
IDDQ pattern. Parts of synthesis and backend using Synopsys/Cadence
tools, for the latest projects Magma was used for optimization, place and
route. Writing of many utilities in C, AWK and other to support the design
flows using combinations of different tools.
2000: Participation to the preparation of a big ARM-based SOC design for
mobile applications. Together with customers and third party design house
defined the specification for this project.
Later taking part in the software team to write low-level routines in C and
assembler for accessing the modules of the chip and test them within the
ARM emulation board.
1998 to 1999: Continuing support of German projects as well as projects
from Italy. Spice simulations for special cases (high frequency clocks and
pads). Development of a glitch-free clock switching unit between low
frequency rc-oscillator and PLL for power-saving modes. Design of small
RTL blocks, translation of test-vectors using TSSI.
1997 to 1998
Digital designer and customer support at STMicroelectronics, Munich
(Germany)
Digital designer and customer support for ASICs in computer and industrial
applications for front end flow which included synthesis dft insertion and
post-layout static timing analysis. Other tasks were also support to
marketing for feasibility analysis and pricing of new projects.
1995 to 1997
Design Engineer for microcontroller for the 8051 derivatives of Siemens
at Siemens Semiconductors, Munich (Germany)
1997: VHDL implementation of timer modules of 8051 as well as external
interfaces for the USB module. Test concept for the microcontroller using
full-scan and test pattern generation for some modules.
Developed a patent for "Circuit arrangement for in-circuit emulation of a
microcontroller" which is registered in Germany and USA.
1995 to 1996: Setup of a hardware evaluation board for the C509 as well as a
needle prober for on-chip measurements. Wrote software in C and
assembler for 8051 and PC to access the micro on the board. Developed
and built an EPROM emulator for the evaluation board. Ported the layout
of the microcontroller to the E-beam device and did measurements and
CAD support for the E-beam. Made extensive analog and digital
simulations of critical parts (ADC, clock-tree) of the microcontroller.

4. Curriculum Vitae
Jens Grunert
I authorise the use of my personal data in compliance with Article 13 of Legislative Decree No. 196/2003
1995
UMIST, Manchester (UK)
Six-month final project in the Department of Electrical Engineering &
Electronics at the University of Manchester Institute of Science and
Technology. Designed, built and validated the RISC core of the PIC16C84
microcontroller using Actel FPGAs. The design was done schematically
using Mentor Graphics tools.
Another important part was the development of the microcode of the RISC
core which has been implemented in EPROM and an small assembler in
Pascal which generates the code-set for each instruction from a simple input
file. The model runs at real time (4MHz) and is used as a teaching tool for
microelectronics at UMIST.
The emulator was presented at the CEBIT in Hannover and was awarded
a prize by the VDI (Union of German Engineers).
1994
MAGNA ELECTRONICS, Hereford (UK)
Six-month project in the design department of Magna Electronics.
Designed and built a programmer forPIC16C5X microcontrollers based on
a 80C552 microcontroller. This included the design of the PCB, the
software of the programmer in assembler for the 8051 and the design of the
box. Additional responsibilities in the test department, building test
equipment for digital hardware.
1991 to 1995
FACHHOCHSCHULE TELEKOM, Leipzig (Germany)
During my studies I worked part time as a tutor at university and I was
responsible for our PCB design and manufacturing laboratory.
1994 to 1995: Tutor for the CAD and PCB laboratory. Setting up of the
laboratory which included the adjustment of different CAD packages for
PCB design (e.g. TopCad) as well as the drill-mill machine. Wrote several
instructions and teaching material for PCB design and manufacturing.
• Short introduction to the PCB design package TopCad.
• Structure and post-processing of Gerber data used for drill-mill
machines and photo plotters.
• Manual for the drill-mill machine in the laboratory.
• Manufacturing of PCBs using etch technique.
Officially supervised students during the design and manufacturing process

5. Curriculum Vitae
Jens Grunert
I authorise the use of my personal data in compliance with Article 13 of Legislative Decree No. 196/2003
of PCBs.
1993 to 1994: Tutor in the subject Fundamentals of Electrical Engineering.
Preparation of electrical engineering students for their exams by improving
their understanding of the subject.
1983 to 1989
TELEPHONE EXCHANGE, Dresden (Germany)
Telecommunications engineer in the communications department.
Preventive maintenance of the PCM and RF transmission techniques.
Extensive fault finding in transmission and switching systems. Carried out
complex measurements of transmission lines and techniques. From the
control centre, provided technical supervision of the transmission
equipment in my department.
EDUCATION 1991 to 1995
Master’s degree as a Diploma-Engineer from FH TELEKOM, Leipzig
(Germany)
The Fachhochschule Telekom is a university for applied sciences in
telecommunications and microelectronics.
Main courses included:
- 1994 to 1995: Advanced Microelectronics, Cable and Satellite
Telecommunications. Final degree project at UMIST.
- 3rd year project in 1994: Design and building of a simple speech
synthesizer using a 68000 microcontroller. The software was written
in assembler language.
- 1991 to 1994: Mathematics, Physics, Materials sciences, Computers
sciences, Analog and Digital Electronics.
1989 to 1991
High school diploma, Leipzig (Germany)
I obtained my high school diploma at the University of Leipzig for entrance
to the Fachhochschule of German TELEKOM in Leipzig
1980 to 1983
Professional training, Leipzig (Germany)

6. Curriculum Vitae
Jens Grunert
I authorise the use of my personal data in compliance with Article 13 of Legislative Decree No. 196/2003
Attained qualification as a telecommunications engineer at the Deutsche
Post, Dresden. The main subjects in the course were electronic/electro-
techniques, measurement, switching- and transmission systems and a six-
month practical training on the job.
1970 to 1980
School, Dresden (Germany)
Primary and secondary school in Dresden until the 10th class; ten subjects
equivalent to junior high school.
AWARDED
SCOLARSHIPS
COMETT for six months from the COMETT programme (an EEC
foundation) in 1994 used for my practical training in Hereford
DAAD for six months from the DAAD (Deutscher Akademischer
Austauschdienst) in 1995 used for my final project at UMIST
PROFESSIONAL
BACKGROUND
CAD Systems
Synopsys
• Design Compiler, VCS Simulator
• Chip Architect, Physical Compiler
• Tetramax, Power Fault, Formality
• Avanti-Astro, Prime Rail
• IC Compiler, IC Compiler 2
Cadence
• Ncverilog
• Soc Encounter, PKS, Conformal
• Cell3, Silicon ensemble
Other
• Mentor Olympus
• Magma
• TSSI (test pattern conversion)
• LSIM, Quicksim, Modelsim (Mentor digital simulator)
FPGA and PCB
• Design Architect (Mentor)

7. Curriculum Vitae
Jens Grunert
I authorise the use of my personal data in compliance with Article 13 of Legislative Decree No. 196/2003
• ALS synthesis tool (Actel)
• XACT (Xilinx)
• PROTEL, TopCad (PCB)
Programming Languages
C/C++ for PC as well as embedded applications with 8051, PIC and ARM
microprocessors, Pascal. Assembler for a variety of microcontroller (8051,
PIC, 68000, ARM). Several script languages.
Special Hardware knowledge
Architecture of microcontroller 8051, PIC, overview ARM, 68000.
Operating Systems
UNIX (Solaris), Linux, Windows
PUBLICATIONS Article named “In FPGA implementierter Mikrocontrollerkern” in
“Electronik Industrie” about the project at UMIST in August 1996.
LANGUAGES Mother tongue: German
Other languages: Italian and English
INFORMATION Nationality: German
Date of birth: 16 September 1963
Place of birth: Bad Gottleuba, Germany
Address:
Email:
Cell: