Timing Diagram of 8085, Instruction Cycle, Machine Cycle, T-States, Memory Read Cycle, Memory Write Cycle, I/O Read Cycle, I/O Write Cycle, Opcode Fetch Machine Cycle, Timing Diagram of MVI B, 43H, Timing Diagram of STA 526A, Timing Diagram of MOV B,M, Timing Diagram of MVI A, Timing Diagram of IN Instruction, Timing Diagram of OUT Instruction

1. Instruction cycle, Machine
cycle & T-states
1

2. Instruction cycle
• Instructions are contained in the memory and is pointed by the
program counter.
• It is first moved to the instruction register and is decoded in binary
form and stored as an instruction in the memory.
• The computer takes a certain period to complete this task i.e.,
instruction fetching, decoding and executing on the basis of clock
speed.
• Such a time period is called ‘Instruction cycle’ and consists two cycles
namely Fetch cycle and Execute cycle.
2

3. Instruction cycle
• Instruction cycle can be defined as the time taken to complete an
instruction.
• We can also say that an instruction cycle is defined as the sequence of
operations that are required by the CPU to fetch an instruction and
data from the memory and to execute it.
• The instruction cycle consists of a fetch cycle and a execute cycle.
• The sequence of operations which are required to fetch an opcode
from the memory constitute a fetch cycle.
• The necessary steps which are required to get data from the memory
and to perform the operation specified by an instruction constitute an
execute cycle.
3

4. • Instruction Cycle = Fetch Cycle + Execute Cycle
• An instruction cycle consists of one to six machine cycles
4

5. Machine Cycle
• Each READ or WRITE operations of the 8085 is referred to
as Machine Cycle.
• An 8085 instruction’s execution consists of a number of machine
cycles.
• These cycles vary from one to five (M1 to M5) depending on the
instruction.
• Each machine cycle contains a number of clock cycles (also referred
to as T-states).
5

6. • The time required to complete one operation; accessing either the
memory or I/O device.
• A machine cycle consists of three to six T-states.
6

7. T-state
• T-state may be defined as the time taken by the clock to complete one
period.
• Time corresponding to one clock period.
• It is the basic unit to calculate execution of instructions or programs in
a processor.
• A T-state is measured from the falling edge of one clock pulse to the
falling edge of the next clock pulse.
• Fetch cycle takes four t-states and execution cycle takes three t-states
7

8. T-States
Machine Cycle
Instruction Cycle
8

9. T-States, Machine and Instruction Cycle
9
Instruction Cycle
Machine Cycle
T-States
Time required to complete execution of an
instruction.
Time required by the microprocessor to complete
an operation.
Operation performed in one clock period.

10. T-States
• “T-States are defined as operation performed in one clock period.”
• These sub-divisions are internal states synchronized with system clock
& each T-state is precisely equal to one clock period.
10
CLK
Clock Period

11. Machine Cycle
• “Machine Cycle is defined as time required by the microprocessor to complete an
operation.“
• This cycle may consist 3 to 6 T-states.
• The basic microprocessor operation such as reading a byte from I/O port or
writing a byte to memory.
11
T1 T2 T3 T4 T1 T2 T3 T1 T2 T3
Opcode Fetch Memory Read
CLK
I/O Write
Machine Cycle-1 Machine Cycle-2 Machine Cycle-3
m/m Read

12. Instruction Cycle
• “Instruction Cycle is defined as time required to complete execution of
an instruction. “
• In 8085 microprocessor instruction cycle consists of 1 to 6 Machine
Cycles or 1 to 6 operations.
12
CLK

13. Timing Diagram
13

14. Timing Diagram
• Representation of Various Control signals generated during Execution
of an Instruction.
• Following Buses and Control Signals must be shown in a Timing
Diagram:
•Higher Order Address Bus.
•Lower Address/Data bus
•ALE
•RD
•WR
•IO/M’
14

15. 15
High order memory address Unspecified
Low order
M/m addr.
Opcode
CLK
A8
AD0
AD7
ALE
IO/M
RD
A15
Opcode Fetch

16. 16
High order memory address
Low order
M/m addr.
Data from memory
CLK
A8
AD0
AD7
ALE
IO/M
RD
A15
Memory read cycle
S1 S0 Mode
0 0 HLT
0 1 WRITE
1 0 READ
IO/M=0, S1=1 , S0=0
S1
S0

17. 17
High order memory address
Low order
M/m addr.
Data from
Microprocessor
CLK
A8
AD0
AD7
ALE
IO/M
WR
A15
Memory write cycle
S1 S0 Mode
0 0 HLT
0 1 WRITE
1 0 READ
IO/M=0, S1=0 , S0=1
S0
S1

18. 18
High order I/O address
Low order
I/O addr.
I/O data
CLK
A8
AD0
AD7
ALE
IOR
A15
I/O read cycle
S1 S0 Mode
0 0 HLT
0 1 WRITE
1 0 READ
IO/M=1, S1=1 , S0=0
IO/M
S1
S0

19. 19
High order I/O address
Low order
I/O addr.
Data from
Microprocessor
CLK
A8
AD0
AD7
ALE
IOW
A15
I/O write cycle
S1 S0 Mode
0 0 HLT
0 1 WRITE
1 0 READ
IO/M=1, S1=0 , S0=1
IO/M
S0
S1

20. 20
Timing Diagram : MOV B,M
T1 T2 T3 T4 T5 T6 T7
CLK
A8
AD0
AD7
ALE
IO/M
A15 High order memory
address
Unspe
cified
High order memory
address
Low order
M/m
addr.
Opcode
Low order
M/m
addr.
Data from
memory
RD
Opcode Fetch Memory Read

21. 21
Timing Diagram : MVI A, 32H
T1 T2 T3 T4 T5 T6 T7
CLK
A8
AD0
AD7
ALE
IO/M
A15 High order memory
address
Unspe
cified
High order memory
address
Low order
M/m
addr.
Opcode
Low order
M/m
addr.
Read
Immediate
RD
Opcode Fetch Memory Read

22. Calculate Execution time of MVI A,32H
Given: Clock Frequency (f) = 2 MHz
Calculation:
Step-1: T-state = clock period =
1
𝑓
=
1
2
= 0.5 sec
Step-2: Execution time for Opcode Fetch
= 4T x 0.5 = 2sec
Step-3: Execution time for Memory Read
= 3T x 0.5 = 1.5sec
Step-4: Execution time for Instruction
= (4T + 3T) x 0.5
= 7T x 0.5
= 3.5sec
22

23. Timing Diagram : IN 02H
Opcode Fetch Memory Read
T1 T2 T3 T4 T1 T2 T3 T1 T2 T3
CLK
A8
AD0
AD7
ALE
IO/M
A15
High order memory
address
High order memory
address
Unspecif
ied
Port address 02H
RD
IOR
Low
addr
02H
Low
addr
Opcode
Port
addr
Acc.
content
I/O Read
23

24. Timing Diagram : OUT 02H
Opcode Fetch Memory Read
T1 T2 T3 T4 T1 T2 T3 T1 T2 T3
CLK
A8
AD0
AD7
ALE
IO/M
A15
High order
memory address
High order
memory address
Unspecif
ied
Port address 02H
RD
IOW
Low
addr
02H
Low
addr
Opcode
Port
addr
Acc.
content
I/O Write
24

25. More Notes in with
explanation
25

26. MACHINE CYCLES OF 8085
The 8085 microprocessor has 5 basic machine cycles.
They are
1. Opcode fetch cycle (4T)
2. Memory read cycle (3 T)
3. Memory write cycle (3 T)
4. I/O read cycle (3 T)
5. I/O write cycle (3 T)

27. MACHINE CYCLES OF 8085
• The processor takes a definite time to execute the machine cycles. The
time taken by the processor to execute a machine cycle is expressed in
T-states.
• One T-state is equal to the time period of the internal clock signal of
the processor.
• The T-state starts at the falling edge of a clock.

28. OPCODE FETCH MACHINE CYCLE OF
8085

29. OPCODE FETCH MACHINE CYCLE OF
8085
• Each instruction of the processor has one byte opcode.
• The opcodes are stored in memory. So, the processor executes the opcode fetch machine
cycle to fetch the opcode from memory.
• Hence, every instruction starts with opcode fetch machine cycle.
• The time taken by the processor to execute the opcode fetch cycle is 4T.
• In this time, the first, 3 T-states are used for fetching the opcode from memory and the
remaining T-states are used for internal operations by the processor.

30. MEMORY READ MACHINE CYCLE OF
8085

31. MEMORY READ MACHINE CYCLE OF
8085
• The memory read machine cycle is executed by the processor to read a
data byte from memory.
• The processor takes 3T states to execute this cycle
• The instructions which have more than one byte word size will use the
machine cycle after the opcode fetch machine cycle.

32. MEMORY WRITE MACHINE CYCLE OF
8085

33. MEMORY WRITE MACHINE CYCLE OF
8085
• The memory write machine cycle is executed by the processor to write
a data byte in a memory location.
• The processor takes, 3T states to execute this machine cycle

34. I/O READ CYCLE OF 8085
• The I/O Read cycle is executed by the processor to read a data byte
from I/O port or from the peripheral.
• The processor takes 3T states to execute this machine cycle.
• The IN instruction uses this machine cycle during the execution.

35. I/O READ CYCLE OF 8085

36. I/O WRITE CYCLE OF 8085
• The I/O write machine cycle is executed by the processor to write a
data byte in the I/O port or to a peripheral, which is I/O, mapped in the
system.
• The processor takes, 3T states to execute this machine cycle.

37. I/O WRITE CYCLE OF 8085

38. EXAMPLE INSTRUCTION :
MVI B, 43

39. EXAMPLE INSTRUCTION :
STA 526A