Mini Project 2 - 4-to-1 Multiplexer And 1-to-4 Demultiplexer With Enable
1. EEEC6420307
Digital Circuits and SystemDesign
Faculty of Engineering and Computer Technology
Laboratory Manual
Lecturer: Ravandran Muttiah BEng (Hons) MSc MIET
Year/Semester: Year 1 / Semester 2
Academic Session: 2021/2022
The information in this documentis important and should be noted by all students undertaking the
Bachelor of Engineering (Honours) in Electrical and Electronic Engineering
Approved by Coordinator: Endorsed By Dean:
------------------------------------------ __________________
2. AIMST University Faculty of Engineering and Computer Technology
BEng (Hons) in Electrical and Electronic Engineering Digital Circuits and System Design 1
Mini Project 2 - 4-to-1 Multiplexer And 1-to-4 Demultiplexer With
Enable
Multiplexers
In general, a multiplexer is a modular device that selects one of many input lines to
appear on a single output line. A demultiplexer performs the inverse operation; it takes a
single input line and routes it to one of several output lines. A simplified diagram
illustrating the general concept of multiplexing and demultiplexing is shown in figure 1.
The rotary switch ๐๐1moves from input line ๐ด to ๐ต to ๐ถ, and so on. The rotary switch
๐๐
2 at the output of the channel is synchronised to ๐๐1 and it too moves from output
line ๐ด to ๐ต to ๐ถ, and so on. This multiplex/demultiplex configuration illustrates one
manner in which data are selected and routed. The logic configuration is shown in figure
2. Here the signal, ๐, ๐, โฆ ๐ are control signals that select which set of inputs/outputs will
be using the โsingle channelโ. The channel in this configuration could be contained
within a computer system or could be a mechanism with which the computer
communicates with the outside world.
Figure 1: K-channel multiplex/demultiplex operation.
Figure 2: Simple logic diagram of K-channel multiplex/demultiplex.
๐ดin
๐พin
๐ตin
Single
channel
๐ดout
๐พout
๐ตout
Multiplexer Demultiplexer
โฎ โฎ
๐๐1 ๐๐2
๐ดout
๐ตout
๐พout
๐ดin
๐ตin
๐พin
โฎ
๐
๐
๐
๐
๐
๐
โฎ
3. AIMST University Faculty of Engineering and Computer Technology
BEng (Hons) in Electrical and Electronic Engineering Digital Circuits and System Design 2
Multiplexer Circuit Structures
In an ๐ โ to โ 1 line multiplexer, one of the ๐ input data lines (๐ท๐โ1 ,๐ท๐โ2, โฆ, ๐ท0) is
designated for connection to the single output line (๐) by a selection code (๐๐โ1, โฆ , ๐0),
where ๐ = 2๐
. Examine figure 3, which depicts a 4 โ to โ 1 line multiplexer, with ๐ต =
๐1 and ๐ต = ๐0. The circuit will connect data line ๐ท๐ to the output ๐ when the code,
๐ = (๐ต๐ด) (1)
is applied to the selection terminals. Table 1 displays the truth table of the multiplexer.
From the truth table we may write,
๐ = (๐ต
ฬ ๐ดฬ )๐ท0 + (๐ต
ฬ ๐ด)๐ท1 + (๐ต๐ดฬ )๐ท2 + (๐ต๐ด)๐ท3 (2)
The selection code forms the min-terms of two variables, ๐ต and ๐ด. Hence, we may write,
๐ = โ ๐๐๐ท๐
3
๐=0 (3)
Figure 3: Functional diagram of 4 โ to โ 1 multiplexer.
Table 1: Truth table
๐ท0
๐ท3
๐ท1
๐ท2
๐
4 โ to โ 1
Multiplexer
๐ต ๐ด
Selection code
๐ต ๐ด ๐
0 0 ๐ท0
0 1 ๐ท1
1 0 ๐ท2
1 1 ๐ท3
4. AIMST University Faculty of Engineering and Computer Technology
BEng (Hons) in Electrical and Electronic Engineering Digital Circuits and System Design 3
Figure 4: Logic diagram of 4 โ to โ 1 multiplexer.
where the ๐๐ are the min-terms of the selection code. The logic diagram for the 4 โ to โ
1 multiplexer is shown in figure 4.
Demultiplexers
In the last section we examined a combinational logic circuit that multiplexed ๐ lines to
one line by using a selection code to specify which input line to connect to the output
line. In this section we will examine the inverse circuit, a demultiplexer. A demultiplexer
connects a single input line to one of ๐ output lines, the specific output line being
determined by an ๐ โbit selection code, where,
2๐
โฅ ๐ (4)
A functional diagram for a 1 โ to โ ๐ demultiplexer is shown in figure 5. The selection
code is used to generate a min-term of ๐ variables; that min-term then gates the input data
to the proper output terminal. See figure 6 for a specific example. This 1 โ to โ 4
demultiplexer has an enable signal (๐ธ) that controls the operation of the circuit. When ๐ธ
is 1, the circuit is operational. We may thus describe the operation of the device by,
๐๐ = (๐๐๐ท)๐ธ (5)
๐ท0
๐ท1
๐ท2
๐ต
๐ท3
๐ด
2-to-4
Decoder
๐
0 1 2 3
5. AIMST University Faculty of Engineering and Computer Technology
BEng (Hons) in Electrical and Electronic Engineering Digital Circuits and System Design 4
where ๐ท is the input signal to be distributed to the ๐ output line. Compare equation 5 to
equation 4.
Figure 5: Functional diagram of demultiplexer.
Figure 6: 1 โ to โ 4 demultiplexer with enable.
๐0
๐3
๐1
Outputs
Input 1 โ to โ ๐
Demultiplexer
1
Selection code
โฎ
2 ๐
โฏ
๐0
๐1
๐2
๐ต
๐3
๐ด
2-to-4
Decoder
๐0 ๐1 ๐2 ๐3
๐ท
๐ธ
Input
Enable
Selection code
6. AIMST University Faculty of Engineering and Computer Technology
BEng (Hons) in Electrical and Electronic Engineering Digital Circuits and System Design 5
Objectives
The objective of this experimental project is to become acquainted with the design of
multiplexer and demultiplexer. Demonstrate your ability to design and construct the
multiplexer and demultiplexer, and to view the function of the inputs and outputs
respectively.
Specification
Design a 4 โ to โ 1 multiplexer, and a 1 โ to โ 4 demultiplexer with Enable.
Report
Write a laboratory report on this project:
(1) Explain in detail about the theory of 4 โ to โ 1 multiplexer, and the 1 โ to โ 4
demultiplexer with Enable.
(2) Discuss the method of productions and fabrications of multiplexer and
demultiplexer, and comment on the test results.
(3) Prepare slides for presentation and demonstration of this project.