1. RASHMI PALAKKAL
B101 Sobha Hibiscus,
Amballipura Village, Bellandur,
Off Outer Ring Road, Bangalore-560103
Mob: 9986254719
Email ID: pallakal@rediffmail.com
CAREER OBJECTIVE
To strive for excellence and to work hard towards a challenging position, this provides the opportunity to make
a strong contribution to organizational goals through continued development of professional skills.
PROFESSIONAL SUMMARY
• 10 years of experience in SOC/FPGA design and verification.
• Working as Lead Engineer for UTC Aerospace system since 3 months.
• Worked as Engineer senior for Qualcomm India Pvt.Ltd, Bangalore for almost 3 years.
• Worked as Lead Engineer at HCL Technologies, Bangalore for over 5 years.
• Worked at ISRO Satellite Centre, Bangalore as trainee engineer for one and a half years.
PRIMARY SKILLS
• FPGA/SOC verification and validation, testing and debugging.
• FPGA implementation, Logic Synthesis.
• High-level design, Low-level design/Detailed design, RTL Coding.
• Proficient in VHDL/Verilog RTL design and simulation.
• Testbench/Testcase creation, Functional simulation & debugging.
• Experience in SOC GLS activities with SVTB and UVM Methodology.
• Was responsible for Pre and Post silicon validation activities for 4 tape out.
• Good knowledge of Xilinx/actel FPGA architectures.
• Have implemented and tested at least 3-4 simulator designs on FPGA boards.
• Very good knowledge of board interfaces like RS232, I2C .
• Experience on AHB/AMBA protocol.
• Hands on experience on EDA tools, Verdi, Modelsim, VCS, Xilinx ISE, Libero,
schematic entry ORCAD and PADS.
• Good in C and proficient in OS Windows/UNIX.
• Excellent Team player and able to work independently.
• Exposure to aerospace Hardware development life cycle and DO254B Guidelines.
• Exposure to Software Development Life Cycle and DO178B Guidelines
QUALIFICATION
Bachelor of Engineering in Electronics & Communication from East Point College of Engineering and
Technology, in the year 2005 with an aggregate of 70%.
Pre university College Education from Sacred Heart’s College, Bangalore in the year 2001.
Secondary Education from Vidyanikethan School, Bangalore in the year 1999.
ACHIEVEMENTS
Qualstar Awarded at Qualcomm for the Individual responsibility and leading the team.
Young Power House Awarded at HCL Technologies for the Individual contribution to the team.

2. PROJECT DETAILS
Projects worked at Qualcomm:
1
Project # : ISTARI (Aug 2013 to Till Date)
Description : The SOC chip MSM8996 is a high performance device consisting of 64
bit Qualcomm Processor chip, originally intended for high performance tablets, computing and
automotive applications. Comprises of Quad-core 64bit ARMv8/2MB L2/, computing
Multimedia, HSIO’s, peripherals like PCIE, UFS and SDIO.
Role:
• Lead the team for the GLS and Vector activities.
• Responsible for the Post and pre-silicon verification and GLS activities.
o GLS Data base generation and release
o Sanity test case run/debug
o Drive all identified test cases to Meet the TO goals
o CHARACTERISATION vector Generation for the chip
o ATE silicon debug.
2
Project # : GANDALF (Nov 2012 to June 2013)
Description : The chip APQ8084 is a high performance device consisting of ARM
based Processor chip, originally intended for tablets, smart phones and set top box markets.
Comprises of Quad-core Krait/2MB L2/, computing Multimedia, HSIO’s, peripherals like PCIE,
SATA, UFS and SDIO.
Role
• Lead the team for the GLS and Vector activities.
• Understanding the UVM test environment.
• Responsible for Post and pre-silicon verification and GLS activities.
o GATEID generation
o Template test case run/debug
o Release to the entire team
o Debug all identified gate sim test cases
o GLS test case modification to increase the coverage during the silicon Debug.
• Vector generation and ATE testing.
Projects worked at HCL:
1
Project # : COPS SILA FPGA for BAE (Dec 2011 to May 2012)
Description : The SILA FPGA receives three independent 29 bit serial data streams
and transmits one 29 bit data stream over three separate channels. The SILA writes any valid
received data to the external memory by performing a direct memory access (DMA). The SILA is

3. able to transmit a single stream of serial data over three independently enabled channels. The
processor writes the external memory starts and finish locations corresponding to the block of
data to be transmitted into the SILA Start and Finish Registers.
Responsible :
• Understanding requirement specification.
• Creating test bench and test cases for the Module.
• Reviewing and debugging test cases.
• Documentation involving the Design verification document.
2
Project # : TTR TrafficFPGA for RCI (Jan 2011 to Sep 2011)
Description : The FPGA receives IF data from the receiver, implements the DSP
algorithms to generate video data, decodes video data, places decoded reply data in a DPRAM
for the host processor, and generates TCAS transmissions.
Role :
• Understanding requirement specification.
• Understanding the ARINC module.
• Creating test cases for ARINC module.
• Reviewing and debugging test cases.
3
Project Name : Meggitt eVPU FPGA for Meggitt (July 2010 to Oct 2010)
Team Size : 7
Tools : Modelsim.
Description : The FPGA receives the ADC data from the peripherals and provided to
the processor module for the generation of respective displacements of the rotaryshaft unit and
also monitors the health of the sub-system.
Role:
• Requirement study and analysis.
• Test Plan and Test case development.
• Verification of RTL Code with model sim.
4
Project Name : Protocol converter for HCL (custom Board) (Dec 2009 to March 2010)
Team Size : 4
Tools : PADS.
Description : The Project involves the Interface Board design consisting of interfaces
like USB2.0, Ethernet, ARINC 429, CAN and RS485/RS232.The board shall be interfaced to the
devices which requires the data conversion compatible with the above mentioned interfaces.
The protocol converter interface board core is the backbone of the product. The LPC 2468 core
used for the design with a clock speed of 12MHz and 32.768 KHz.
Role:

4. • The Requirement capture and high level design document of the custom Board.
• The Design of Ethernet section.
5
Project Name : gTESTER Simulator for HS (April 2008 to Dec 2009)
Team Size : 3
Tools : Xilinx ISE, Logic Analyzer.
Description : The gTESTER, a generic test Equipment was developed to test Analog
and Digital boards for bench test application. The Test Equipment basically generates all the
signals that are required for Analog and High Frequency Digital Board testing such as discrete
data, Analog data, Frequency and Phase signals. The Project involved the control signal
generation for ADC and DAC chips, and Provide GUI Interface with the FPGA via RS-232
Communication Protocol. The gTESTER can be directly interfaced to the PC using the serial port.
All the Input signals to the gTESTER are controlled through Serial port (GUI) or from the Toggle
switches mounted on the Test Equipment, based on which the required control signals are
generated by FPGA using 50 MHz clock. The FPGA used was Spartan 3AN XC3S700AN.
Role:
• Requirement Specification and Design document preparation.
• Study of the Architecture of Xilinx FPGA XC3S700AN.
• Involved in requirement study, analysis and implementation.
• Design and implementation Using VHDL.
• Verification of RTL Code with modelsim and on the Starter kit FPGA.
• Hardware software integration testing with the custom board.
Projects worked at ISRO:
1
Project Name : OCM AND SCATTEROMETER SIMULATORS for ISRO (Nov 2005 to
March 2007)
Team Size : 2
Tools : Libero IDE, Logic Analyzer, Modelsim
Description : The project involved design and coding of Simulator FPGA (OCM
simulator and SCAT simulator).
Role :
• Study of the Architecture of 54SX32 and Block level Description.
• Design and implementation.
• Verification of the FPGA for the functionality.