1. Siddhartha K. Ghoshal
4030 Remington Oaks Circle
Cary, NC 27519
TEL: (919) 372-9343(H)
Email: siddhartha.ghoshal@gmail.com
Permanent Resident of USA permitted to work, OCI (can travel to India anytime)
Key Skills
• 18 years of experience in Unix Kernel, Device Drivers, Multiple CPU implementation of
algorithms, scripting, Testing and test automation
• Well versed in FC Jammer, WAN simulator, Clustered Computer architecture, FC distance
emulators, FC switch commands and automating them
• Perl, C, bash, and may other scripting and programming languages
• 5 Years of writing drivers for chipsets for high-performance Intel Pentium motherboards
• 3 Years of PCI configuration Space programming
• 19 Years of experience with PC BIOS calls
• 20 Years of Experience in assembly language programming for X86 Family
• Hardware design, implementation and testing experience with Single Board Computers and
FPGA
• 14 Years of experience in Boot Loader and Boot-level Diagnostic design and implementation
• 3 Years of experience writing Storage and networking device drivers
• Embedded Linux and Solaris 64-bit Driver development
• 4 years of Command Level utility and applications developing environment for NAS and SAN
applications
• Developed Virtual Partition Management Utility and IDE drivers for compact Flash Disks
• Experience with BIOS32 and PCI Interrupt Routing for High-performance SAN/NAS servers
Experience:
04/10 – Present
NTAP, MTS, RTP, NC (MCC QA Engineer)
• Currently focused on Comprehensive functional testing of LB.1 and leading a NB-based sub-team
• Successfully completed RRT, FST and pre-FST of MCC in Fullsteam.0
• Effectively shared test-beds and test equipment and completed tests against tight schedules
• Successfully coordinated verification of a large number of MCC related TESTME-BURTS
• Currently Triaging Longboard Rainbow tests regularly and maintaining code-line stability
• Had served as the lead for all the test efforts from SN chunk 0 through 8 and FS Integrated Chunk 1in
MCC pacing schedule
• Been with MCC design team from the very beginning, brought up DPG and x-TG teams that test
MCC
• Designed assertions and steps of Regular and Acceptance tests for DPG owned and x-TG owned MCC
features at each chunk
• Wrote and got reviewed and approved STP and TDS of MCC
• Reviewed most Arch Spec, Functional Specs and Design specs of MCC, authored by x-TG and DPG
• Reviewed PRD of MCC and formulated key test requirements and resource planning
• Advised about contingencies and mitigation
• Developed Skill set requirements, curricula and training plans of new MCC testers
• Mentored many test engineers within DPG and x-TG
• Built and helped build many test-beds at GDL and CTL, owned by DPG and x-TG
• Brought up Engineering Support teams skills about MCC
• MAXCAP MCC related test planning and coordination across x-TG and within DPG
• Helped all other test team members with test execution and test bed triage and recovery
• Reassign, verify and coordinate all TESTME verification of MCC related BURTS
• Wrote many NIRs and helped others become co-inventors
• Handled Campus MCC related test planning
• Minimized impacts caused by STF, shifting contents and acute shortage of QA resources
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2. • Did original NACL framework adaptation of MCC testing with LWG and automation leads
• Did Quality assessment of MCC code line and suggest corrective actions from time to time
• Expert of fixing test beds both about hardware issues and from side effects of testing
• Skilled user of DPG test automation, NATE, NACL and all MCC related test-ware
• Well-versed in FC analysis, Jammer usage and triaging of MCC bugs
• Developed close well-knit tiger teams of Dev and QA (most recently in interconnect area)
04/10 - 04/10 (15 days)
NTAP, MTS, RTP, NC (Help with Paloma Testing)
• Running Paloma Tests, manual and automated
• Fixing scripts
09/06 – 04/10
NTAP, MTS, RTP, NC (FMC-QA Engineer)
• Regular Release specific FMC feature tests, FFT, RRT
• OOD implementation and Special Topology Test Planning and execution
• Storage, Switch and fabric tests, Firmware validation
• 7-mode FMC MAXCAP Testing and Test planning
• PVR Release Testing
• Patch Release Testing
• Mind-tech (sub-contracting company based at Bangalore) management
• Transition to NB and Training NB-based NTAP FMC-QA engineers
03/04 – 09/06
Network Appliance Inc. Member of Technical Staff, SVL, CA (Platform Software Developer)
Embedded Linux Development for Remote LAN module service processor, Platform software design
and development in environmental sensor drivers and policy code, Rapid prototyping of
environmental monitoring software to new platform models(3 platforms till date). Tracking down
issues in Agent/I2C communications and adding resilience to applications. Evaluating firmware and
adapting applications to platform needs. Adding testability to applications by providing additional test
and debugging commands and interfaces for remote debugging. Developed test automation scripts
for file servers. Wrote extensive amounts of web documents describing software architecture of
recently completed projects as well as traditional framework of generic NetApp modules so that they
can be used bring up new employees to speed quickly. Did extensive testing of new software
developed by me and published test results on the internal web. Participated in code inspection
processes about recently completed projects and re-architected some internal modules for portability,
scalability and maintainability. Testing and test script development of Clustered SAN servers over
long distance FC links. Written a lot of documents, plans for testing and test automation
development. Driven teams of subcontractors working in India and provided technical training to
teams distributed globally. Test script development to support migration from monolithic to
segmented multitasked embedded operating systems.
05/03 – 03/04
IBM Consulting Senior Software Engineer, Austin, TX
Writing Command Level Interface for IBM’s NAS servers. Designing, developing and implementing
AIX-kernel algorithms for Snapshot management and Rollback Recovery of IBM’s JFS2 file systems.
Developing Functional Verification Tests for NAS. Experience in developing and maintaining 64-bit
file system code both at kernel and user privilege levels. Implemented snapshots on multi-node
cluster architecture. Implemented snapshot scheduling with different periodicities and other attributes.
Solved customer problems by analyzing AIX core dumps.
11/99 - 04/03
Auspex Inc Senior Software Engineer; Santa Clara, CA
- Ported Linux-like monolithic kernels to High-performance multiple CPU motherboards with
Server-works HE-SL chipsets and optimized performance by kernel-level profiling and
compacting PCI configuration spaces for storage and network cards
- Wrote drivers for JNI Fiber channel Adapters and accessed BIOS PCI IRQ data
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3. - Adapted Intel Gigabit Drivers and debugged NFS version 3 protocols on a NAS environment
- Worked closely with other engineering groups, developed standardized and exported Application
Programming Interfaces for the kernel, developed manuals and other literature
- Provided Close boot-level support for Mellanox Infiniband Host Adapter Cards
- Worked closely with Customer Service to Fix Bugs and to identify sources of problems in the field
and formulating the best approach to fix it as well as giving leads to other engineers on these
issues
4/99 - 11/99
University of Minnesota Visiting Professor, Duluth, MN
- Developed Web Robots for Scientific Information Extraction, Analysis, Classification and
Assimilation
- Used Perl5, CGI, Solaris 2.6 Kernel Calls, Linux, Apache, PHP
- Took out US Patent “A Web Robot for Scientific Document Analysis, Assimilation and
Classification “, U/M Docket #Z02040.
5/89 – 4/99
Supercomputer Education and Research Center . Indian Institute of Science, Bangalore, India
Sr. Research Scientist
Designed and built High Performance Multiple CPU distributed computers using Intel CPUs and
message passing inter-processor communication interfaces, and wrote Unix Kernels for it,
Developed PC-based FPGA testing equipment, implemented Java Virtual Machines for
Embedded Micro-controllers, Investigated numerous research projects, Guided MSEE and BSEE
student projects, served as a consultant to different departments of the Government of India in
areas of high-performance computing and VLSI design, wrote many research papers, one
textbook and many popular articles. More than 10 years of teaching and intensive course design
experience
Education
Ph. D, Indian Institute of Science (Thesis: Numerical Integration of Ordinary Differential Equations on
Multiprocessing Systems, Department: CS) , 1988, MSEE, Indian Institute of Science, 1984
BSEE, Indian Institute of Science, 1982, BS, Indian Institute of Technology, 1979
Publications: Over 20 research Publications and One Textbook in areas of parallel and distributed
computing systems and algorithms. More than 10 educational articles on computer science and VLSI
technology subjects. List will be provided on request.
Tools and Programming Languages
In-circuit Emulators for Pentium and all 80X86 CPUs, Xilinx XACT5.0 FPGA development tool, HP
logic Analyzers, V-Metro PCI bus analyzers, SCSI protocol analyzers, Infiniband Protocol Analyzers,
C, Assembly Language for Pentium Family, ksh, Perl, sed, awk, kdb, Fortran90.
Awards
Gold Medal of Institution of Engineers, Numerous Best Paper Awards in Computer Subject
Conferences
Memberships IEEE Computer Society, Program Committee of the International Society of High-
Performance Computing, Member of Advanced Computing Society
Patents P01-4113 Automatic Zoning by dynamic net-list exploration, P01-4116 Disk Unfailing by
Iterative improvement, P01-5332 Speeding up Fabric Testing by dynamic switch programming
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