Fet

Field-effect transistors
Dr.R.P.Rao
Gate
JFET
Source Drain

Dr.R.P.Rao
Gate
Source Drain
* A Field-Effect Transistor(FET) has a gate (G) terminal w hich controls the
current flow between the other two terminals, viz., source (S) and drain (D).

Dr.R.P.Rao
Gate
Source Drain
* In simple terms, a FET can be thought of as a resistance connected between S
and D, w hich is a function of the gate voltage VG .

Dr.R.P.Rao
Gate
Source Drain
* The mechanism of gate controlvaries in different types of FETs, e.g., JFET,
MESFET, MOSFET, HEMT.

Dr.R.P.Rao
Gate
Source Drain
* The mechanism of gate controlvaries in different types of FETs, e.g., JFET,
MESFET, MOSFET, HEMT.
* FETs can be used for analog and digital applications. In each case, the fact that
the gate is used to controlcurrent flow between S and D plays a crucialrole.

Junction Field-effect transistors (JFET)
Dr.R.P.Rao
3D v iew
Gate
Source Drain
Z
L′
G
p+
S D
G L
(Not drawn to scale. Typically, L≫ 2a.)
Cross−sectional v iew
G
p+
S D
G L
Simplified structure
n −Si
2a
n −Si
2a

Dr.R.P.Rao
3D v iew
* The n-type region betw een the top and bottom p+
regions offers a resistanceto
current flow. The resistance depends on VG .
Gate
Source Drain
Z
L′
G
p+
S D
G L
G
p+
S D
G L
n −Si
2a
n −Si
2a

Dr.R.P.Rao
3D v iew
* The n-type region betw een the top and bottom p+
regions offers a resistanceto
current flow. The resistance depends on VG .
* We w ill first consider the case, VD =VS =0 V.
Gate
Source Drain
Z
L′
G
p+
S D
G L
G
p+
S D
G L
n −Si
2a
n −Si
2a

JFET with VS = VD = 0V
Dr.R.P.Rao
a
neutral
depleted G p+
W
S h D
0 V 0V
G L
Vtt = 0 V Vtt =−1 V Vtt = −2 V
G
S
0V
D
0 V
G
G
S
0V
D
0 V
G

Dr.R.P.Rao
a
neutral
depleted G p+
W
S h D
0 V 0V
G L
Vtt = 0 V Vtt =−1 V Vtt = −2 V
* The bias across the p-n junction is (VG − VS ), i.e., VG , since VS = VD = 0 V .
G
S
0V
D
0 V
G
G
S
0V
D
0 V
G

Dr.R.P.Rao
a
neutral
depleted G p+ G
W
S h D S
G
D S D
0 V 0 V 0 V 0 V 0 V 0 V
G L
Vtt = 0 V
G
Vtt =−1 V
G
Vtt = −2 V
* The bias across the p-n junction is (VG − VS ), i.e., VG , since VS = VD = 0V.
* As the reverse bias across the junction is increased (by making VG more
negative), the depletion region w idens, and the resistance offered by the n-region
increases.

Dr.R.P.Rao
a
neutral
depleted G p+ G
W
S h D S
G
D S D
0 V 0 V 0 V 0 V 0 V 0 V
G L
Vtt = 0 V
G
Vtt =−1 V
G
Vtt = −2 V
* The bias across the p-n junction is (VG − VS ), i.e., VG , since VS = VD = 0V.
* As the reverse bias across the junction is increased (by making VG more
negative), the depletion region w idens, and the resistance offered by the n-region
increases.
* When the reverse bias becomes large enough, the depletion region consumes the
entire n-region. The corresponding VG is called the “pinch-off” voltage.

JFET: pinch-off voltage
Dr.R.P.Rao
neutral
G
depleted p+
W
S
a
h D
0 V 0V
G

Dr.R.P.Rao
* VP = VG for w hich h = 0, i.e., W =a.
neutral
depleted
G
p+
W
S
0V
a
h D
0V
G

Dr.R.P.Rao
s
* VP =VG for w hich h = 0, i.e., W = a.
* For a p+
-n junction, W =
2 s (Vbi − V )
, w here V
q Nd
bi is the built-in potential of
the junction.
neutral
depleted
G
p+
W
S
0V
a
h D
0V
G

Dr.R.P.Rao
s
s
* VP =VG for w hich h = 0, i.e., W = a.
* For a p+
-n junction, W =
2 s (Vbi − V )
, w here V
q Nd
bi is the built-in potential of
the junction.
* For pinch-off, W =a =
2 s (Vbi − V )
q Nd
⇒ VP = Vbi −
q Nd a2
.
2 s
neutral
depleted
G
p+
W
S
0V
a
h D
0V
G

Dr.R.P.Rao
* For pinch-off, W = a =
2 s (Vbi − V )
q Nd
⇒ VP = Vbi −
q Nd a2
.
2 s
neutral
depleted
G
p+
W
S
0V
a
h D
0V
G
s

Dr.R.P.Rao
2 s (Vbi − V )
q Nd
⇒ VP = Vbi −
q Nd a2
.
2 s
* Example: Nd = 2 × 1015
cm−3
, a = 1.5 µm, Vbi = 0.8 V .
neutral
depleted
G
p+
W
S
0V
a
h D
0V
G
s

Dr.R.P.Rao
2 s (Vbi − V )
q Nd
⇒ VP = Vbi −
q Nd a2
.
2 s
* Example: Nd = 2 × 1015
cm−3
, a = 1.5 µm, Vbi = 0.8 V .
(1.6 × 10−19
Coul)(2 × 1015
cm−3
)((1.5 × 10−4
)2
cm2
)
W = 0.8 −
2 × 11.7 × 8.85 × 10−14 F/cm
= 0.8 − 3.48 ≈ −2.7 V .
neutral
depleted
G
p+
W
S
0V
a
h D
0V
G
s

Dr.R.P.Rao
⇒ −
2 s (Vbi − V )
q Nd
⇒ VP = Vbi −
q Nd a2
.
2 s
* Example: Nd = 2 × 1015
cm−3
, a = 1.5 µm, Vbi = 0.8 V .
(1.6 × 10−19
Coul)(2 × 1015
cm−3
)((1.5 × 10−4
)2
cm2
)
W = 0.8 −
2 × 11.7 × 8.85 × 10−14 F/cm
= 0.8 − 3.48 ≈ −2.7 V .
If a gate voltage VG = 2.7 V is applied, the n-channelgets pinched off, and
the device resistance becomes very large.
neutral
depleted
G
p+
W
S
0V
a
h D
0V
G
s

JFET with VG = constant, VD ƒ= 0V
Dr.R.P.Rao
a
neutral
depleted G p+
W
S h D
0 V
G L
x
G
S
0V
D
G
G
S
0V
D
G
V (x) 1V
0V
ha
W
VD = 1 VVD = 0.05 VVD = 0 V

Dr.R.P.Rao
haha
W
neutral
depleted G p+ G
W
S D S
0 V 0 V
G L G
x
G
D S D
0 V
G
V (x) 1 V
0 V
* Consider an n-JFET w ith VG constant (and not in pinch-off mode).
VD = 1 VVD = 0.05 VVD = 0 V

Dr.R.P.Rao
haha
W
neutral
depleted G p+ G
W
S D S
0 V 0 V
G L G
x
G
D S D
0 V
G
V (x) 1 V
0 V
If a positive VD is applied, the potential V (x ) inside the channelfrom S to D
(along the dashed line) increases from0 Vto VD .
VD = 1 VVD = 0.05 VVD = 0 V

Dr.R.P.Rao
haha
W
neutral
depleted G p+ G
W
S D S
0 V 0 V
G L G
x
G
D S D
0 V
G
V (x) 1 V
0 V
Note that W and h are now functions of x such that, W (x ) + h(x ) = a.
VD = 1 VVD = 0.05 VVD = 0 V

Dr.R.P.Rao
haha
−
W
neutral
depleted G p+ G
W
S D S
0 V 0 V
G L G
x
G
D S D
0 V
G
V (x) 1 V
0 V
Note that W and h are now functions of x such that, W (x ) + h(x ) = a.
* Since the p-n junction bias at a given x is (VG V (x )), the drain end of the
channelhas a larger reverse bias than the source end.
VD = 1 VVD = 0.05 VVD = 0 V

Dr.R.P.Rao
⇒ the depletion region is w ider at the drain.

JFET: derivation of ID equation
Dr.R.P.Rao
ha
y G
S D
2 h
0 V
Z
G
V VD
Area = 2 h Z
0 V L x
W
x

Dr.R.P.Rao
ha
y G
S D
2 h
0 V
Z
G
V VD
Area = 2 h Z
0 V L x
Consider a slice of the dev ice. The current density at any point in the neutral region is assumed to
be in the x direction, and giv en by ,
dn dV
Jn = qµnnE + qDn
dx
≈ qµnnE = qµnNd
dx
,
W
x

Dr.R.P.Rao
ha
y G
S D
2 h
0 V
Z
G
V VD
Area = 2 h Z
0 V L x
dn dV
Jn = qµnnE + qDn
dx
≈ qµnnE = qµnNd
dx
,
dn
where we hav e neglected the dif f usion current, since n ≈ Nd ⇒
dx
= 0.
W
x

Dr.R.P.Rao
ha
y G
S D
2 h
0 V
Z
G
V VD
Area = 2 h Z
0 V L x
dn dV
Jn = qµnnE + qDn
dx
≈ qµnnE = qµnNd
dx
,
dn
dx
= 0.
Note that only the neutral part of the n-Si conducts since there are no carriers in the depletion
regions.
W
x

Dr.R.P.Rao
ha
y G
S D
2 h
0 V
Z
G
V VD
Area = 2 h Z
0 V L x
dn dV
Jn = qµnnE + qDn
dx
≈ qµnnE = qµnNd
dx
,
dn
dx
= 0.
regions.
At a given x, the current ID is obtained by integrating Jn ov er the area of the neutral channel
region (see f igure on the right). Since Jn is constant ov er this area,
W
x

Dr.R.P.Rao
ha
D n n d
dx
n d
dx a
y G
S D
2 h
0 V
Z
G
V VD
Area = 2 h Z
0 V L x
dn dV
Jn = qµnnE + qDn
dx
≈ qµnnE = qµnNd
dx
,
dn
dx
= 0.
regions.
At a given x, the current ID is obtained by integrating Jn ov er the area of the neutral channel
region (see f igure on the right). Since Jn is constant ov er this area,
I (x ) =
Z Z
J dx dz = 2hZ ×
„
qµ N
dV
«
= 2qZ µ N a
dV
„
1 −
W
«
,
W
x

Dr.R.P.Rao
where we hav e used h = a − W , i.e., h = a(1 − W /a).

Dr.R.P.Rao
ha
«
a
y G
dV
ID (x ) = 2 q Z µn Nd a
dx
S D
0 V
„
1 −
W
.
W
x
G

Dr.R.P.Rao
ha
«
s
Vbi − (VG − V )
a
y G
dV
dx
S D
0 V
„
1 −
W
.
Since ID (x ) is constant f rom x = 0 to x = L, we get,
Z L Z VD
s
2s
q !
where we hav e used, f or the depletion width W ,
W (x ) =
2s
qNd
[Vbi − (VG − V )] .
qNd a2
00
IDdx = ID L = 2qZ µnNd a
W
x
1 − dV ,
G

Dr.R.P.Rao
ha
«
s
Vbi − (VG − V )
VD −
3
(Vbi − VP )
a
y G
dV
dx
S D
0 V
„
1 −
W
.
Z L Z VD
s
2s
q !
W (x ) =
2s
qNd
[Vbi − (VG − V )] .
qNd a2
Ev aluating the integral and using Vbi − VP = , we get (do this!)
2s
(
2
"„
VD + Vbi − VG
«3/2 „
Vbi − VG
«3/2
#)
where G0 = 2qZ µnNd a/L.
PbiVPbiV
qNd a2
00
W
x
1 − dV ,
ID = G0
− V
−
− V
,
G

ha
«
s
Vbi − (VG − V )
VD −
3
(Vbi − VP )
a
y G
dV
dx
S D
0 V
„
1 −
W
.
Z L Z VD
s
2s
q !
W (x ) =
2s
qNd
[Vbi − (VG − V )] .
qNd a2
Ev aluating the integral and using Vbi − VP = , we get (do this!)
2s
(
2
"„
VD + Vbi − VG
«3/2 „
Vbi − VG
«3/2
#)
where G0 = 2qZ µnNd a/L.
Note that G0 is the channel conductance if there was no depletion, i.e., if h(x ) = a throughout the
channel.
PbiVPbiV
qNd a2
00
W
x
1 − dV ,
ID = G0
− V
−
− V
,
G

Special case: VD ≈ 0V
Dr.R.P.Rao
VD ≈ 0 V
a
VD −
3
(Vbi − VP )
neutral
depleted G p+
W
S h D
0 V
G L
(
2
"„
VD + Vbi − VG
«3/2
„
Vbi − VG
/2
#)
PbiVPbiV
y G
S
0V
D
G
x
ha
W
ID = G0
− V
−
− V

Dr.R.P.Rao
VD ≈ 0 V
a
VD −
3
(Vbi − VP )
− V − V
0
3 P
2
bi G
neutral
depleted G p+
W
S h D
0 V
G L
(
2
"„
VD + Vbi − VG
«3/2
„
Vbi − VG
«3/2
#)
≈ G V
2
− (V − V )−1/2
»
3
V (V − V )1/2
–ff
(using Taylor’s series)
PbiVPbiV
y G
S
0V
D
G
x
ha
W
ID = G0 −
D
bi D

Dr.R.P.Rao
VD ≈ 0 V
a
VD −
3
(Vbi − VP )
− V − V
0
3
P
2 bi G
1 −
Vbi P
neutral
depleted G p+
W
S h D
0 V
G L
(
2
"„
VD + Vbi − VG
«3/2
„
Vbi − VG
«3/2
#)
≈ G V
2
− (V − V )−1/2
»
3
V (V − V )1/2
–ff
( „
Vbi − VG
«1/2
)
PbiVPbiV
y G
S
0V
D
G
x
ha
W
ID = G0 −
D bi D
= G0VD
− V
.

Dr.R.P.Rao
VD ≈ 0 V
a
1/2
VD −
3
(Vbi − VP )
− V − V
0
3
P
2 bi G
1 −
Vbi P
neutral
depleted G p+
W
S h D
0 V
G L
(
2
"„
VD + Vbi − VG
«3/2
„
Vbi − VG
«3/2
#)
≈ G V
2
− (V − V )−1/2
»
3
V (V − V )1/2
–ff
( „
Vbi − VG
«1/2
)
2sSince W = (V
1/2 2s
− V ) , and a = (V
− V ) , we get
bi G
qNd
bi P
qNd
PbiVPbiV
y G
S
0V
D
G
x
ha
W
ID = G0 −
D bi D
= G0VD
− V
.

VD ≈ 0 V
a
1/2
a
VD −
3
(Vbi − VP )
− V − V
0
3
P
2 bi G
1 −
Vbi P
neutral
depleted G p+
W
S h D
0 V
G L
(
2
"„
VD + Vbi − VG
«3/2
„
Vbi − VG
«3/2
#)
≈ G V
2
− (V − V )−1/2
»
3
V (V − V )1/2
–ff
( „
Vbi − VG
«1/2
)
2sSince W = (V
1/2 2s
− V ) , and a = (V
− V ) , we get
bi G
qNd
bi P
qNd
ID = G0VD 1 −
W
f f
.
PbiVPbiV
y G
S
0V
D
G
x
ha
W
ID = G0 −
D bi D
= G0VD
− V
.

VD ≈ 0 V
a
1/2
a
VD −
3
(Vbi − VP )
− V − V
0
3
P
2 bi G
1 −
Vbi P
neutral
depleted G p+
W
S h D
0 V
G L
(
2
"„
VD + Vbi − VG
«3/2
„
Vbi − VG
«3/2
#)
≈ G V
2
− (V − V )−1/2
»
3
V (V − V )1/2
–ff
( „
Vbi − VG
«1/2
)
2sSince W = (V
1/2 2s
− V ) , and a = (V
− V ) , we get
bi G
qNd
bi P
qNd
ID = G0VD 1 −
W
f f
.
This simply shows that the channel conductance reduces linearly with W (as seen bef ore the
VS = VS = 0 V condition), and f or VG = VP (i.e., W = a), the conductance becomes zero.
PbiVPbiV
y G
S
0V
D
G
x
ha
W
ID = G0 −
D bi D
= G0VD
− V
.

JFET: pinch-off near drain
VD −
3
(Vbi − VP )
200
150
100
50
0
0
(
2
"„
VD + Vbi − VG
«3/2
1 2 3 4 5
VD (Volts)
„
Vbi − VG
«3/2
#)
PbiVPbiV
y G
S
0 V
D
G
x
h
a
W
Vtt =0 V
Vtt =−1 V
Vtt =−2 V
ID(µA)
ID = G0
− V
−
− V
.

−
VD −
3
(Vbi − VP )
200
150
100
50
0
0
(
2
"„
VD + Vbi − VG
«3/2
1 2 3 4 5
VD (Volts)
„
Vbi − VG
«3/2
#)
For a giv en VG , ID reaches a maximum at VD = VG VP (show this by dif f erentiating the abov e
equation).
PbiVPbiV
y G
S
0 V
D
G
x
h
a
W
Vtt =0 V
Vtt =−1 V
Vtt =−2 V
ID(µA)
ID = G0
− V
−
− V
.

−
VD −
3
(Vbi − VP )
200
150
100
50
0
0
(
2
"„
VD + Vbi − VG
«3/2
1 2 3 4 5
VD (Volts)
„
Vbi − VG
«3/2
#)
equation).
At this v alue of VD , the bias across the p-n junction at the drain end is VG − VD = VP .
PbiVPbiV
y G
S
0 V
D
G
x
h
a
W
Vtt =0 V
Vtt =−1 V
Vtt =−2 V
ID(µA)
ID = G0
− V
−
− V
.

−
−
VD −
3
(Vbi − VP )
200
150
100
50
0
0
(
2
"„
VD + Vbi − VG
«3/2
1 2 3 4 5
VD (Volts)
„
Vbi − VG
«3/2
#)
equation).
At this v alue of VD, the bias across the p-n junction at the drain end is VG VD = VP .
In other words, the drain end of the channel has just reached pinch-of f .
PbiVPbiV
y G
S
0 V
D
G
x
h
a
W
Vtt =0 V
Vtt =−1 V
Vtt =−2 V
ID(µA)
ID = G0
− V
−
− V
.

−
−
VD −
3
(Vbi − VP )
200
150
100
50
0
0
(
2
"„
VD + Vbi − VG
«3/2
1 2 3 4 5
VD (Volts)
„
Vbi − VG
«3/2
#)
equation).
G
S D
0 V pinch−off
G
PbiVPbiV
y G
S
0 V
D
G
x
h
a
W
Vtt =0 V
Vtt =−1 V
Vtt =−2 V
ID(µA)
ID = G0
− V
−
− V
.

−
−
VD −
3
(Vbi − VP )
200
150
100
50
0
0
(
2
"„
VD + Vbi − VG
«3/2
1 2 3 4 5
VD (Volts)
„
Vbi − VG
«3/2
#)
equation).
G
S
0 V
G
What happens if VD is increased f urther?
D
pinch−off
PbiVPbiV
y G
S
0 V
D
G
x
h
a
W
Vtt =0 V
Vtt =−1 V
Vtt =−2 V
ID(µA)
ID = G0
− V
−
− V
.

JFET: saturation
sat
D
DV < V
D tt
G G G
S D S D S
0V 0V 0V
G
A VD ≈ 0V
G G
B C
ID
C D
B
A
VD
V sat = V − V
Consider a f ixed VG with VD v ary ing f rom ∼ 0 V to a v alue bey ond condition C.
G
D S
0 V
D
G
D sat
D
DV > V
sat
D
DV = V
P

JFET: saturation
sat
D
DV < V
D tt
G G G
S D S D S
0V 0V 0V
G
A VD ≈ 0V
G G
B C
ID
C D
B
A
VD
V sat = V − V
In this situation, i.e., VD > V sat
, a short high-f ield region dev elops near the drain end, and the
“excess” v oltage, VD
sat
D
− VD drops across this region.
G
D S
0 V
D
G
D sat
D
DV > V
sat
D
DV = V
P

JFET: saturation
sat
D
DV < V
D tt
G G G
S D S D S
0V 0V 0V
G
A VD ≈ 0V
G G
B C
ID
C D
B
A
VD
V sat = V − V
sat
D
Because the high-f iled region is conf ined to a v ery small distance, the conditions in the dev ice are
almost identical in C and D.
G
D S
0 V
D
G
D sat
D
DV > V
sat
D
DV = V
P

JFET: saturation
sat
D
DV < V
D tt
G G G
S D S D S
0V 0V 0V
G
A VD ≈ 0V
G G
B C
ID
C D
B
A
VD
V sat = V − V
sat
D
⇒ The current in case D is almost the same as that f or case C.
G
D S
0 V
D
G
D sat
D
DV > V
sat
D
DV = V
P

JFET: saturation
sat
D
DV < V
D
D tt
G G G
S D S D S
0V 0V 0V
G
A VD ≈ 0V
G G
B C
ID
C D
B
A
VD
V sat = V − V
sat
D
⇒ The current in case D is almost the same as that f or case C.
The region VD > V sat
is theref ore called the “saturation region.”
G
D S
0 V
D
G
D sat
D
DV > V
sat
D
DV = V
P

JFET: example
D
An n-channel silicon JFET has the f ollowing parameters (at T = 300 K ): a = 1.5 µm, L = 5 µm,
Z = 50 µm, Nd = 2 × 1015
cm− 3
, Vbi = 0.8 V , µn = 300 cm2
/V -sec.
(a) What is the pinch-of f v oltage?
(b) Write a program to generate ID -VD characteristics f or VG = 0 V , −0.5 V , −1 V , −1.5 V ,
−2 V.
(c) For each of the abov e VG v alues, compute V sat
, and show it on the ID -VD plot. The part of
an I -V corresponding to V D
< V sat
D D D D is called the “linear” region, and that corresponding
to VD > V sat
is called the “saturation” region.

JFET: example
D
An n-channel silicon JFET has the f ollowing parameters (at T = 300 K ): a = 1.5 µm, L = 5 µm,
Z = 50 µm, Nd = 2 × 1015
cm− 3
, Vbi = 0.8 V , µn = 300 cm2
/V -sec.
(a) What is the pinch-of f v oltage?
(b) Write a program to generate ID -VD characteristics f or VG = 0 V , −0.5 V , −1 V , −1.5 V ,
−2 V.
(c) For each of the abov e VG v alues, compute V sat
, and show it on the ID -VD plot. The part of
an I -V corresponding to V D
< V sat
D D D D is called the “linear” region, and that corresponding
to VD > V sat
is called the “saturation” region.
Answer:
(a) VP =
(b)
200
150
100
50
0
0 1 2 3 4 5
VD (Volts)
−2.68 V.
linear saturation
Vtt =0 V
−0.5 V
−1 V
−1.5 V
−2 V
ID(µA)

JFET: simplified model for saturation
VD −
3
(Vbi − VP )
(
2
"„
VD + Vbi − VG
«3/2 „
Vbi − VG
«3/2
#)
PbiVPbiVID = G0
− V
−
− V
.

D
VD −
3
(Vbi − VP )
ID = G0 VD −
3
(Vbi − VP )
(
2
"„
VD + Vbi − VG
«3/2 „
Vbi − VG
«3/2
#)
At saturtation, V sat
= VG − VP , giv ing
sat
(
2 " „
Vbi − VG
«3/2
#)
PbiV
PbiVPbiV
ID = G0
− V
−
− V
.
1 −
− V
.

D
VD −
3
(Vbi − VP )
ID = G0 VD −
3
(Vbi − VP )
D D
(
2
"„
VD + Vbi − VG
«3/2 „
Vbi − VG
«3/2
#)
sat
(
2 " „
Vbi − VG
«3/2
#)
The f ollowing approximate model is f ound to be adequate in circuit design:
I sat
(VG ) = IDSS (1 − VG /VP )2
, where IDSS = I sat
(VG = 0 V ).
PbiV
PbiVPbiV
ID = G0
− V
−
− V
.
1 −
− V
.

D
VD −
3
(Vbi − VP )
ID = G0 VD −
3
(Vbi − VP )
(
2
"„
VD + Vbi − VG
«3/2 „
Vbi − VG
«3/2
#)
sat
(
2 " „
Vbi − VG
«3/2
#)
I sat
(VG ) = IDSS (1 − VG /VP )2
(VG = 0 V ).
D
In amplif ier design, we are interested in g
D
∂ID
= , which is obtained as:
G
PbiV
PbiVPbiV
˛
ID = G0
− V
−
− V
.
1 −
− V
.
m
∂V ˛
VD=constant

D
˛
VD −
3
(Vbi − VP )
ID = G0 VD −
3
(Vbi − VP )
(
2
"„
VD + Vbi − VG
«3/2 „
Vbi − VG
«3/2
#)
sat
(
2 " „
Vbi − VG
«3/2
#)
I sat
(VG ) = IDSS (1 − VG /VP )2
(VG = 0 V ).
D
In amplif ier design, we are interested in g
D
∂ID= , which is obtained as:
gm = gm0 (1 − VG /VP ),
m
∂VG
˛
VD =constant
where gm0 = −2IDSS /VP = gm(VG = 0 V ).
PbiV
PbiVPbiV
ID = G0
− V
−
− V
.
1 −
− V
.

JFET: source/drain resistances
S′ D′
G
(Not drawn to scale. Typically, L ≫ 2a.)
RS RD
G p+
S D
G L
n −Si
2a
S D

JFET: source/drain resistances
S′ D′
G
(Not drawn to scale. Typically, L ≫ 2a.)
Cro ss − s e ct io n a l view
In real JFETs, there is a separation between the source/drain contacts and the activ e channel.
The n-ty pe semiconductor regions between the activ e channel and the source/drain contacts can
be modelled by resistances RS and RD .
RS RD
G p+
S D
G L
n −Si
2a
S D

JFET: small-signal model
VDD
D R R
D
Vo
1 V2
Rtt
S
S
Rtt
VSS
Amplifier example
* A small-signal model of a JFET is required in analy sis of an amplif ier.
G
vg
Cgd
Cgs gd
gmvg
G
V

VDD
D R R
D
Vo
1 V2
Rtt
S
S
Rtt
VSS
Amplifier example
* The DC gate current, which is the rev erse current of a p-n junction, is generally insignif icant
and is theref ore ignored.
G
vg
Cgd
Cgs gd
gmvg
G
V

VDD
D R R
D
Vo
1 V2
Rtt
S
S
Rtt
VSS
Amplifier example
∂ID
* gm =
∂VG
with VD = constant.
G
vg
Cgd
Cgs gd
gmvg
G
V

VDD
D R R
D
Vo
1 V2
Rtt
S
S
Rtt
VSS
Amplifier example
∂ID
* gm =
* gd =
∂VG
∂ID
∂VD
with VD = constant.
with VG = constant.
G
vg
Cgd
Cgs gd
gmvg
G
V

saturation. Howev er, a real dev ice would show a small increase in ID with an increase in VD
in saturation, giv ing rise to a non-zero gd .
VDD
D R R
D
Vo
1 V2
Rtt
S
S
Rtt
VSS
Amplifier example
∂ID
* gm =
* gd =
∂VG
∂ID
∂VD
with VD = constant.
with VG = constant.
* gm and gd can be obtained by dif ferentiating ID (VG , VD ). Note that, in our simple model,
short-channel ef f ects have not been included; we would theref ore obtain gd = 0 ¥ in
G
vg
Cgd
Cgs gd
gmvg
G
V

saturation. Howev er, a real dev ice would show a small increase in ID with an increase in VD
in saturation, giv ing rise to a non-zero gd .
* The capacitances Cgs and Cgd are depletion capacitances of the p-n junction.
VDD
D R R
D
Vo
1 V2
Rtt
S
S
Rtt
VSS
Amplifier example
∂ID
* gm =
* gd =
∂VG
∂ID
∂VD
with VD = constant.
with VG = constant.
* gm and gd can be obtained by dif ferentiating ID (VG , VD ). Note that, in our simple model,
short-channel ef f ects have not been included; we would theref ore obtain gd = 0 ¥ in
G
vg
Cgd
Cgs gd
gmvg
G
V

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